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zbao7d94cf92012-07-02 14:19:14 +08001/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * AMD Family_15 Trinity Power Management related registers defination
6 *
7 * @xrefitem bom "File Content Label" "Release Content"
8 * @e project: AGESA
9 * @e sub-project: CPU/Family/0x15/TN
10 * @e \$Revision: 63661 $ @e \$Date: 2012-01-03 01:02:47 -0600 (Tue, 03 Jan 2012) $
11 *
12 */
13/*
14 ******************************************************************************
15 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080016 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
17 * All rights reserved.
zbao7d94cf92012-07-02 14:19:14 +080018 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080019 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
zbao7d94cf92012-07-02 14:19:14 +080029 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080030 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +080040 ******************************************************************************
41 */
42
43#ifndef _CPU_F15_TN_POWERMGMT_H_
44#define _CPU_F15_TN_POWERMGMT_H_
45
46/*
47 * Family 15h Trinity CPU Power Management MSR definitions
48 *
49 */
50
51
52/* Interrupt Pending and CMP-Halt MSR Register 0xC0010055 */
53#define MSR_INTPEND 0xC0010055ul
54
55/// Interrupt Pending and CMP-Halt MSR Register
56typedef struct {
57 UINT64 IoMsgAddr:16; ///< IO message address
58 UINT64 Intpend1 :8;
59 UINT64 Intpend2 :1;
60 UINT64 Intpend3 :1;
61 UINT64 Intpend4 :1;
62 UINT64 :37; ///< Reserved
63} INTPEND_MSR;
64
65/* P-state Registers 0xC00100[6B:64] */
66
67/// P-state MSR
68typedef struct {
69 UINT64 CpuFid:6; ///< CpuFid
70 UINT64 CpuDid:3; ///< CpuDid
71 UINT64 CpuVid:8; ///< CpuVid
72 UINT64 :5; ///< Reserved
73 UINT64 NbPstate:1; ///< NbPstate
74 UINT64 :9; ///< Reserved
75 UINT64 IddValue:8; ///< IddValue
76 UINT64 IddDiv:2; ///< IddDiv
77 UINT64 :21; ///< Reserved
78 UINT64 PsEnable:1; ///< Pstate Enable
79} PSTATE_MSR;
80
81#define GetF15TnCpuVid(PstateMsr) (((PSTATE_MSR *) PstateMsr)->CpuVid)
82
83
84/* VID operation related macros */
85#define ConvertVidInuV(Vid) (1550000 - (6250 * Vid)) ///< Convert VID in uV.
86
87/* COFVID Control Register 0xC0010070 */
88#define MSR_COFVID_CTL 0xC0010070ul
89
90/// COFVID Control MSR Register
91typedef struct {
92 UINT64 CpuFid:6; ///< CpuFid
93 UINT64 CpuDid:3; ///< CpuDid
94 UINT64 CpuVid_6_0:7; ///< CpuVid[6:0]
95 UINT64 PstateId:3; ///< Pstate ID
96 UINT64 :1; ///< Reserved
97 UINT64 CpuVid_7:1; ///< CpuVid[7]
98 UINT64 :1; ///< Reserved
99 UINT64 NbPstate:1; ///< Northbridge P-state
100 UINT64 :1; ///< Reserved
101 UINT64 NbVid:8; ///< NbVid
102 UINT64 :32; ///< Reserved
103} COFVID_CTRL_MSR;
104
105#define COFVID_CTRL_MSR_CurCpuVid_6_0_OFFSET 9
106#define COFVID_CTRL_MSR_CurCpuVid_6_0_WIDTH 7
107#define COFVID_CTRL_MSR_CurCpuVid_6_0_MASK 0xfe00
108#define COFVID_CTRL_MSR_CurCpuVid_7_OFFSET 20
109#define COFVID_CTRL_MSR_CurCpuVid_7_WIDTH 1
110#define COFVID_CTRL_MSR_CurCpuVid_7_MASK 0x100000ul
111
112/* SVI VID Encoding */
113
114///< Union structure of VID in SVI1/SVI2 modes
115typedef union {
116 UINT32 RawVid; ///< Raw VID value
117 struct { ///< SVI2 mode VID structure
118 UINT32 Vid_6_0:7; ///< Vid[6:0] of SVI2 mode
119 UINT32 Vid_7:1; ///< Vid[7] of SVI2 mode
120 } SVI2;
121 struct { ///< SVI1 mode VID structure
122 UINT32 Vid_LSB_Ignore:1; ///< Ignored LSB of 8bit VID encoding in SVI1 mode
123 UINT32 Vid_6_0:1; ///< Vid[6:0] of SVI mode
124 } SVI1;
125} SVI_VID;
126
127
128#define SetF15TnCpuVid(CofVidStsMsr, NewCpuVid) ( \
129 ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_6_0) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_6_0; \
130 ((COFVID_CTRL_MSR *) CofVidStsMsr)->CurCpuVid_7) = ((SVI_VID *) NewCpuVid)->SVI2.Vid_7; \
131)
132
133
134/* COFVID Status Register 0xC0010071 */
135#define MSR_COFVID_STS 0xC0010071ul
136
137/// COFVID Status MSR Register
138typedef struct {
139 UINT64 CurCpuFid:6; ///< Current CpuFid
140 UINT64 CurCpuDid:3; ///< Current CpuDid
141 UINT64 CurCpuVid_6_0:7; ///< Current CpuVid[6:0]
142 UINT64 CurPstate:3; ///< Current Pstate
143 UINT64 :1; ///< Reserved
144 UINT64 CurCpuVid_7:1; ///< Current CpuVid[7]
145 UINT64 :2; ///< Reserved
146 UINT64 NbPstateDis:1; ///< NbPstate Disable
147 UINT64 CurNbVid:8; ///< Current NbVid[7:0] <<<------- check where use it
148 UINT64 StartupPstate:3; ///< Startup Pstate
149 UINT64 :14; ///< Reserved
150 UINT64 MaxCpuCof:6; ///< MaxCpuCof
151 UINT64 :1; ///< Reserved
152 UINT64 CurPstateLimit:3; ///< Current Pstate Limit
153 UINT64 MaxNbCof:5; ///< MaxNbCof
154} COFVID_STS_MSR;
155
156#define COFVID_STS_MSR_CurCpuVid_6_0_OFFSET 9
157#define COFVID_STS_MSR_CurCpuVid_6_0_WIDTH 7
158#define COFVID_STS_MSR_CurCpuVid_6_0_MASK 0xfe00
159#define COFVID_STS_MSR_CurCpuVid_7_OFFSET 20
160#define COFVID_STS_MSR_CurCpuVid_7_WIDTH 1
161#define COFVID_STS_MSR_CurCpuVid_7_MASK 0x100000ul
162
163#define GetF15TnCurCpuVid(CofVidStsMsr) ( \
164 (((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_7 << COFVID_STS_MSR_CurCpuVid_6_0_WIDTH) \
165 | ((COFVID_STS_MSR *) CofVidStsMsr)->CurCpuVid_6_0)
166
167
168/* Floating Point Configuration Register 0xC0011028 */
169#define MSR_FP_CFG 0xC0011028ul
170
171/// Floating Point Configuration MSR Register
172typedef struct {
173 UINT64 :16; ///< Reserved
174 UINT64 DiDtMode:1; ///< Di/Dt Mode
175 UINT64 :1; ///< Reserved
176 UINT64 DiDtCfg0:5; ///< Di/Dt Config 0
177 UINT64 :2; ///< Reserved
178 UINT64 DiDtCfg2:2; ///< Di/Dt Config 2
179 UINT64 DiDtCfg1:8; ///< Di/Dt Config 1
180 UINT64 :6; ///< Reserved
181 UINT64 DiDtCfg5:1; ///< Di/Dt Config 5
182 UINT64 DiDtCfg4:3; ///< Di/Dt Config 4
183 UINT64 :19; ///< Reserved
184} FP_CFG_MSR;
185
186/* Load-Store Configuration 2 0xC001102D */
187
188/// Load-Store Configuration 2 MSR Register
189typedef struct {
190 UINT64 :14; ///< Reserved
191 UINT64 ForceSmcCheckFlwStDis:1; ///< ForceSmcCheckFlwStDis
192 UINT64 :8; ///< Reserved
193 UINT64 DisScbThreshold:1; ///< DisScbThreshold
194 UINT64 :40; ///< Reserved
195} LS_CFG2_MSR;
196
197/*
198 * Family 15h Trinity CPU Power Management PCI definitions
199 *
200 */
201
202
203/* DRAM Configuration High Register F2x[1,0]94 */
204#define DRAM_CFG_HI_REG0 0x94
205#define DRAM_CFG_HI_REG1 0x194
206
207/// DRAM Configuration High PCI Register
208typedef struct {
209 UINT32 MemClkFreq:5; ///< Memory clock frequency
210 UINT32 :2; ///< Reserved
211 UINT32 MemClkFreqVal:1; ///< Memory clock frequency valid
212 UINT32 :2; ///< Reserved
213 UINT32 ZqcsInterval:2; ///< ZQ calibration short interval
214 UINT32 :2; ///< Reserved
215 UINT32 DisDramInterface:1; ///< Disable the DRAM interface
216 UINT32 PowerDownEn:1; ///< Power down mode enable
217 UINT32 PowerDownMode:1; ///< Power down mode
218 UINT32 :2; ///< Reserved
219 UINT32 DcqArbBypassEn:1; ///< DRAM controller arbiter bypass enable
220 UINT32 SlowAccessMode:1; ///< Slow access mode
221 UINT32 FreqChgInProg:1; ///< Frequency change in progress
222 UINT32 BankSwizzleMode:1; ///< Bank swizzle mode
223 UINT32 ProcOdtDis:1; ///< Processor on-die termination disable
224 UINT32 DcqBypassMax:5; ///< DRAM controller queue bypass maximum
225 UINT32 :3; ///< Reserved
226} DRAM_CFG_HI_REGISTER;
227
228/* DCT Configuration Select D18F1x10C */
229#define DCT_CFG_SEL_REG 0x10C
230#define DCT_CFG_SEL_REG_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_1, DCT_CFG_SEL_REG))
231
232/// DCT Configuration Select
233typedef struct {
234 UINT32 DctCfgSel:1; ///< DRAM controller configuration select
235 UINT32 :31; ///< Reserved
236} DCT_CFG_SEL_REGISTER;
237
238
239/* GMC to DCT Control 2 D18F2x408_dct[1:0] */
240#define GMC_TO_DCT_CTL_2_REG 0x408
241#define GMC_TO_DCT_CTL_2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_2, GMC_TO_DCT_CTL_2_REG))
242
243/// GMC to DCT Control 2 PCI Register
244typedef struct {
245 UINT32 CpuElevPrioDis:1; ///< Cpu elevate priority disable
Rudolf Marekc805e622014-07-07 22:16:36 +0200246 UINT32 Reserved_30_1:30; ///<
247 UINT32 DisHalfNclkPwrGate:1; ///<
zbao7d94cf92012-07-02 14:19:14 +0800248} GMC_TO_DCT_CTL_2_REGISTER;
249
250
251/* Power Control Miscellaneous Register F3xA0 */
252#define PW_CTL_MISC_REG 0xA0
253#define PW_CTL_MISC_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PW_CTL_MISC_REG))
254
255/// Power Control Miscellaneous PCI Register
256typedef struct {
257 UINT32 PsiVid:7; ///< PSI_L VID threshold VID[6:0]
258 UINT32 PsiVidEn:1; ///< PSI_L VID enable
259 UINT32 PsiVid_7:1; ///< PSI_L VID threshold VID[7]
260 UINT32 :2; ///< Reserved
261 UINT32 PllLockTime:3; ///< PLL synchronization lock time
262 UINT32 Svi2HighFreqSel:1; ///< SVI2 high frequency select
263 UINT32 :1; ///< Reserved
264 UINT32 ConfigId:12; ///< Configuration ID
265 UINT32 :3; ///< Reserved
266 UINT32 CofVidProg:1; ///< COF and VID of Pstate programmed
267} POWER_CTRL_MISC_REGISTER;
268
269
270/* Clock Power/Timing Control 0 Register F3xD4 */
271#define CPTC0_REG 0xD4
272#define CPTC0_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC0_REG))
273
274/// Clock Power Timing Control PCI Register
275typedef struct {
276 UINT32 MaxSwPstateCpuCof:6; ///< Maximum software P-state core COF
277 UINT32 :2; ///< Reserved
278 UINT32 ClkRampHystSel:4; ///< Clock Ramp Hysteresis Select
279 UINT32 ClkRampHystCtl:1; ///< Clock Ramp Hysteresis Control
280 UINT32 :1; ///< Reserved
281 UINT32 CacheFlushImmOnAllHalt:1; ///< Cache Flush Immediate on All Halt
282 UINT32 :1; ///< Reserved
283 UINT32 clkpwr0 :2;
284 UINT32 :2; ///< Reserved
285 UINT32 PowerStepDown:4; ///< Power Step Down
286 UINT32 PowerStepUp:4; ///< Power Step Up
287 UINT32 NbClkDiv:3; ///< NbClkDiv
288 UINT32 NbClkDivApplyAll:1; ///< NbClkDivApplyAll
289} CLK_PWR_TIMING_CTRL_REGISTER;
290
291
292/* Clock Power/Timing Control 1 Register F3xD8 */
293#define CPTC1_REG 0xD8
294#define CPTC1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, CPTC1_REG))
295
296/// Clock Power Timing Control 1 PCI Register
297typedef struct {
298 UINT32 :4; ///< Reserved
299 UINT32 VSRampSlamTime:3; ///< Voltage stabilization ramp time
300 UINT32 :25; ///< Reserved
301} CLK_PWR_TIMING_CTRL1_REGISTER;
302
303
304/* Northbridge Capabilities Register F3xE8 */
305#define NB_CAPS_REG 0xE8
306#define NB_CAPS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, NB_CAPS_REG))
307
308/// Northbridge Capabilities PCI Register
309typedef struct {
310 UINT32 :1; ///< Reserved
311 UINT32 DualNode:1; ///< Dual-node multi-processor capable
312 UINT32 EightNode:1; ///< Eight-node multi-processor capable
313 UINT32 Ecc:1; ///< ECC capable
314 UINT32 Chipkill:1; ///< Chipkill ECC capable
315 UINT32 :3; ///< Reserved
316 UINT32 MctCap:1; ///< Memory controller capable
317 UINT32 SvmCapable:1; ///< SVM capable
318 UINT32 HtcCapable:1; ///< HTC capable
319 UINT32 :3; ///< Reserved
320 UINT32 MultVidPlane:1; ///< Multiple VID plane capable
321 UINT32 :4; ///< Reserved
322 UINT32 x2Apic:1; ///< x2Apic capability
323 UINT32 :4; ///< Reserved
324 UINT32 MemPstateCap:1; ///< Memory P-state capable
325 UINT32 L3Capable:1; ///< L3 capable
326 UINT32 :6; ///< Reserved
327} NB_CAPS_REGISTER;
328
329
330/* Product Info Register F3x1FC */
331#define PRCT_INFO_REG 0x1FC
332#define PRCT_INFO_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_3, PRCT_INFO_REG))
333
334/// Product Information PCI Register
335typedef struct {
336 UINT32 DiDtMode:1; ///< DiDtMode
337 UINT32 DiDtCfg0:5; ///< DiDtCfg0
338 UINT32 DiDtCfg1:8; ///< DiDtCfg1
339 UINT32 DiDtCfg2:2; ///< DiDtCfg2
340 UINT32 :1; ///< Reserved
341 UINT32 DiDtCfg4:3; ///< DiDtCfg4
342 UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit
343 UINT32 :1; ///< Reserved
344 UINT32 DiDtCfg5:1; ///< DiDtCfg5
345 UINT32 ForceSmcCheckFlwStDis:1; ///< ForceSmcCheckFlwStDis
346 UINT32 SWDllCapTableEn:1; ///< SWDllCapTableEn
347 UINT32 DllProcessFreqCtlIndex2Rate50:4; ///< DllProcessFreqCtlIndex2Rate50
348 UINT32 EnDcqChgPriToHigh:1; ///< EnDcqChgPriToHigh
349 UINT32 :2; ///< Reserved
350} PRODUCT_INFO_REGISTER;
351
352
353/* C-state Control 1 Register D18F4x118 */
354#define CSTATE_CTRL1_REG 0x118
355#define CSTATE_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL1_REG))
356
357/// C-state Control 1 Register
358typedef struct {
359 UINT32 CpuPrbEnCstAct0:1; ///< Core direct probe enable
360 UINT32 CacheFlushEnCstAct0:1; ///< Cache flush enable
361 UINT32 CacheFlushTmrSelCstAct0:2; ///< Cache flush timer select
362 UINT32 :1; ///< Reserved
363 UINT32 ClkDivisorCstAct0:3; ///< Clock divisor
364 UINT32 PwrGateEnCstAct0:1; ///< Power gate enable
365 UINT32 PwrOffEnCstAct0:1; ///< C-state action field 3
366 UINT32 NbPwrGate0:1; ///< NB power-gating 0
367 UINT32 NbClkGate0:1; ///< NB clock-gating 0
368 UINT32 SelfRefr0:1; ///< Self-refresh 0
369 UINT32 SelfRefrEarly0:1; ///< Allow early self-refresh 0
370 UINT32 :2; ///< Reserved
371 UINT32 CpuPrbEnCstAct1:1; ///< Core direct probe enable
372 UINT32 CacheFlushEnCstAct1:1; ///< Cache flush eable
373 UINT32 CacheFlushTmrSelCstAct1:2; ///< Cache flush timer select
374 UINT32 :1; ///< Reserved
375 UINT32 ClkDivisorCstAct1:3; ///< Clock divisor
376 UINT32 PwrGateEnCstAct1:1; ///< Power gate enable
377 UINT32 PwrOffEnCstAct1:1; ///< C-state action field 3
378 UINT32 NbPwrGate1:1; ///< NB power-gating 1
379 UINT32 NbClkGate1:1; ///< NB clock-gating 1
380 UINT32 SelfRefr1:1; ///< Self-refresh 1
381 UINT32 SelfRefrEarly1:1; ///< Allow early self-refresh 1
382 UINT32 :2; ///< Reserved
383} CSTATE_CTRL1_REGISTER;
384
385
386/* C-state Control 2 Register D18F4x11C */
387#define CSTATE_CTRL2_REG 0x11C
388#define CSTATE_CTRL2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_CTRL2_REG))
389
390/// C-state Control 2 Register
391typedef struct {
392 UINT32 CpuPrbEnCstAct2:1; ///< Core direct probe enable
393 UINT32 CacheFlushEnCstAct2:1; ///< Cache flush eable
394 UINT32 CacheFlushTmrSelCstAct2:2; ///< Cache flush timer select
395 UINT32 cstate0 :1;
396 UINT32 ClkDivisorCstAct2:3; ///< Clock divisor
397 UINT32 PwrGateEnCstAct2:1; ///< Power gate enable
398 UINT32 PwrOffEnCstAct2:1; ///< C-state action field 3
399 UINT32 NbPwrGate2:1; ///< NB power-gating 2
400 UINT32 NbClkGate2:1; ///< NB clock-gating 2
401 UINT32 SelfRefr2:1; ///< Self-refresh 2
402 UINT32 SelfRefrEarly2:1; ///< Allow early self-refresh 2
403 UINT32 :18; ///< Reserved
404} CSTATE_CTRL2_REGISTER;
405
406
407/* Cstate Policy Control 1 Register D18F4x128 */
408#define CSTATE_POLICY_CTRL1_REG 0x128
409#define CSTATE_POLICY_CTRL1_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, CSTATE_POLICY_CTRL1_REG))
410
411/// Cstate Policy Control 1 Register
412typedef struct {
413 UINT32 cstplyc0 :1;
414 UINT32 CoreCstatePolicy:1; ///< Specified processor arbitration of voltage and frequency
415 UINT32 HaltCstateIndex:3; ///< Specifies the IO-based C-state that is invoked by a HLT instruction
416 UINT32 CacheFlushTmr:7; ///< Cache flush timer
417 UINT32 :6; ///< Reserved
418 UINT32 CacheFlushSucMonThreshold:3; ///< Cache flush success monitor threshold
419 UINT32 :10; ///< Reserved
420 UINT32 CstateMsgDis:1; ///< C-state messaging disable
421} CSTATE_POLICY_CTRL1_REGISTER;
422
423
424/* Core Performance Boost Control Register D18F4x15C */
425
426/// Core Performance Boost Control Register
427typedef struct {
428 UINT32 BoostSrc:2; ///< Boost source
429 UINT32 NumBoostStates:3; ///< Number of boosted states
430 UINT32 :2; ///< Reserved
431 UINT32 ApmMasterEn:1; ///< APM master enable
432 UINT32 :23; ///< Reserved
433 UINT32 BoostLock:1; ///<
434} CPB_CTRL_REGISTER;
435
436
437/* Northbridge Capabilities 2 F5x84*/
438#define NB_CAPS_REG2 0x84
439#define NB_CAPS_REG2_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CAPS_REG2))
440
441/// Northbridge Capabilities 2 PCI Register
442typedef struct {
443 UINT32 CmpCap:8; ///< CMP capable
444 UINT32 :4; ///< Reserved
445 UINT32 DctEn:2; ///< DCT enabled
446 UINT32 :2; ///< Reserved
447 UINT32 DdrMaxRate:5; ///< maximum DDR rate
448 UINT32 :3; ///< Reserved
449 UINT32 DdrMaxRateEnf:5; ///< enforced maximum DDR rate:
450 UINT32 :3; ///< Reserved
451} NB_CAPS_2_REGISTER;
452
453/* Northbridge Configuration 4 F5x88*/
454#define NB_CFG_REG4 0x88
455#define NB_CFG_REG4_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_CFG_REG4))
456
457/// Northbridge Configuration 4 PCI Register
458typedef struct {
459 UINT32 :2; ///< Reserved
460 UINT32 IntStpClkHaltExitEn:1; ///< IntStpClkHaltExitEn
461 UINT32 :11; ///< Reserved
462 UINT32 Bit14:1; ///< Reserved
463 UINT32 :3; ///< Reserved
464 UINT32 EnCstateBoostBlockCC6Exit:1;///< EnCstateBoostBlockCC6Exit
465 UINT32 :13; ///< Reserved
466} NB_CFG_4_REGISTER;
467
468/* Northbridge P-state [3:0] F5x1[6C:60] */
469
470/// Northbridge P-state Register
471typedef struct {
472 UINT32 NbPstateEn:1; ///< NB P-state enable
473 UINT32 NbFid:6; ///< NB frequency ID
474 UINT32 NbDid:1; ///< NB divisor ID
475 UINT32 :2; ///< Reserved
476 UINT32 NbVid_6_0:7; ///< NB VID[6:0]
477 UINT32 :1; ///< Reserved
478 UINT32 MemPstate:1; ///< Memory P-State
479 UINT32 :2; ///< Reserved
480 UINT32 NbVid_7:1; ///< NB VID[7]
481 UINT32 NbIddDiv:2; ///< northbridge current divisor
482 UINT32 NbIddValue:8; ///< northbridge current value
483} NB_PSTATE_REGISTER;
484
485#define NB_PSTATE_REGISTER_NbVid_6_0_OFFSET 10
486#define NB_PSTATE_REGISTER_NbVid_6_0_WIDTH 7
487#define NB_PSTATE_REGISTER_NbVid_6_0_MASK 0x0001FC00ul
488#define NB_PSTATE_REGISTER_NbVid_7_OFFSET 21
489#define NB_PSTATE_REGISTER_NbVid_7_WIDTH 1
490#define NB_PSTATE_REGISTER_NbVid_7_MASK 0x00200000ul
491
492#define GetF15TnNbVid(NbPstateRegister) ( \
493 (((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 << NB_PSTATE_REGISTER_NbVid_6_0_WIDTH) \
494 | ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0)
495
496#define SetF15TnNbVid(NbPstateRegister, NewNbVid) { \
497 ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_6_0 = ((SVI_VID *) NewNbVid)->SVI2.Vid_6_0; \
498 ((NB_PSTATE_REGISTER *) NbPstateRegister)->NbVid_7 = ((SVI_VID *) NewNbVid)->SVI2.Vid_7; \
499}
500
501/* Northbridge P-state Status */
502#define NB_PSTATE_CTRL 0x170
503#define NB_PSTATE_CTRL_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_CTRL))
504
505/// Northbridge P-state Control Register
506typedef struct {
507 UINT32 NbPstateMaxVal:2; ///< NB P-state maximum value
508 UINT32 :1; ///< Reserved
509 UINT32 NbPstateLo:2; ///< NB P-state low
510 UINT32 :1; ///< Reserved
511 UINT32 NbPstateHi:2; ///< NB P-state high
512 UINT32 :1; ///< Reserved
513 UINT32 NbPstateThreshold:3; ///< NB P-state threshold
514 UINT32 :1; ///< Reserved
515 UINT32 NbPstateDisOnP0:1; ///< NB P-state disable on P0
516 UINT32 SwNbPstateLoDis:1; ///< Software NB P-state low disable
517 UINT32 :8; ///< Reserved
518 UINT32 NbPstateGnbSlowDis:1; ///< Disable NB P-state transition take GnbSlow into account.
519 UINT32 NbPstateLoRes:3; ///< NB P-state low residency timer
520 UINT32 NbPstateHiRes:3; ///< NB P-state high residency timer
521 UINT32 :1; ///< Reserved
522 UINT32 MemPstateDis:1; ///< Memory P-state disable
523} NB_PSTATE_CTRL_REGISTER;
524
525
526/* Northbridge P-state Status */
527#define NB_PSTATE_STATUS 0x174
528#define NB_PSTATE_STATUS_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, NB_PSTATE_STATUS))
529
530/// Northbridge P-state Status Register
531typedef struct {
532 UINT32 NbPstateDis:1; ///< Nb pstate disable
533 UINT32 StartupNbPstate:2; ///< startup northbridge Pstate number
534 UINT32 CurNbFid:6; ///< Current NB FID
535 UINT32 CurNbDid:1; ///< Current NB DID
536 UINT32 :2; ///< Reserved
537 UINT32 CurNbVid_6_0:7; ///< Current NB VID[6:0]
538 UINT32 CurNbPstate:2; ///< Current NB Pstate
539 UINT32 :2; ///< Reserved
540 UINT32 CurNbVid_7:1; ///< Current NB VID[7]
541 UINT32 CurMemPstate:1; ///< Current memory P-state
542 UINT32 :7; ///< Reserved
543} NB_PSTATE_STS_REGISTER;
544
545#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_OFFSET 12
546#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH 7
547#define NB_PSTATE_STS_REGISTER_CurNbVid_6_0_MASK 0x0007F000ul
548#define NB_PSTATE_STS_REGISTER_CurNbVid_7_OFFSET 23
549#define NB_PSTATE_STS_REGISTER_CurNbVid_7_WIDTH 1
550#define NB_PSTATE_STS_REGISTER_CurNbVid_7_MASK 0x00800000ul
551
552#define GetF15TnCurNbVid(NbPstateStsRegister) ( \
553 (((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_7 << NB_PSTATE_STS_REGISTER_CurNbVid_6_0_WIDTH) \
554 | ((NB_PSTATE_STS_REGISTER *) NbPstateStsRegister)->CurNbVid_6_0)
555
556/* Miscellaneous Voltages */
557#define MISC_VOLTAGES 0x17C
558#define MISC_VOLTAGES_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, MISC_VOLTAGES))
559
560/// Miscellaneous Voltages Register
561typedef struct {
562 UINT32 MaxVid:8; ///< Maximum Voltage
563 UINT32 :2; ///< Reserved
564 UINT32 MinVid:8; ///< Minimum Voltage
565 UINT32 :5; ///< Reserved
566 UINT32 NbPsi0Vid:8; ///< Northbridge PSI0_L VID threshold
567 UINT32 NbPsi0VidEn:1; ///< Northbridge PSI0_L VID enable
568} MISC_VOLTAGE_REGISTER;
569
570
571/* Clock Power/Timing Control 5 Register F5x188 */
572#define CPTC5_REG 0x188
573#define CPTC5_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_5, CPTC5_REG))
574
575/// Clock Power Timing Control 5 Register
576typedef struct {
577 UINT32 NbOffsetTrim:2; ///< Northbridge offset trim
578 UINT32 NbLoadLineTrim:3; ///< Northbridge load line trim
579 UINT32 NbPsi1:1; ///< Northbridge PSI1_L
580 UINT32 :26; ///< Reserved
581} CLK_PWR_TIMING_CTRL_5_REGISTER;
582
583#endif /* _CPU_F15_TN_POWERMGMT_H_ */