blob: 59fe8c1bcaa9f62012a55baba1624d78c02a1dec [file] [log] [blame]
zbao7d94cf92012-07-02 14:19:14 +08001/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * AMD Family_15 Trinity PCI tables with values as defined in BKDG
6 *
7 * @xrefitem bom "File Content Label" "Release Content"
8 * @e project: AGESA
9 * @e sub-project: CPU/Family/0x15/TN
10 * @e \$Revision: 64462 $ @e \$Date: 2012-01-21 10:59:15 -0600 (Sat, 21 Jan 2012) $
11 *
12 */
13/*
14 ******************************************************************************
15 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080016 * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
17 * All rights reserved.
zbao7d94cf92012-07-02 14:19:14 +080018 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080019 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions are met:
21 * * Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * * Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
27 * its contributors may be used to endorse or promote products derived
28 * from this software without specific prior written permission.
zbao7d94cf92012-07-02 14:19:14 +080029 *
Siyuan Wang641f00c2013-06-08 11:50:55 +080030 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
34 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
37 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
39 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
zbao7d94cf92012-07-02 14:19:14 +080040 ******************************************************************************
41 */
42
43/*----------------------------------------------------------------------------------------
44 * M O D U L E S U S E D
45 *----------------------------------------------------------------------------------------
46 */
47#include "AGESA.h"
48#include "amdlib.h"
49#include "cpuRegisters.h"
50#include "cpuF15TnPowerMgmt.h"
51#include "Table.h"
52#include "Filecode.h"
53CODE_GROUP (G3_DXE)
54RDATA_GROUP (G3_DXE)
55
56#define FILECODE PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE
57
58
59/*----------------------------------------------------------------------------------------
60 * D E F I N I T I O N S A N D M A C R O S
61 *----------------------------------------------------------------------------------------
62 */
63
64/*----------------------------------------------------------------------------------------
65 * T Y P E D E F S A N D S T R U C T U R E S
66 *----------------------------------------------------------------------------------------
67 */
68
69/*----------------------------------------------------------------------------------------
70 * P R O T O T Y P E S O F L O C A L F U N C T I O N S
71 *----------------------------------------------------------------------------------------
72 */
73
74VOID
75STATIC
76SetEnCstateBoostBlockCC6Exit (
77 IN UINT32 Data,
78 IN AMD_CONFIG_PARAMS *StdHeader
79 );
80
81VOID
82STATIC
83Erratum687Workaround (
84 IN UINT32 Data,
85 IN AMD_CONFIG_PARAMS *StdHeader
86 );
87
Rudolf Marekc805e622014-07-07 22:16:36 +020088VOID
89STATIC
90Erratum712Workaround (
91 IN UINT32 Data,
92 IN AMD_CONFIG_PARAMS *StdHeader
93 );
94
zbao7d94cf92012-07-02 14:19:14 +080095/*----------------------------------------------------------------------------------------
96 * E X P O R T E D F U N C T I O N S
97 *----------------------------------------------------------------------------------------
98 */
99
100// P C I T a b l e s
101// ----------------------
102
103STATIC CONST TABLE_ENTRY_FIELDS ROMDATA F15TnPciRegisters[] =
104{
105// F0x68 - Link Transaction Control
106// bits[22:21] DsNpReqLmt = 01b
107// bit [19] ApicExtSpur = 1
108// bit [18] ApicExtId = 1
109// bit [17] ApicExtBrdCst = 1
110// bit [15] LimitCldtCfg = 1
111// bit [10] DisFillP = 0
112 {
113 PciRegister,
114 {
115 AMD_FAMILY_15_TN, // CpuFamily
116 AMD_F15_TN_ALL // CpuRevision
117 },
118 {AMD_PF_ALL}, // platformFeatures
119 {{
120 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x68), // Address
121 0x002E8000, // regData
122 0x006E8400, // regMask
123 }}
124 },
125// F0x6C - Link Initialization Control
126// bit[0] RouteTblDis = 0
127 {
128 PciRegister,
129 {
130 AMD_FAMILY_15_TN, // CpuFamily
131 AMD_F15_TN_ALL // CpuRevision
132 },
133 {AMD_PF_ALL}, // platformFeatures
134 {{
135 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address
136 0x00000000, // regData
137 0x00000001, // regMask
138 }}
139 },
140// F0x84 - Link Control
141// bit [12] IsocEn = 1
142 {
143 PciRegister,
144 {
145 AMD_FAMILY_15_TN, // CpuFamily
146 AMD_F15_TN_ALL // CpuRevision
147 },
148 {AMD_PF_ALL}, // platformFeatures
149 {{
150 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x84), // Address
151 0x00001000, // regData
152 0x00001000, // regMask
153 }}
154 },
155// F0x90 - Upstream Base Channel Buffer Count
156// bits[27:25] FreeData = 0
157// bits[24:20] FreeCmd = 0
158// bits[19:18] RspData = 1
159// bits[17:16] NpReqData = 1
160// bits[15:12] ProbeCmd = 0
161// bits[11:8] RspCmd = 2
162// bits[7:5] PReq = 5
163// bits[4:0] NpReqCmd = 8
164 {
165 PciRegister,
166 {
167 AMD_FAMILY_15_TN, // CpuFamily
168 AMD_F15_TN_ALL // CpuRevision
169 },
170 {AMD_PF_ALL}, // platformFeatures
171 {{
172 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90), // Address
173 0x000502A8, // regData
174 0x0FFFFFFF, // regMask
175 }}
176 },
177// F0x94 - Link Isochronous Channel Buffer Count
178// bits[28:27] IsocRspData = 0
179// bits[26:25] IsocNpReqData = 1
180// bits[24:22] IsocRspCmd = 0
181// bits[21:19] IsocpReq = 0
182// bits[18:16] IsocNpReqCmd = 1
183// bits[15:8] SecBusNum = 0 (F1XE0 [BaseBusNum])
184 {
185 PciRegister,
186 {
187 AMD_FAMILY_15_TN, // CpuFamily
188 AMD_F15_TN_ALL // CpuRevision
189 },
190 {AMD_PF_ALL}, // platformFeatures
191 {{
192 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x94), // Address
193 0x02010000, // regData
194 0x1FFFFF00, // regMask
195 }}
196 },
197// F1xE0 - Configuration Map
198// bits[31:24] BusNumLimit = F8
199// bits[23:16] BaseBusNum = 0
200// bit [1] WE = 1
201// bit [0] RE = 1
202 {
203 PciRegister,
204 {
205 AMD_FAMILY_15_TN, // CpuFamily
206 AMD_F15_TN_ALL // CpuRevision
207 },
208 {AMD_PF_ALL}, // platformFeatures
209 {{
210 MAKE_SBDFO (0, 0, 24, FUNC_1, 0xE0),// Address
211 0xF8000003, // regData
212 0xFFFF0003, // regMask
213 }}
214 },
215// F3x44 - MCA NB Configuration
216//
217// bit[30] SyncFloodOnDramAdrParErr = 1
218// bit[27] NbMcaToMstCpuEn = 1
219// bit[21] SyncFloodOnAnyUcErr = 1
220// bit[20] SyncFloodOnWDT = 1
221
222 {
223 PciRegister,
224 {
225 AMD_FAMILY_15_TN, // CpuFamily
226 AMD_F15_TN_ALL // CpuRevision
227 },
228 {AMD_PF_ALL}, // platformFeatures
229 {{
230 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x44), // Address
231 0x48300000, // regData
232 0x48300000, // regMask
233 }}
234 },
235// F3x70 - SRI_to_XBAR Command Buffer Count
236// bits[30:28] IsocRspCBC = 1
237// bits[26:24] IsocPreqCBC = 0
238// bits[22:20] IsocReqCBC = 1
239// bits[18:16] UpRspCBC = 7
240// bits[14:12] DnPreqCBC = 1
241// bits[10:8] UpPreqCBC = 1
242// bits[7:6] DnRspCBC = 1
243// bits[5:4] DnReqCBC = 1
244// bits[2:0] UpReqCBC = 7
245 {
246 PciRegister,
247 {
248 AMD_FAMILY_15_TN, // CpuFamily
249 AMD_F15_TN_ALL // CpuRevision
250 },
251 {AMD_PF_ALL}, // platformFeatures
252 {{
253 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x70), // Address
254 0x10171157, // regData
255 0x777777F7, // regMask
256 }}
257 },
258// F3x74 - XBAR_to_SRI Command Buffer Count
259// bits[31:28] DRReqCBC = 0
260// bits[26:24] IsocPreqCBC = 1
261// bits[23:20] IsocReqCBC = 1
262// bits[19:16] ProbeCBC = 8
263// bits[14:12] DnPreqCBC = 0
264// bits[10:8] UpPreqCBC = 1
265// bits[6:4] DnReqCBC = 0
266// bits[2:0] UpReqCBC = 1
267 {
268 PciRegister,
269 {
270 AMD_FAMILY_15_TN, // CpuFamily
271 AMD_F15_TN_ALL // CpuRevision
272 },
273 {AMD_PF_ALL}, // platformFeatures
274 {{
275 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x74), // Address
276 0x01180101, // regData
277 0xF7FF7777, // regMask
278 }}
279 },
280// F3x7C - Free List Buffer Count
281// bits[26:23] ExtSrqFreeList = 8
282// bits[22:20] Sri2XbarFreeRspDBC = 0
283// bits[19:16] Sri2XbarFreeXreqDBC = 5
284// bits[15:12] Sri2XbarFreeRspCBC = 0
285// bits[11:8] Sri2XbarFreeXreqCBC = 0xE
286// bits[4:0] Xbar2SriFreeListCBC = 18h
287 {
288 PciRegister,
289 {
290 AMD_FAMILY_15_TN, // CpuFamily
291 AMD_F15_TN_ALL // CpuRevision
292 },
293 {AMD_PF_ALL}, // platformFeatures
294 {{
295 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x7C), // Address
296 0x04050E18, // regData
297 0x07FFFF1F, // regMask
298 }}
299 },
300// F3x84 - ACPI Power State Control High
301// ACPI State S3
302// bit[1] NbLowPwrEnSmafAct4 = 1
303// bit[7:5] ClkDivisorSmafAct4 = 7
304 {
305 PciRegister,
306 {
307 AMD_FAMILY_15_TN, // CpuFamily
308 AMD_F15_TN_ALL // CpuRevision
309 },
310 {AMD_PF_ALL}, // platformFeatures
311 {{
312 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x84), // Address
313 0x000000E2, // regData
314 0x000000E2, // regMask
315 }}
316 },
317// F3xA0 - Power Control Miscellaneous
318// bit[14] Svi2HighFreqSel = 1, if PERFORMANCE_VRM_HIGH_SPEED_ENABLE == TRUE
319 {
320 ProfileFixup,
321 {
322 AMD_FAMILY_15_TN, // CpuFamily
323 AMD_F15_TN_ALL // CpuRevision
324 },
325 {AMD_PF_ALL}, // platformFeatures
326 {{
327 PERFORMANCE_VRM_HIGH_SPEED_ENABLE, // PerformanceFeatures
328 MAKE_SBDFO (0, 0, 24, FUNC_3, 0xA0), // Address
329 0x00004000, // regData
330 0x00004000, // regMask
331 }}
332 },
333// F3xD4 - Clock Power Timing Control 0
334// bit [31] NbClkDivApplyAll = 1
335// bits[30:28] NbClkDiv = 4
336// bits[27:24] PowerStepUp = 8
337// bits[23:20] PowerStepDown = 8
338// bit [14] CacheFlushImmOnAllHalt = 0
339// bit [12] ClkRampHystCtl = 0
340// bits[11:8] ClkRampHystSel = 0xF
341 {
342 PciRegister,
343 {
344 AMD_FAMILY_15_TN, // CpuFamily
345 AMD_F15_TN_ALL // CpuRevision
346 },
347 {AMD_PF_ALL}, // platformFeatures
348 {{
349 MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD4), // Address
350 0xC8800F00, // regData
351 0xFFF05F00, // regMask
352 }}
353 },
354// F3xD8 - Clock Power Timing Control 1
355// bits[6:4] VSRampSlamTime = 100b
356 {
357 PciRegister,
358 {
359 AMD_FAMILY_15_TN, // CpuFamily
360 AMD_F15_TN_ALL // CpuRevision
361 },
362 {AMD_PF_ALL}, // platformFeatures
363 {{
364 MAKE_SBDFO (0, 0, 24, FUNC_3, 0xD8), // Address
365 0x00000040, // regData
366 0x00000070, // regMask
367 }}
368 },
369// F3xDC - Clock Power Timing Control 2
370// bits[14:12] NbsynPtrAdj = 5
371 {
372 PciRegister,
373 {
374 (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
375 AMD_F15_TN_ALL // CpuRevision
376 },
377 {AMD_PF_ALL}, // platformFeatures
378 {{
379 MAKE_SBDFO (0, 0, 24, FUNC_3, 0xDC), // Address
380 0x00005000, // regData
381 0x00007000, // regMask
382 }}
383 },
384// F3x140 - SRI_to_XCS Token Count
385// bits[23:20] FreeTok = 0xA
386// bits[17:16] IsocRspTok = 1
387// bits[15:14] IsocPreqTok = 0
388// bits[13:12] IsocReqTok = 1
389// bits[11:10] DnRspTok = 1
390// bits[9:8] UpRspTok = 1
391// bits[7:6] DnPreqTok = 1
392// bits[5:4] UpPreqTok = 1
393// bits[3:2] DnReqTok = 1
394// bits[1:0] UpReqTok = 1
395 {
396 PciRegister,
397 {
398 AMD_FAMILY_15_TN, // CpuFamily
399 AMD_F15_TN_ALL // CpuRevision
400 },
401 {AMD_PF_ALL}, // platform Features
402 {{
403 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x140), // Address
404 0x00A11555, // regData
405 0x00F3FFFF, // regMask
406 }}
407 },
408// F3x144 - MCT_to_XCS Token Count
409// bits[7:4] ProbeTok = 7
410// bits[3:0] RspTok = 7
411 {
412 PciRegister,
413 {
414 AMD_FAMILY_15_TN, // CpuFamily
415 AMD_F15_TN_ALL // CpuRevision
416 },
417 {AMD_PF_ALL}, // platform Features
418 {{
419 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x144), // Address
420 0x00000077, // regData
421 0x000000FF, // regMask
422 }}
423 },
424// F3x148 - Link_to_XCS Token Count
425// bits[31:30] FreeTok[3:2] = FreeTok[1:0] = 0
426// bit [28] IsocRspTok1 = 0
427// bit [26] IsocPreqTok1 = 0
428// bit [24] IsocReqTok1 = 0
429// bits[23:22] ProbeTok1 = 0
430// bits[21:20] RspTok1 = 0
431// bits[19:18] PReqTok1 = 0
432// bits[17:16] ReqTok1 = 0
433// bits[15:14] FreeTok[1:0] = 0
434// bits[13:12] IsocRspTok0 = 0
435// bits[11:10] IsocPreqTok0 = 1
436// bits[9:8] IsocReqTok0 = 1
437// bits[7:6] ProbeTok0 = 0
438// bits[5:4] RspTok0 = 2
439// bits[3:2] PReqTok0 = 2
440// bits[1:0] ReqTok0 = 2
441 {
442 PciRegister,
443 {
444 AMD_FAMILY_15_TN, // CpuFamily
445 AMD_F15_TN_ALL // CpuRevision
446 },
447 {AMD_PF_ALL}, // platform Features
448 {{
449 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x148), // Address
450 0x0000052A, // regData
451 0xD5FFFFFF // regMask
452 }}
453 },
454// F3x17C - Extended Freelist Buffer Count
455// bits[3:0] SPQPrbFreeCBC = 4
456 {
457 PciRegister,
458 {
459 AMD_FAMILY_15_TN, // CpuFamily
460 AMD_F15_TN_ALL // CpuRevision
461 },
462 {AMD_PF_ALL}, // platform Features
463 {{
464 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x17C), // Address
465 0x00000004, // regData
466 0x0000000F // regMask
467 }}
468 },
469// F3x180 - NB Extended Configuration
470// bit[24] McaLogErrAddrWdtErr = 1
471// bit[22] SyncFloodOnTblWalkErr = 1
472// bit[21] SyncFloodOnCpuLeakErr = 1
473// bit[20] SyncFloodOnL3LeakErr = 1
474// bit[9] SyncFloodOnUCNbAry = 1
475// bit[8] SyncFloodOnHtProt = 1
476// bit[7] SyncFloodOnTgtAbortErr = 1
477// bit[6] SyncFloodOnDatErr = 1
478// bit[5] DisPciCfgCpuMstAbortRsp = 1
479 {
480 PciRegister,
481 {
482 AMD_FAMILY_15_TN, // CpuFamily
483 AMD_F15_TN_ALL // CpuRevision
484 },
485 {AMD_PF_ALL}, // platformFeatures
486 {{
487 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x180), // Address
488 0x017003E0, // regData
489 0x017003E0, // regMask
490 }}
491 },
492// F3x1A0 - Core to NB Buffer Count
493// bit[17:16] CpuToNbFreeBufCnt = 3
494 {
495 PciRegister,
496 {
497 AMD_FAMILY_15_TN, // CpuFamily
498 AMD_F15_TN_ALL // CpuRevision
499 },
500 {AMD_PF_ALL}, // platformFeatures
501 {{
502 MAKE_SBDFO (0, 0, 24, FUNC_3, 0x1A0), // Address
503 0x00030000, // regData
504 0x00030000, // regMask
505 }}
506 },
507// F4x110 - Sample and Residency Timer
508// bits[11:0] CSampleTimer = 2
509 {
510 PciRegister,
511 {
512 AMD_FAMILY_15_TN, // CpuFamily
513 AMD_F15_TN_ALL // CpuRevision
514 },
515 {AMD_PF_ALL}, // platformFeatures
516 {{
517 MAKE_SBDFO (0, 0, 24, FUNC_4, 0x110), // Address
518 0x00000002, // regData
519 0x00000FFF, // regMask
520 }}
521 },
522// F4x124 - C-state Interrupt Control
523// bits[26:23] IntMonPC6Limit = 0
524// bit [22] IntMonPC6En = 1
525 {
526 PciRegister,
527 {
528 AMD_FAMILY_15_TN, // CpuFamily
529 AMD_F15_TN_ALL // CpuRevision
530 },
531 {AMD_PF_ALL}, // platformFeatures
532 {{
533 MAKE_SBDFO (0, 0, 24, FUNC_4, 0x124), // Address
534 0x00400000, // regData
535 0x07C00000, // regMask
536 }}
537 },
538// F4x16C - Erratum #667
539// bit [1] = 1
540// bit [4] = 1
541 {
542 PciRegister,
543 {
544 AMD_FAMILY_15_TN, // CpuFamily
545 AMD_F15_TN_ALL // CpuRevision
546 },
547 {AMD_PF_ALL}, // platformFeatures
548 {{
549 MAKE_SBDFO (0, 0, 24, FUNC_4, 0x16C), // Address
550 0x00000012, // regData
551 0x00000012, // regMask
552 }}
553 },
554// F5xAC - Erratum #667
555// bit [3] = 1
556 {
557 PciRegister,
558 {
559 AMD_FAMILY_15_TN, // CpuFamily
560 AMD_F15_TN_ALL // CpuRevision
561 },
562 {AMD_PF_ALL}, // platformFeatures
563 {{
564 MAKE_SBDFO (0, 0, 24, FUNC_5, 0xAC), // Address
565 0x00000008, // regData
566 0x00000008, // regMask
567 }}
568 },
569// F5x88 - Northbridge Configuration 4
570// bit[24] DisHbNpReqBusLock = 1
571// bit[2] IntStpClkHaltExitEn = 1
572 {
573 PciRegister,
574 {
575 AMD_FAMILY_15_TN, // CpuFamily
576 AMD_F15_TN_ALL // CpuRevision
577 },
578 {AMD_PF_ALL}, // platformFeatures
579 {{
580 MAKE_SBDFO (0, 0, 24, FUNC_5, 0x88), // Address
581 0x01000004, // regData
582 0x01000004, // regMask
583 }}
584 },
585// F5xE0 - Processor TDP Running Average
586// bits[3:0] RunAvgRange = 0x2
587 {
588 PciRegister,
589 {
590 AMD_FAMILY_15_TN, // CpuFamily
591 AMD_F15_TN_ALL // CpuRevision
592 },
593 {AMD_PF_ALL}, // platformFeatures
594 {{
595 MAKE_SBDFO (0, 0, 24, FUNC_5, 0xE0), // Address
596 0x00000002, // regData
597 0x0000000F, // regMask
598 }}
599 },
600// F5x128 - Clock Power/Timing Control 3
601// bits[13:12] PwrGateTmr = 1
602// bits[11:10] PllVddOutUpTime = 3
603// bit [9] FastSlamTimeDown = 1
604 {
605 PciRegister,
606 {
607 AMD_FAMILY_15_TN, // CpuFamily
608 AMD_F15_TN_ALL // CpuRevision
609 },
610 {AMD_PF_ALL}, // platformFeatures
611 {{
612 MAKE_SBDFO (0, 0, 24, FUNC_5, 0x128), // Address
613 0x00001E00, // regData
614 0x00003E00, // regMask
615 }}
616 },
617// F5x12C - Clock Power/Timing Control 4
618// bit [5] CorePsi1En = 1
619 {
620 PciRegister,
621 {
622 AMD_FAMILY_15_TN, // CpuFamily
623 AMD_F15_TN_ALL // CpuRevision
624 },
625 {AMD_PF_ALL}, // platformFeatures
626 {{
627 MAKE_SBDFO (0, 0, 24, FUNC_5, 0x12C), // Address
628 0x00000020, // regData
629 0x00000020, // regMask
630 }}
631 },
632// F5x178 - Northbridge Fusion Configuration
633// bit [18] CstateFusionHsDis = 1
634// bit [17] Dis2ndGnbAllowPsWait = 1
635// bit [11] AllowSelfRefrS3Dis = 1
636// bit [10] InbWakeS3Dis = 1
637// bit [2] CstateFusionDis = 1
638 {
639 PciRegister,
640 {
641 AMD_FAMILY_15_TN, // CpuFamily
642 AMD_F15_TN_ALL // CpuRevision
643 },
644 {AMD_PF_ALL}, // platformFeatures
645 {{
646 MAKE_SBDFO (0, 0, 24, FUNC_5, 0x178), // Address
647 0x00060C04, // regData
648 0x00060C04, // regMask
649 }}
650 },
651// F0x90 - Upstream Base Channel Buffer Count
652// bit [31] LockBc = 1
653//
654// NOTE: The entry is intended to be programmed after other bits of D18F0x[90, 94] is programmed and before D18F0x6C[30] is programmed.
655 {
656 PciRegister,
657 {
658 AMD_FAMILY_15_TN, // CpuFamily
659 AMD_F15_TN_ALL // CpuRevision
660 },
661 {AMD_PF_ALL}, // platformFeatures
662 {{
663 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x90), // Address
664 0x80000000, // regData
665 0x80000000, // regMask
666 }}
667 },
668// F0x6C - Link Initialization Control
669// bit [30] RlsLnkFullTokCntImm = 1
670// bit [28] RlsIntFullTokCntImm = 1
671//
672// NOTE: The entry is intended to be after D18F0x[90, 94] and D18F0x[70, 74, 78, 7C, 140, 144, 148, 17C, 1A0] are programmed.
673 {
674 PciRegister,
675 {
676 AMD_FAMILY_15_TN, // CpuFamily
677 AMD_F15_TN_ALL // CpuRevision
678 },
679 {AMD_PF_ALL}, // platformFeatures
680 {{
681 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address
682 0x50000000, // regData
683 0x50000000, // regMask
684 }}
685 },
686// F0x6C - Link Initialization Control
687// bit [27] ApplyIsocModeEnNow = 1
688//
689// NOTE: The entry is intended to be after D18F0x6C[30, 28] are programmed.
690 {
691 PciRegister,
692 {
693 AMD_FAMILY_15_TN, // CpuFamily
694 AMD_F15_TN_ALL // CpuRevision
695 },
696 {AMD_PF_ALL}, // platformFeatures
697 {{
698 MAKE_SBDFO (0, 0, 24, FUNC_0, 0x6C), // Address
699 0x08000000, // regData
700 0x08000000, // regMask
701 }}
702 },
703};
704
705
706// PCI with Special Programming Requirements Table
707
708STATIC CONST FAM_SPECIFIC_WORKAROUND_TYPE_ENTRY_INITIALIZER ROMDATA F15TnPciWorkarounds[] =
709{
710// D18F5x88
711 {
712 FamSpecificWorkaround,
713 {
714 (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
715 AMD_F15_TN_GT_A0 // CpuRevision
716 },
717 {AMD_PF_ALL}, // platformFeatures
718 {{
719 SetEnCstateBoostBlockCC6Exit, // function call
720 0x00000000, // data
721 }}
722 },
723// D18F5x88 and D18F2x408
724 {
725 FamSpecificWorkaround,
726 {
727 (AMD_FAMILY_15_OR | AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
728 AMD_F15_TN_ALL // CpuRevision
729 },
730 {AMD_PF_ALL}, // platformFeatures
731 {{
732 Erratum687Workaround, // function call
733 0x00000000, // data
734 }}
735 },
Rudolf Marekc805e622014-07-07 22:16:36 +0200736 {
737 FamSpecificWorkaround,
738 {
739 (AMD_FAMILY_15_TN | 0x0000000000000800ull) , // CpuFamily
740 AMD_F15_TN_ALL // CpuRevision
741 },
742 {AMD_PF_ALL}, // platformFeatures
743 {{
744 Erratum712Workaround, // function call
745 0x00000000, // data
746 }}
747 },
zbao7d94cf92012-07-02 14:19:14 +0800748};
749
750
751CONST REGISTER_TABLE ROMDATA F15TnPciRegisterTable = {
752 PrimaryCores,
753 (sizeof (F15TnPciRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
754 F15TnPciRegisters,
755};
756
757
758CONST REGISTER_TABLE ROMDATA F15TnPciWorkaroundTable = {
759 PrimaryCores,
760 (sizeof (F15TnPciWorkarounds) / sizeof (TABLE_ENTRY_FIELDS)),
761 (TABLE_ENTRY_FIELDS *) F15TnPciWorkarounds,
762};
763
764
765/*---------------------------------------------------------------------------------------*/
766/**
767 * Workaround for Non-A0 TN processors.
768 *
769 * AGESA should program F5x88[18] with the fused value from F3x1FC[20] for non-RevA0 parts.
770 *
771 * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
772 * @param[in] StdHeader Config handle for library and services.
773 *
774 */
775VOID
776STATIC
777SetEnCstateBoostBlockCC6Exit (
778 IN UINT32 Data,
779 IN AMD_CONFIG_PARAMS *StdHeader
780 )
781{
782 PCI_ADDR PciAddress;
783 PRODUCT_INFO_REGISTER ProductInfo;
784 NB_CFG_4_REGISTER NbCfg4;
785
786 PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
787 LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
788
789 PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
790 LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
791
792 NbCfg4.EnCstateBoostBlockCC6Exit = ProductInfo.EnCstateBoostBlockCC6Exit;
793 LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
794}
795
796/*---------------------------------------------------------------------------------------*/
797/**
798 * Workaround for Erratum #687 for TN processors.
799 *
800 * AGESA should program F5x88[14] with the fused value from F3x1FC[29] and
801 * program F2x408[CpuElevPrioDis] with inversed fuse value from F3x1FC[29] for all TN parts.
802 *
803 * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
804 * @param[in] StdHeader Config handle for library and services.
805 *
806 */
807VOID
808STATIC
809Erratum687Workaround (
810 IN UINT32 Data,
811 IN AMD_CONFIG_PARAMS *StdHeader
812 )
813{
814 PCI_ADDR PciAddress;
815 PRODUCT_INFO_REGISTER ProductInfo;
816 NB_CFG_4_REGISTER NbCfg4;
817 GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2;
818 UINT32 DctSelCnt;
819 DCT_CFG_SEL_REGISTER DctCfgSel;
820
821 PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
822 LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&ProductInfo, StdHeader);
823
824 PciAddress.AddressValue = NB_CFG_REG4_PCI_ADDR;
825 LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
826 NbCfg4.Bit14 = ProductInfo.EnDcqChgPriToHigh;
827 LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&NbCfg4, StdHeader);
828
829 for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) {
830 PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR;
831 LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
832 GmcToDctCtrl2.CpuElevPrioDis = ~ProductInfo.EnDcqChgPriToHigh;
833 LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
834
835 PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR;
836 LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
837 DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel;
838 LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
839 }
840}
Rudolf Marekc805e622014-07-07 22:16:36 +0200841/*---------------------------------------------------------------------------------------*/
842/**
843 * Workaround for Erratum #712 for TN processors.
844 *
845 * AGESA should program D18F2x408_dct[1:0] bit 31 = 1b for all TN parts.
846 *
847 * @param[in] Data The table data value, for example to indicate which CPU and Platform types matched.
848 * @param[in] StdHeader Config handle for library and services.
849 *
850 */
851VOID
852STATIC
853Erratum712Workaround (
854 IN UINT32 Data,
855 IN AMD_CONFIG_PARAMS *StdHeader
856 )
857{
858 PCI_ADDR PciAddress;
859 GMC_TO_DCT_CTL_2_REGISTER GmcToDctCtrl2;
860 UINT32 DctSelCnt;
861 DCT_CFG_SEL_REGISTER DctCfgSel;
zbao7d94cf92012-07-02 14:19:14 +0800862
Rudolf Marekc805e622014-07-07 22:16:36 +0200863 for (DctSelCnt = 0; DctSelCnt <= 1; DctSelCnt++) {
864 PciAddress.AddressValue = GMC_TO_DCT_CTL_2_PCI_ADDR;
865 LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
866 GmcToDctCtrl2.DisHalfNclkPwrGate |= 1;
867 LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&GmcToDctCtrl2, StdHeader);
868
869 PciAddress.AddressValue = DCT_CFG_SEL_REG_PCI_ADDR;
870 LibAmdPciRead (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
871 DctCfgSel.DctCfgSel = ~DctCfgSel.DctCfgSel;
872 LibAmdPciWrite (AccessWidth32, PciAddress, (VOID *)&DctCfgSel, StdHeader);
873 }
874}