Anton Kochkov | 54c07a6 | 2012-07-04 07:35:45 +0400 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of msrtool. |
| 3 | * |
| 4 | * Copyright (C) 2012 Anton Kochkov <anton.kochkov@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Anton Kochkov | 54c07a6 | 2012-07-04 07:35:45 +0400 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include "msrtool.h" |
| 21 | |
Anton Kochkov | 59b36f1 | 2012-07-21 07:29:48 +0400 | [diff] [blame] | 22 | int intel_nehalem_probe(const struct targetdef *target, const struct cpuid_t *id) { |
Anton Kochkov | 54c07a6 | 2012-07-04 07:35:45 +0400 | [diff] [blame] | 23 | return ((0x6 == id->family) && ( |
| 24 | (0x1a == id->model) || |
| 25 | (0x1e == id->model) || |
| 26 | (0x1f == id->model) || |
| 27 | (0x2e == id->model) |
| 28 | )); |
| 29 | } |
| 30 | |
| 31 | const struct msrdef intel_nehalem_msrs[] = { |
| 32 | {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", |
| 33 | "Model Specific Platform ID", { |
| 34 | { 63, 11, RESERVED }, |
| 35 | { 52, 3, RESERVED }, |
| 36 | { 49, 37, RESERVED }, |
| 37 | { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio", |
| 38 | PRESENT_DEC, { |
| 39 | { BITVAL_EOT } |
| 40 | }}, |
| 41 | { 7, 8, RESERVED }, |
| 42 | { BITS_EOT } |
| 43 | }}, |
| 44 | /* FIXME: This MSR not documented for Nehalem */ |
| 45 | {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { |
| 46 | /* This field indicates the intended scaleable bus clock speed */ |
| 47 | { BITS_EOT } |
| 48 | }}, |
| 49 | {0xce, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PLATFORM_INFO", "", { |
| 50 | { 63, 16, RESERVED }, |
| 51 | { 47, 8, "Maximum Efficiency Ratio", "R/O", PRESENT_DEC, { |
| 52 | { BITVAL_EOT } |
| 53 | }}, |
| 54 | { 39, 10, RESERVED }, |
| 55 | { 29, 1, "Programmable TDC-TDP Limit for Turbo Mode", "R/O", PRESENT_DEC, { |
| 56 | { MSR1(0), "TDC and TDP Limits for Turbo Mode are not programmable" }, |
| 57 | { MSR1(1), "TDC and TDP Limits for Turbo Mode are programmable" }, |
| 58 | { BITVAL_EOT } |
| 59 | }}, |
| 60 | { 28, 1, "Programmable Ratio Limit for Turbo Mode", "R/O", PRESENT_DEC, { |
| 61 | { MSR1(0), "Programmable Ratio Limit for Turbo Mode is disabled" }, |
| 62 | { MSR1(1), "Programmable Ratio Limit for Turbo Mode is enabled" }, |
| 63 | { BITVAL_EOT } |
| 64 | }}, |
| 65 | { 27, 12, RESERVED }, |
| 66 | { 15, 8, "Maximum Non-Turbo Ratio", "R/O", PRESENT_DEC, { |
| 67 | /* The is ratio of the frequency that invariant TSC runs at. The invariant |
| 68 | * TSC requency can be computed by multipying this ratio by 133.33 Mhz |
| 69 | */ |
| 70 | { BITVAL_EOT } |
| 71 | }}, |
| 72 | { 7, 8, RESERVED }, |
| 73 | { BITS_EOT } |
| 74 | }}, |
| 75 | {0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { |
| 76 | { BITS_EOT } |
| 77 | }}, |
| 78 | /* FIXME: There is already two 0x1ad MSRs for Nehalem in the |
| 79 | * Intel 64 and IA-32 Architectures Software Developer's Manual |
| 80 | * Volume 3C 34-91. But from decimal value of this register, |
| 81 | * we can conclude, that it was just typo, and this register |
| 82 | * have address 0x1ac. |
| 83 | */ |
| 84 | {0x1ac, MSRTYPE_RDWR, MSR2(0,0), "MSR_TURBO_POWER_CURRENT_LIMIT", "", { |
| 85 | { 63, 32, RESERVED }, |
| 86 | { 31, 1, "TDC Limit Override Enable", "R/W", PRESENT_BIN, { |
| 87 | { MSR1(0), "TDC Limit Override is not active" }, |
| 88 | { MSR1(1), "TDC Limit Override is active" }, |
| 89 | { BITVAL_EOT } |
| 90 | }}, |
| 91 | { 30, 15, "TDC Limit", "R/W", PRESENT_HEX, { |
| 92 | /* TDC Limit in 1/8 Amp granularity */ |
| 93 | { BITVAL_EOT } |
| 94 | }}, |
| 95 | { 15, 1, "TDP Limit Override Enable", "R/W", PRESENT_BIN, { |
| 96 | { MSR1(0), "TDP Limit Override is not active" }, |
| 97 | { MSR1(1), "TDP Limit Override is active" }, |
| 98 | { BITVAL_EOT } |
| 99 | }}, |
| 100 | { 14, 15, "TDP Limit", "R/W", PRESENT_HEX, { |
| 101 | /* TDP Limit in 1/8 Watt granularity */ |
| 102 | { BITVAL_EOT } |
| 103 | }}, |
| 104 | { BITS_EOT } |
| 105 | }}, |
| 106 | {0x1ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_TURBO_RATIO_LIMIT", |
| 107 | "Maximum Ratio Limit of Turbo Mode", { |
| 108 | // "RO" if MSR_PLATFORM_INFO.[28] = 0 |
| 109 | // "RW" if MSR_PLATFORM_INFO.[23] = 1 |
| 110 | { 63, 32, RESERVED }, |
| 111 | { 31, 8, "Maximum Ratio Limit for 4C", "R/O", PRESENT_HEX, { |
| 112 | // Maximum Turbo Ratio Limit of 4 core active |
| 113 | { BITVAL_EOT } |
| 114 | }}, |
| 115 | { 23, 8, "Maximum Ratio Limit for 3C", "R/O", PRESENT_HEX, { |
| 116 | // Maximum Turbo Ratio Limit of 3 core active |
| 117 | { BITVAL_EOT } |
| 118 | }}, |
| 119 | { 15, 8, "Maximum Ratio Limit for 2C", "R/O", PRESENT_HEX, { |
| 120 | // Maximum Turbo Ratio Limit of 2 core active |
| 121 | { BITVAL_EOT } |
| 122 | }}, |
| 123 | { 7, 8, "Maximum Ratio Limit for 1C", "R/O", PRESENT_HEX, { |
| 124 | // Maximum Turbo Ratio Limit of 1 core active |
| 125 | { BITVAL_EOT } |
| 126 | }}, |
| 127 | { BITS_EOT } |
| 128 | }}, |
| 129 | {0x280, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL2", "", { |
| 130 | { 63, 33, RESERVED }, |
| 131 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 132 | { BITVAL_EOT } |
| 133 | }}, |
| 134 | { 29, 15, RESERVED }, |
| 135 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 136 | { BITVAL_EOT } |
| 137 | }}, |
| 138 | { BITS_EOT } |
| 139 | }}, |
| 140 | {0x281, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL2", "", { |
| 141 | { 63, 33, RESERVED }, |
| 142 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 143 | { BITVAL_EOT } |
| 144 | }}, |
| 145 | { 29, 15, RESERVED }, |
| 146 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 147 | { BITVAL_EOT } |
| 148 | }}, |
| 149 | { BITS_EOT } |
| 150 | }}, |
| 151 | {0x286, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL2", "", { |
| 152 | { 63, 33, RESERVED }, |
| 153 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 154 | { BITVAL_EOT } |
| 155 | }}, |
| 156 | { 29, 15, RESERVED }, |
| 157 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 158 | { BITVAL_EOT } |
| 159 | }}, |
| 160 | { BITS_EOT } |
| 161 | }}, |
| 162 | {0x287, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_CTL2", "", { |
| 163 | { 63, 33, RESERVED }, |
| 164 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 165 | { BITVAL_EOT } |
| 166 | }}, |
| 167 | { 29, 15, RESERVED }, |
| 168 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 169 | { BITVAL_EOT } |
| 170 | }}, |
| 171 | { BITS_EOT } |
| 172 | }}, |
| 173 | {0x288, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_CTL2", "", { |
| 174 | { 63, 33, RESERVED }, |
| 175 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 176 | { BITVAL_EOT } |
| 177 | }}, |
| 178 | { 29, 15, RESERVED }, |
| 179 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 180 | { BITVAL_EOT } |
| 181 | }}, |
| 182 | { BITS_EOT } |
| 183 | }}, |
| 184 | {0x3f8, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C3_RESIDENCY", "", { |
| 185 | { 63, 64, "Package C3 Residency Counter", "R/O", PRESENT_DEC, { |
| 186 | /* Value since last reset that this package is in C3 states. |
| 187 | * Count at the same frequency as the TSC. |
| 188 | */ |
| 189 | { BITVAL_EOT } |
| 190 | }}, |
| 191 | { BITS_EOT } |
| 192 | }}, |
| 193 | {0x3f9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C6_RESIDENCY", "", { |
| 194 | { BITS_EOT } |
| 195 | }}, |
| 196 | {0x3fa, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C7_RESIDENCY", "", { |
| 197 | { BITS_EOT } |
| 198 | }}, |
| 199 | {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", { |
| 200 | { BITS_EOT } |
| 201 | }}, |
| 202 | {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", { |
| 203 | { BITS_EOT } |
| 204 | }}, |
| 205 | {0x41a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_ADDR", "", { |
| 206 | { BITS_EOT } |
| 207 | }}, |
| 208 | {0x41b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_MISC", "", { |
| 209 | { BITS_EOT } |
| 210 | }}, |
| 211 | {0x41c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_CTL", "", { |
| 212 | { BITS_EOT } |
| 213 | }}, |
| 214 | {0x41d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_STATUS", "", { |
| 215 | { BITS_EOT } |
| 216 | }}, |
| 217 | {0x41e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_ADDR", "", { |
| 218 | { BITS_EOT } |
| 219 | }}, |
| 220 | {0x41f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_MISC", "", { |
| 221 | { BITS_EOT } |
| 222 | }}, |
| 223 | {0x420, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_CTL", "", { |
| 224 | { BITS_EOT } |
| 225 | }}, |
| 226 | {0x421, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_STATUS", "", { |
| 227 | { BITS_EOT } |
| 228 | }}, |
| 229 | {0x422, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_ADDR", "", { |
| 230 | { BITS_EOT } |
| 231 | }}, |
| 232 | {0x423, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_MISC", "", { |
| 233 | { BITS_EOT } |
| 234 | }}, |
| 235 | |
| 236 | /* ========================================================================== |
| 237 | * Per core MSRs |
| 238 | * ========================================================================== |
| 239 | */ |
| 240 | |
| 241 | {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ |
| 242 | Machine-Check Exception Address", { |
| 243 | { BITS_EOT } |
| 244 | }}, |
| 245 | {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ |
| 246 | Machine-Check Exception Type", { |
| 247 | { BITS_EOT } |
| 248 | }}, |
| 249 | {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { |
| 250 | { BITS_EOT } |
| 251 | }}, |
| 252 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { |
| 253 | { BITS_EOT } |
| 254 | }}, |
| 255 | {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", { |
| 256 | /* In Intel's manual there is MAXPHYWID, |
| 257 | * which determine index of highest bit of |
| 258 | * APIC Base itself, so marking it as |
| 259 | * 'RESERVED'. |
| 260 | */ |
| 261 | { 63, 52, RESERVED }, |
| 262 | { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN, { |
| 263 | { BITVAL_EOT } |
| 264 | }}, |
| 265 | { 10, 1, "x2APIC mode", "R/W", PRESENT_BIN, { |
| 266 | { MSR1(0), "x2APIC mode is disabled" }, |
| 267 | { MSR1(1), "x2APIC mode is enabled" }, |
| 268 | { BITVAL_EOT } |
| 269 | }}, |
| 270 | { 9, 1, RESERVED }, |
| 271 | { 8, 1, "BSP Flag", "R/W", PRESENT_BIN, { |
| 272 | { BITVAL_EOT } |
| 273 | }}, |
| 274 | { 7, 8, RESERVED }, |
| 275 | { BITS_EOT } |
| 276 | }}, |
| 277 | {0x34, MSRTYPE_RDONLY, MSR2(0,0), "MSR_SMI_COUNT", "SMI Counter register", { |
| 278 | { 63, 32, RESERVED }, |
| 279 | { 31, 32, "SMI Count", "R/O", PRESENT_HEX, { |
| 280 | { BITVAL_EOT } |
| 281 | }}, |
| 282 | { BITS_EOT } |
| 283 | }}, |
| 284 | /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */ |
| 285 | {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", |
| 286 | "Control features in Intel 64Processor", { |
| 287 | { 63, 48, RESERVED }, |
| 288 | /* if CPUID.01H: ECX[6] = 1 */ |
| 289 | { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, { |
| 290 | { MSR1(0), "SENTER leaf functions are disabled" }, |
| 291 | { MSR1(1), "SENTER leaf functions are enabled" }, |
| 292 | { BITVAL_EOT } |
| 293 | }}, |
| 294 | /* if CPUID.01H: ECX[6] = 1 */ |
| 295 | { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, { |
| 296 | { BITVAL_EOT } |
| 297 | }}, |
| 298 | { 7, 5, RESERVED }, |
| 299 | /* if CPUID.01H: ECX[5 or 6] = 1 */ |
| 300 | { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, { |
| 301 | /* This bit enables VMX for system executive |
| 302 | * that do not require SMX. |
| 303 | */ |
| 304 | { MSR1(0), "VMX outside of SMX operation disabled" }, |
| 305 | { MSR1(1), "VMX outside of SMX operation enabled" }, |
| 306 | { BITVAL_EOT } |
| 307 | }}, |
| 308 | { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { |
| 309 | /* This bit enables a system executive to use |
| 310 | * VMX in conjuction with SMX to support Intel |
| 311 | * Trusted Execution Technology. |
| 312 | */ |
| 313 | { MSR1(0), "VMX inside of SMX operation disabled" }, |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 314 | { MSR1(1), "VMX inside of SMX operation enabled" }, |
Anton Kochkov | 54c07a6 | 2012-07-04 07:35:45 +0400 | [diff] [blame] | 315 | { BITVAL_EOT } |
| 316 | }}, |
| 317 | /* if CPUID.01H: ECX[5 or 6] = 1 */ |
| 318 | { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, { |
| 319 | /* Once the Lock bit is set, the contents |
| 320 | * of this register cannot be modified. |
| 321 | * Therefore the lock bit must be set after |
| 322 | * configuring support for Intel Virtualization |
| 323 | * Technology and prior transferring control |
| 324 | * to an Option ROM or bootloader. Hence, once |
| 325 | * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR |
| 326 | * contents are preserved across RESET when |
| 327 | * PWRGOOD it not deasserted. |
| 328 | */ |
| 329 | { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" }, |
| 330 | { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" }, |
| 331 | { BITVAL_EOT } |
| 332 | }}, |
| 333 | { BITS_EOT } |
| 334 | }}, |
| 335 | {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { |
| 336 | { BITS_EOT } |
| 337 | }}, |
| 338 | {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { |
| 339 | { BITS_EOT } |
| 340 | }}, |
| 341 | {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { |
| 342 | { BITS_EOT } |
| 343 | }}, |
| 344 | {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { |
| 345 | { BITS_EOT } |
| 346 | }}, |
| 347 | {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { |
| 348 | { BITS_EOT } |
| 349 | }}, |
| 350 | {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { |
| 351 | { BITS_EOT } |
| 352 | }}, |
| 353 | {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { |
| 354 | { BITS_EOT } |
| 355 | }}, |
| 356 | {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { |
| 357 | { BITS_EOT } |
| 358 | }}, |
| 359 | {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", |
| 360 | "BIOS Update Trigger Register (W)", { |
| 361 | { BITS_EOT } |
| 362 | }}, |
| 363 | {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", |
| 364 | "BIOS Update Signature ID (RO)", { |
| 365 | { BITS_EOT } |
| 366 | }}, |
| 367 | {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", { |
| 368 | { BITS_EOT } |
| 369 | }}, |
| 370 | {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", { |
| 371 | { BITS_EOT } |
| 372 | }}, |
| 373 | {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", |
| 374 | "Performance counter register", { |
| 375 | { BITS_EOT } |
| 376 | }}, |
| 377 | {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", |
| 378 | "Performance counter register", { |
| 379 | { BITS_EOT } |
| 380 | }}, |
| 381 | {0xc3, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC2", |
| 382 | "Performance counter register", { |
| 383 | { BITS_EOT } |
| 384 | }}, |
| 385 | {0xc4, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC3", |
| 386 | "Performance counter register", { |
| 387 | { BITS_EOT } |
| 388 | }}, |
| 389 | {0xe2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PKG_CST_CONFIG_CONTROL", |
| 390 | "C-State Configuration Control", { |
| 391 | { 63, 37, RESERVED }, |
| 392 | { 26, 1, "C1 state auto demotion", "R/W", PRESENT_DEC, { |
| 393 | { MSR1(0), "Demotion of C3/C6/C7 requests to C1 is disabled" }, |
| 394 | { MSR1(1), "Demotion of C3/C6/C7 requests to C1 is enabled" }, |
| 395 | { BITVAL_EOT } |
| 396 | }}, |
| 397 | { 25, 1, "C3 state auto demotion", "R/W", PRESENT_DEC, { |
| 398 | { MSR1(0), "Demotion of C6/C7 requests to C3 is disabled" }, |
| 399 | { MSR1(1), "Demotion of C6/C7 requests to C3 is enabled" }, |
| 400 | { BITVAL_EOT } |
| 401 | }}, |
| 402 | { 24, 1, "Interrupt filtering enabled/disabled", "R/W", PRESENT_DEC, { |
| 403 | { MSR1(0), "All CPU cores in deep C-State will wake for an \ |
| 404 | event message" }, |
| 405 | { MSR1(1), "CPU in deep C-State will wake only when the event \ |
| 406 | message is destined for that core" }, |
| 407 | { BITVAL_EOT } |
| 408 | }}, |
| 409 | { 23, 8, RESERVED }, |
| 410 | { 15, 1, "CFG Lock", "R/WO", PRESENT_DEC, { |
| 411 | { MSR1(0), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) \ |
| 412 | are writeable" }, |
| 413 | { MSR1(1), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) \ |
| 414 | are locked until reset" }, |
| 415 | { BITVAL_EOT } |
| 416 | }}, |
| 417 | { 14, 4, RESERVED }, |
| 418 | { 10, 1, "I/O MWAIT Redirection", "R/W", PRESENT_DEC, { |
| 419 | { MSR1(0), "I/O MWAIT Redirection disabled" }, |
| 420 | { MSR1(1), "CPU will map IO_read instructions sent to \ |
| 421 | IO register specified by MSR_PMG_IO_CAPTURE_BASE \ |
| 422 | to MWAIT instructions" }, |
| 423 | { BITVAL_EOT } |
| 424 | }}, |
| 425 | { 9, 7, RESERVED }, |
| 426 | { 2, 3, "Package C-State limit", "R/W", PRESENT_BIN, { |
| 427 | /* Specifies the lowest processor specific C-state code name |
| 428 | * (consuming the least power) for the package. The default is set |
| 429 | * as factory-configured package C-state limit. |
| 430 | */ |
| 431 | { MSR1(0), "C0 (no package C-state support)" }, |
| 432 | { MSR1(1), "C1 (behavior is the same as C0)" }, |
| 433 | { MSR1(2), "C3" }, |
| 434 | { MSR1(3), "C6" }, |
| 435 | { MSR1(4), "C7" }, |
| 436 | { MSR1(5), "Reserved" }, |
| 437 | { MSR1(6), "Reserved" }, |
| 438 | { MSR1(7), "No package C-state limit" }, |
| 439 | { BITVAL_EOT } |
| 440 | /* Note: this field cannot be used to limit |
| 441 | * package C-state to C3 |
| 442 | */ |
| 443 | }}, |
| 444 | { BITS_EOT } |
| 445 | }}, |
| 446 | {0xe4, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMG_IO_CAPTURE_BASE", |
| 447 | "Power Management IO Redirection in C-state", { |
| 448 | { 63, 45, RESERVED }, |
| 449 | { 18, 3, "C-state Range", "R/W", PRESENT_BIN, { |
| 450 | /* Specifies the encoding value of the maximum C-State code name |
| 451 | * to be included when IO read to MWAIT redirection is enabled by |
| 452 | * MSR_PMG_CST_CONFIG_CONTROL[bit10]. |
| 453 | */ |
| 454 | { MSR1(0), "C3 is the max C-State to include" }, |
| 455 | { MSR1(1), "C6 is the max C-State to include" }, |
| 456 | { MSR1(2), "C7 is the max C-State to include" }, |
| 457 | { BITVAL_EOT } |
| 458 | }}, |
| 459 | { 15, 16, "LVL_2 Base Address", "R/W", PRESENT_HEX, { |
| 460 | /* Specifies the base address visible to software for IO redirection. |
| 461 | * If I/O MWAIT Redirection is enabled, reads to this address will be |
| 462 | * consumed by the power management logic and decoded to MWAIT |
| 463 | * instructions. When IO port address redirection is enabled, |
| 464 | * this is the I/O port address reported to the OS/software. |
| 465 | */ |
| 466 | { BITVAL_EOT } |
| 467 | }}, |
| 468 | { BITS_EOT } |
| 469 | }}, |
| 470 | {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { |
| 471 | { BITS_EOT } |
| 472 | }}, |
| 473 | {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { |
| 474 | { BITS_EOT } |
| 475 | }}, |
| 476 | {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { |
| 477 | { BITS_EOT } |
| 478 | }}, |
| 479 | {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { |
| 480 | { BITS_EOT } |
| 481 | }}, |
| 482 | {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { |
| 483 | { BITS_EOT } |
| 484 | }}, |
| 485 | {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { |
| 486 | { BITS_EOT } |
| 487 | }}, |
| 488 | {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { |
| 489 | { BITS_EOT } |
| 490 | }}, |
| 491 | {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { |
| 492 | { 63, 61, RESERVED }, |
| 493 | { 2, 1, "MCIP", "R/W", PRESENT_BIN, { |
| 494 | /* When set, bit indicates that a machine check has been |
| 495 | * generated. If a second machine check is detected while |
| 496 | * this bit is still set, the processor enters a shutdown state. |
| 497 | * Software should write this bit to 0 after processing |
| 498 | * a machine check exception. |
| 499 | */ |
| 500 | { MSR1(0), "Nothing" }, |
| 501 | { MSR1(1), "Machine check has been generated" }, |
| 502 | { BITVAL_EOT } |
| 503 | }}, |
| 504 | { 1, 1, "EPIV", "R/W", PRESENT_BIN, { |
| 505 | /* When set, bit indicates that the instruction addressed |
| 506 | * by the instruction pointer pushed on the stack (when |
| 507 | * the machine check was generated) is directly associated |
| 508 | * with the error |
| 509 | */ |
| 510 | { MSR1(0), "Nothing" }, |
| 511 | { MSR1(1), "Instruction addressed directly associated with the error" }, |
| 512 | { BITVAL_EOT } |
| 513 | }}, |
| 514 | { 0, 1, "RIPV", "R/W", PRESENT_BIN, { |
| 515 | /* When set, bit indicates that the instruction addressed |
| 516 | * by the instruction pointer pushed on the stack (when |
| 517 | * the machine check was generated) can be used to restart |
| 518 | * the program. If cleared, the program cannot be reliably restarted |
| 519 | */ |
| 520 | { MSR1(0), "Program cannot be reliably restarted" }, |
| 521 | { MSR1(1), "Instruction addressed can be used to restart the program" }, |
| 522 | { BITVAL_EOT } |
| 523 | }}, |
| 524 | { BITS_EOT } |
| 525 | }}, |
| 526 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 527 | {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", |
| 528 | "Performance Event Select Register 0", { |
| 529 | { 63, 32, RESERVED }, |
| 530 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 531 | /* When CMASK is not zero, the corresponding performance |
| 532 | * counter 0 increments each cycle if the event count |
| 533 | * is greater than or equal to the CMASK. |
| 534 | */ |
| 535 | { BITVAL_EOT } |
| 536 | }}, |
| 537 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 538 | { MSR1(0), "CMASK using as is" }, |
| 539 | { MSR1(1), "CMASK inerting" }, |
| 540 | { BITVAL_EOT } |
| 541 | }}, |
| 542 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 543 | { MSR1(0), "No commence counting" }, |
| 544 | { MSR1(1), "Commence counting" }, |
| 545 | { BITVAL_EOT } |
| 546 | }}, |
| 547 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 548 | { BITVAL_EOT } |
| 549 | }}, |
| 550 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 551 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 552 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 553 | { BITVAL_EOT } |
| 554 | }}, |
| 555 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 556 | { MSR1(0), "Disabled pin control" }, |
| 557 | { MSR1(1), "Enabled pin control" }, |
| 558 | { BITVAL_EOT } |
| 559 | }}, |
| 560 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 561 | { MSR1(0), "Disabled edge detection" }, |
| 562 | { MSR1(1), "Enabled edge detection" }, |
| 563 | { BITVAL_EOT } |
| 564 | }}, |
| 565 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 566 | { MSR1(0), "Nothing" }, |
| 567 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 568 | { BITVAL_EOT } |
| 569 | }}, |
| 570 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 571 | { MSR1(0), "Nothing" }, |
| 572 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 573 | { BITVAL_EOT } |
| 574 | }}, |
| 575 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 576 | /* Qualifies the microarchitectural condition |
| 577 | * to detect on the selected event logic. */ |
| 578 | { BITVAL_EOT } |
| 579 | }}, |
| 580 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 581 | /* Selects a performance event logic unit. */ |
| 582 | { BITVAL_EOT } |
| 583 | }}, |
| 584 | { BITS_EOT } |
| 585 | }}, |
| 586 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 587 | {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", |
| 588 | "Performance Event Select Register 1", { |
| 589 | { 63, 32, RESERVED }, |
| 590 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 591 | /* When CMASK is not zero, the corresponding performance |
| 592 | * counter 1 increments each cycle if the event count |
| 593 | * is greater than or equal to the CMASK. |
| 594 | */ |
| 595 | { BITVAL_EOT } |
| 596 | }}, |
| 597 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 598 | { MSR1(0), "CMASK using as is" }, |
| 599 | { MSR1(1), "CMASK inerting" }, |
| 600 | { BITVAL_EOT } |
| 601 | }}, |
| 602 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 603 | { MSR1(0), "No commence counting" }, |
| 604 | { MSR1(1), "Commence counting" }, |
| 605 | { BITVAL_EOT } |
| 606 | }}, |
| 607 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 608 | { BITVAL_EOT } |
| 609 | }}, |
| 610 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 611 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 612 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 613 | { BITVAL_EOT } |
| 614 | }}, |
| 615 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 616 | { MSR1(0), "Disabled pin control" }, |
| 617 | { MSR1(1), "Enabled pin control" }, |
| 618 | { BITVAL_EOT } |
| 619 | }}, |
| 620 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 621 | { MSR1(0), "Disabled edge detection" }, |
| 622 | { MSR1(1), "Enabled edge detection" }, |
| 623 | { BITVAL_EOT } |
| 624 | }}, |
| 625 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 626 | { MSR1(0), "Nothing" }, |
| 627 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 628 | { BITVAL_EOT } |
| 629 | }}, |
| 630 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 631 | { MSR1(0), "Nothing" }, |
| 632 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 633 | { BITVAL_EOT } |
| 634 | }}, |
| 635 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 636 | /* Qualifies the microarchitectural condition |
| 637 | * to detect on the selected event logic. */ |
| 638 | { BITVAL_EOT } |
| 639 | }}, |
| 640 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 641 | /* Selects a performance event logic unit. */ |
| 642 | { BITVAL_EOT } |
| 643 | }}, |
| 644 | { BITS_EOT } |
| 645 | }}, |
| 646 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 647 | {0x188, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL2", |
| 648 | "Performance Event Select Register 2", { |
| 649 | { 63, 32, RESERVED }, |
| 650 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 651 | /* When CMASK is not zero, the corresponding performance |
| 652 | * counter 2 increments each cycle if the event count |
| 653 | * is greater than or equal to the CMASK. |
| 654 | */ |
| 655 | { BITVAL_EOT } |
| 656 | }}, |
| 657 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 658 | { MSR1(0), "CMASK using as is" }, |
| 659 | { MSR1(1), "CMASK inerting" }, |
| 660 | { BITVAL_EOT } |
| 661 | }}, |
| 662 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 663 | { MSR1(0), "No commence counting" }, |
| 664 | { MSR1(1), "Commence counting" }, |
| 665 | { BITVAL_EOT } |
| 666 | }}, |
| 667 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 668 | { BITVAL_EOT } |
| 669 | }}, |
| 670 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 671 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 672 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 673 | { BITVAL_EOT } |
| 674 | }}, |
| 675 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 676 | { MSR1(0), "Disabled pin control" }, |
| 677 | { MSR1(1), "Enabled pin control" }, |
| 678 | { BITVAL_EOT } |
| 679 | }}, |
| 680 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 681 | { MSR1(0), "Disabled edge detection" }, |
| 682 | { MSR1(1), "Enabled edge detection" }, |
| 683 | { BITVAL_EOT } |
| 684 | }}, |
| 685 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 686 | { MSR1(0), "Nothing" }, |
| 687 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 688 | { BITVAL_EOT } |
| 689 | }}, |
| 690 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 691 | { MSR1(0), "Nothing" }, |
| 692 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 693 | { BITVAL_EOT } |
| 694 | }}, |
| 695 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 696 | /* Qualifies the microarchitectural condition |
| 697 | * to detect on the selected event logic. */ |
| 698 | { BITVAL_EOT } |
| 699 | }}, |
| 700 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 701 | /* Selects a performance event logic unit. */ |
| 702 | { BITVAL_EOT } |
| 703 | }}, |
| 704 | { BITS_EOT } |
| 705 | }}, |
| 706 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 707 | {0x189, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL3", |
| 708 | "Performance Event Select Register 3", { |
| 709 | { 63, 32, RESERVED }, |
| 710 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 711 | /* When CMASK is not zero, the corresponding performance |
| 712 | * counter 3 increments each cycle if the event count |
| 713 | * is greater than or equal to the CMASK. |
| 714 | */ |
| 715 | { BITVAL_EOT } |
| 716 | }}, |
| 717 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 718 | { MSR1(0), "CMASK using as is" }, |
| 719 | { MSR1(1), "CMASK inerting" }, |
| 720 | { BITVAL_EOT } |
| 721 | }}, |
| 722 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 723 | { MSR1(0), "No commence counting" }, |
| 724 | { MSR1(1), "Commence counting" }, |
| 725 | { BITVAL_EOT } |
| 726 | }}, |
| 727 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 728 | { BITVAL_EOT } |
| 729 | }}, |
| 730 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 731 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 732 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 733 | { BITVAL_EOT } |
| 734 | }}, |
| 735 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 736 | { MSR1(0), "Disabled pin control" }, |
| 737 | { MSR1(1), "Enabled pin control" }, |
| 738 | { BITVAL_EOT } |
| 739 | }}, |
| 740 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 741 | { MSR1(0), "Disabled edge detection" }, |
| 742 | { MSR1(1), "Enabled edge detection" }, |
| 743 | { BITVAL_EOT } |
| 744 | }}, |
| 745 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 746 | { MSR1(0), "Nothing" }, |
| 747 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 748 | { BITVAL_EOT } |
| 749 | }}, |
| 750 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 751 | { MSR1(0), "Nothing" }, |
| 752 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 753 | { BITVAL_EOT } |
| 754 | }}, |
| 755 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 756 | /* Qualifies the microarchitectural condition |
| 757 | * to detect on the selected event logic. */ |
| 758 | { BITVAL_EOT } |
| 759 | }}, |
| 760 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 761 | /* Selects a performance event logic unit. */ |
| 762 | { BITVAL_EOT } |
| 763 | }}, |
| 764 | { BITS_EOT } |
| 765 | }}, |
| 766 | {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { |
| 767 | { 63, 48, RESERVED }, |
| 768 | { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX, { |
| 769 | { BITVAL_EOT } |
| 770 | }}, |
| 771 | { BITS_EOT } |
| 772 | }}, |
| 773 | {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { |
| 774 | { BITS_EOT } |
| 775 | }}, |
| 776 | {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", |
| 777 | "Clock Modulation", { |
| 778 | { 63, 59, RESERVED }, |
| 779 | { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { |
| 780 | { MSR1(0), "On demand Clock Modulation is disabled" }, |
| 781 | { MSR1(1), "On demand Clock Modulation is enabled" }, |
| 782 | { BITVAL_EOT } |
| 783 | }}, |
| 784 | { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, { |
| 785 | { BITVAL_EOT } |
| 786 | }}, |
| 787 | { 0, 1, RESERVED }, |
| 788 | { BITS_EOT } |
| 789 | }}, |
| 790 | {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", |
| 791 | "Thermal Interrupt Control", { |
| 792 | { BITS_EOT } |
| 793 | }}, |
| 794 | {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", |
| 795 | "Thermal Monitor Status", { |
| 796 | { BITS_EOT } |
| 797 | }}, |
| 798 | {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { |
| 799 | { BITS_EOT } |
| 800 | }}, |
| 801 | {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", |
| 802 | "Enable miscellaneous processor features", { |
| 803 | { 63, 25, RESERVED }, |
| 804 | /* Note: [38] bit using for whole package, |
| 805 | * while some other bits can be Core or Thread |
| 806 | * specific. |
| 807 | */ |
| 808 | { 38, 1, "Turbo Mode", "R/W", PRESENT_BIN, { |
| 809 | /* When set to a 0 on processors that support IDA, |
| 810 | * CPUID.06H: EAX[1] reports the processor's |
| 811 | * support of turbo mode is enabled. |
| 812 | */ |
| 813 | { MSR1(0), "Turbo Mode enabled" }, |
| 814 | /* When set 1 on processors that support Intel Turbo Boost |
| 815 | * technology, the turbo mode feature is disabled and |
| 816 | * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). |
| 817 | */ |
| 818 | { MSR1(1), "Turbo Mode disabled" }, |
| 819 | { BITVAL_EOT } |
| 820 | /* Note: the power-on default value is used by BIOS to detect |
| 821 | * hardware support of turbo mode. If power-on default value is 1, |
| 822 | * turbo mode is available in the processor. If power-on default |
| 823 | * value is 0, turbo mode not available. |
| 824 | */ |
| 825 | }}, |
| 826 | { 37, 3, RESERVED }, |
| 827 | { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, { |
| 828 | { BITVAL_EOT } |
| 829 | }}, |
| 830 | { 33, 10, RESERVED }, |
| 831 | { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, { |
| 832 | { BITVAL_EOT } |
| 833 | }}, |
| 834 | { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, { |
| 835 | { BITVAL_EOT } |
| 836 | }}, |
| 837 | { 21, 3, RESERVED }, |
| 838 | { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, { |
| 839 | { BITVAL_EOT } |
| 840 | }}, |
| 841 | { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, { |
| 842 | { BITVAL_EOT } |
| 843 | }}, |
| 844 | /* Note: [16] bit using for whole package, |
| 845 | * while some other bits can be Core or Thread |
| 846 | * specific. |
| 847 | */ |
| 848 | { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W", |
| 849 | PRESENT_BIN, { |
| 850 | { BITVAL_EOT } |
| 851 | }}, |
| 852 | { 15, 3, RESERVED }, |
| 853 | { 12, 1, "Precise Event Based Sampling Unavailable", "R/O", |
| 854 | PRESENT_BIN, { |
| 855 | { BITVAL_EOT } |
| 856 | }}, |
| 857 | { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, { |
| 858 | { BITVAL_EOT } |
| 859 | }}, |
| 860 | { 10, 3, RESERVED }, |
| 861 | { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, { |
| 862 | { BITVAL_EOT } |
| 863 | }}, |
| 864 | { 6, 3, RESERVED }, |
| 865 | { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W" |
| 866 | , PRESENT_BIN, { |
| 867 | { BITVAL_EOT } |
| 868 | }}, |
| 869 | { 2, 2, RESERVED }, |
| 870 | { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, { |
| 871 | { BITVAL_EOT } |
| 872 | }}, |
| 873 | { BITS_EOT } |
| 874 | }}, |
| 875 | {0x1a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TEMPERATURE_TARGET", "", { |
| 876 | { 63, 40, RESERVED }, |
| 877 | { 23, 8, "Temperature Target", "R", PRESENT_DEC, { |
| 878 | /* The minimum temperature at which PROCHOT# will be |
| 879 | * asserted. The value in degree C. |
| 880 | */ |
| 881 | { BITVAL_EOT } |
| 882 | }}, |
| 883 | { 15, 16, RESERVED }, |
| 884 | { BITS_EOT } |
| 885 | }}, |
| 886 | {0x1a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_OFFCORE_RSP_O", |
| 887 | "Offcore Response Event Select Register", { |
| 888 | { BITS_EOT } |
| 889 | }}, |
| 890 | {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MISC_PWR_MGMT", "", { |
| 891 | { 63, 62, RESERVED }, |
| 892 | { 1, 1, "Energy/Performance Bias Enable", "R/W", PRESENT_BIN, { |
| 893 | /* This bit status is also reflected |
| 894 | * by CPUID.(EAX=06h):ECX[3] |
| 895 | */ |
| 896 | { MSR1(0), "IA32_ENERGY_PERF_BIAS (0x1b0) is invisible \ |
| 897 | for Ring 0 software" }, |
| 898 | { MSR1(1), "IA32_ENERGY_PERF_BIAS (0x1b0) accessible \ |
| 899 | by Ring 0 software" }, |
| 900 | { BITVAL_EOT } |
| 901 | }}, |
| 902 | { 0, 1, "EIST Hardware Coordination Disable", "R/W", PRESENT_BIN, { |
| 903 | { MSR1(0), "Hardware Coordination of EIST request \ |
| 904 | from processor cores is enabled" }, |
| 905 | { MSR1(1), "Hardware Coordination of EIST request \ |
| 906 | from processor cores is disabled" }, |
| 907 | { BITVAL_EOT } |
| 908 | }}, |
| 909 | { BITS_EOT } |
| 910 | }}, |
| 911 | {0x1c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LBR_SELECT", |
| 912 | "Last Branch Record Filtering Select Register", { |
| 913 | /* "Nehalem support filtering of LBR based on combination of CPL |
| 914 | * and branch type conditions. When LBR filtering is enabled, |
| 915 | * the LBR stack only captures the subset of branches |
| 916 | * that are specified by MSR_LBR_SELECT." |
| 917 | * |
| 918 | * -- Section 17.6.2 of Intel 64 and IA-32 Architectures Software |
| 919 | * Developer's Manual, Volume 3 |
| 920 | */ |
| 921 | { BITS_EOT } |
| 922 | }}, |
| 923 | {0x1c9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LASTBRANCH_TOS", |
| 924 | "Last Branch Record Stack TOS", { |
| 925 | /* Contains an index (bits 0-3) that points to the MSR containing |
| 926 | * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680). |
| 927 | */ |
| 928 | { BITS_EOT } |
| 929 | }}, |
| 930 | {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", |
| 931 | "Debug/Trace/Profile Resource Control", { |
| 932 | /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */ |
| 933 | { 63, 49, RESERVED }, |
| 934 | /* Only if IA32_PERF_CAPABILITIES[12] = 1 */ |
| 935 | { 14, 1, "FREEZE_WHILE_SMM", "R/O", PRESENT_BIN, { |
| 936 | { MSR1(0), "Nothing" }, |
| 937 | { MSR1(1), "Freeze perfmon and trace messages while in SMM" }, |
| 938 | { BITVAL_EOT } |
| 939 | }}, |
| 940 | { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { |
| 941 | { MSR1(0), "Nothing" }, |
| 942 | { MSR1(1), "Logical processor can receive and generate PMI \ |
| 943 | on behalf of the uncore" }, |
| 944 | { BITVAL_EOT } |
| 945 | }}, |
| 946 | /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ |
| 947 | { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { |
| 948 | { MSR1(0), "Nothing" }, |
| 949 | { MSR1(1), "Each ENABLE bit of the global counter control MSR \ |
| 950 | are frozen (address 0x3bf) on PMI request" }, |
| 951 | { BITVAL_EOT } |
| 952 | }}, |
| 953 | /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ |
| 954 | { 11, 1, "FREEZE_LBRS_ON_PMI", "R/O", PRESENT_BIN, { |
| 955 | { MSR1(0), "Nothing" }, |
| 956 | { MSR1(1), "LBR stack is frozen on PMI request" }, |
| 957 | { BITVAL_EOT } |
| 958 | }}, |
| 959 | { 10, 1, "BTS_OFF_USR", "R/O", PRESENT_BIN, { |
| 960 | { MSR1(0), "Nothing" }, |
| 961 | { MSR1(1), "BTS or BTM is skipped if CPL > 0" }, |
| 962 | { BITVAL_EOT } |
| 963 | }}, |
| 964 | { 9, 1, "BTS_OFF_OS", "R/O", PRESENT_BIN, { |
| 965 | { MSR1(0), "Nothing" }, |
| 966 | { MSR1(1), "BTS or BTM is skipped if CPL = 0" }, |
| 967 | { BITVAL_EOT } |
| 968 | }}, |
| 969 | { 8, 1, "BTINT", "R/O", PRESENT_BIN, { |
| 970 | { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, |
| 971 | { MSR1(1), "An interrupt is generated by the BTS facility \ |
| 972 | when the BTS buffer is full" }, |
| 973 | { BITVAL_EOT } |
| 974 | }}, |
| 975 | { 7, 1, "BTS", "R/O", PRESENT_BIN, { |
| 976 | { MSR1(0), "Logging of BTMs (branch trace messages) \ |
| 977 | in BTS buffer is disabled" }, |
| 978 | { MSR1(1), "Logging of BTMs (branch trace messages) \ |
| 979 | in BTS buffer is enabled" }, |
| 980 | { BITVAL_EOT } |
| 981 | }}, |
| 982 | { 6, 1, "TR", "R/O", PRESENT_BIN, { |
| 983 | { MSR1(0), "Branch trace messages are disabled" }, |
| 984 | { MSR1(1), "Branch trace messages are enabled" }, |
| 985 | { BITVAL_EOT } |
| 986 | }}, |
| 987 | { 5, 4, RESERVED }, |
| 988 | { 1, 1, "BTF", "R/O", PRESENT_BIN, { |
| 989 | { MSR1(0), "Nothing" }, |
| 990 | { MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ |
| 991 | branches instead of single-step on instructions" }, |
| 992 | { BITVAL_EOT } |
| 993 | }}, |
| 994 | { 0, 1, "LBR", "R/O", PRESENT_BIN, { |
| 995 | { MSR1(0), "Nothing" }, |
| 996 | { MSR1(1), "Enabled recording a running trace of the most \ |
| 997 | recent branches taken by the processor in the LBR stack" }, |
| 998 | { BITVAL_EOT } |
| 999 | }}, |
| 1000 | { BITS_EOT } |
| 1001 | }}, |
| 1002 | {0x1dd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_FROM_LIP", |
| 1003 | "Last Exception Record From Linear IP", { |
| 1004 | /* Contains a pointer to the last branch instruction |
| 1005 | * that the processor executed prior to the last exception |
| 1006 | * that was generated or the last interrupt that was handled. |
| 1007 | */ |
| 1008 | { BITS_EOT } |
| 1009 | }}, |
| 1010 | {0x1de, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_TO_LIP", |
| 1011 | "Last Exception Record To Linear IP", { |
| 1012 | /* This area contains a pointer to the target of the |
| 1013 | * last branch instruction that the processor executed |
| 1014 | * prior to the last exception that was generated or |
| 1015 | * the last interrupt that was handled |
| 1016 | */ |
| 1017 | { BITS_EOT } |
| 1018 | }}, |
| 1019 | {0x1f2, MSRTYPE_RDONLY, MSR2(0,0), "IA32_SMRR_PHYS_BASE", |
| 1020 | "SMRR Base Address", { |
| 1021 | /* Base address of SMM memory range. |
| 1022 | * Writeable only in SMM, so marking it as read-only */ |
| 1023 | { 63, 32, RESERVED }, |
| 1024 | { 31, 20, "SMRR physical Base Address", "R/O", PRESENT_HEX, { |
| 1025 | { BITVAL_EOT } |
| 1026 | }}, |
| 1027 | { 11, 4, RESERVED }, |
| 1028 | { 7, 8, "Memory type of the range", "R/O", PRESENT_HEX, { |
| 1029 | { BITVAL_EOT } |
| 1030 | }}, |
| 1031 | { BITS_EOT } |
| 1032 | }}, |
| 1033 | {0x1f3, MSRTYPE_RDONLY, MSR2(0,0), "IA32_SMRR_PHYS_MASK", |
| 1034 | "SMRR Range Mask", { |
| 1035 | /* Range Mask of SMM memory range. |
| 1036 | * Writeable only in SMM, so marking it as read-only */ |
| 1037 | { 63, 32, RESERVED }, |
| 1038 | { 31, 20, "SMRR address range mask", "R/O", PRESENT_HEX, { |
| 1039 | { BITVAL_EOT } |
| 1040 | }}, |
| 1041 | { 11, 1, "Is Valid SMRR range mask", "R/O", PRESENT_BIN, { |
| 1042 | { MSR1(0), "SMRR range mask is disabled" }, |
| 1043 | { MSR1(1), "SMRR range mask is enabled" }, |
| 1044 | { BITVAL_EOT } |
| 1045 | }}, |
| 1046 | { 10, 11, RESERVED }, |
| 1047 | { BITS_EOT } |
| 1048 | }}, |
| 1049 | {0x1f8, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PLATFORM_DCA_CAP", |
| 1050 | "DCA Capability", { |
| 1051 | { BITS_EOT } |
| 1052 | }}, |
| 1053 | {0x1f9, MSRTYPE_RDONLY, MSR2(0,0), "IA32_CPU_DCA_CAP", |
| 1054 | "Support og Prefetch-Hint type", { |
| 1055 | /* If set, CPU supports Prefetch-Hint type. |
| 1056 | * TODO: As it is undocumented, which bit (or bits) |
| 1057 | * are needed to "be set", we need collect some |
| 1058 | * outputs of msrtool to understand possible msr values. |
| 1059 | */ |
| 1060 | { BITS_EOT } |
| 1061 | }}, |
| 1062 | {0x1fa, MSRTYPE_RDWR, MSR2(0,0), "IA32_DCA_0_CAP", |
| 1063 | "DCA type 0 Status and Control register", { |
| 1064 | /* This register defined as introduced only |
| 1065 | * in 06_2EH Nehalem model (latest), so be careful! |
| 1066 | */ |
| 1067 | { 31, 5, RESERVED }, |
| 1068 | { 26, 1, "HW_BLOCK", "R/O", PRESENT_BIN, { |
| 1069 | /* Hardware block of DCA */ |
| 1070 | { MSR1(0), "DCA is not blocked by HW" }, |
| 1071 | { MSR1(1), "DCA is blocked by HW (e.g. CR0.CD=1)" }, |
| 1072 | { BITVAL_EOT } |
| 1073 | }}, |
| 1074 | { 25, 1, RESERVED }, |
| 1075 | { 24, 1, "SW_BLOCK", "R/W", PRESENT_BIN, { |
| 1076 | /* Software block of DCA */ |
| 1077 | { MSR1(0), "DCA is not blocked by SW" }, |
| 1078 | { MSR1(1), "DCA is blocked by SW" }, |
| 1079 | { BITVAL_EOT } |
| 1080 | }}, |
| 1081 | { 23, 7, RESERVED }, |
| 1082 | { 16, 4, "DCA_RELAY", "R/W", PRESENT_HEX, { |
| 1083 | /* Writes will update the register |
| 1084 | * but have no HW side-effect */ |
| 1085 | { BITVAL_EOT } |
| 1086 | }}, |
| 1087 | { 12, 2, RESERVED }, |
| 1088 | { 10, 4, "DCA_QUEUE_SIZE", "R/O", PRESENT_DEC, { |
| 1089 | { BITVAL_EOT } |
| 1090 | }}, |
| 1091 | { 6, 4, "DCA_TYPE", "R/O", PRESENT_HEX, { |
| 1092 | { BITVAL_EOT } |
| 1093 | }}, |
| 1094 | { 2, 2, "TRANSACTION", "R/O", PRESENT_HEX, { |
| 1095 | { BITVAL_EOT } |
| 1096 | }}, |
| 1097 | { 0, 1, "DCA_ACTIVE", "R/O", PRESENT_BIN, { |
| 1098 | /* Set by HW when DCA is fuse-enabled and |
| 1099 | * no defeauteres are set */ |
| 1100 | { MSR1(0), "DCA inactive" }, |
| 1101 | { MSR1(1), "DCA inactive" }, |
| 1102 | { BITVAL_EOT } |
| 1103 | }}, |
| 1104 | { BITS_EOT } |
| 1105 | }}, |
| 1106 | {0x1fc, MSRTYPE_RDWR, MSR2(0,0), "MSR_POWER_CTL", |
| 1107 | "Power Control Register", { |
| 1108 | { 63, 62, RESERVED }, |
| 1109 | /* Whole package bit */ |
| 1110 | { 1, 1, "C1E Enable", "R/W", PRESENT_BIN, { |
| 1111 | { MSR1(0), "Nothing" }, |
| 1112 | { MSR1(1), "CPU switch to the Minimum Enhaced Intel \ |
| 1113 | SpeedStep Technology operating point when all \ |
| 1114 | execution cores enter MWAIT (C1)" }, |
| 1115 | { BITVAL_EOT } |
| 1116 | }}, |
| 1117 | { 0, 1, RESERVED }, |
| 1118 | { BITS_EOT } |
| 1119 | }}, |
| 1120 | {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { |
| 1121 | { BITS_EOT } |
| 1122 | }}, |
| 1123 | {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { |
| 1124 | { BITS_EOT } |
| 1125 | }}, |
| 1126 | {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { |
| 1127 | { BITS_EOT } |
| 1128 | }}, |
| 1129 | {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { |
| 1130 | { BITS_EOT } |
| 1131 | }}, |
| 1132 | {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { |
| 1133 | { BITS_EOT } |
| 1134 | }}, |
| 1135 | {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { |
| 1136 | { BITS_EOT } |
| 1137 | }}, |
| 1138 | {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { |
| 1139 | { BITS_EOT } |
| 1140 | }}, |
| 1141 | {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { |
| 1142 | { BITS_EOT } |
| 1143 | }}, |
| 1144 | {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { |
| 1145 | { BITS_EOT } |
| 1146 | }}, |
| 1147 | {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { |
| 1148 | { BITS_EOT } |
| 1149 | }}, |
| 1150 | {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { |
| 1151 | { BITS_EOT } |
| 1152 | }}, |
| 1153 | {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { |
| 1154 | { BITS_EOT } |
| 1155 | }}, |
| 1156 | {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { |
| 1157 | { BITS_EOT } |
| 1158 | }}, |
| 1159 | {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { |
| 1160 | { BITS_EOT } |
| 1161 | }}, |
| 1162 | {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { |
| 1163 | { BITS_EOT } |
| 1164 | }}, |
| 1165 | {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { |
| 1166 | { BITS_EOT } |
| 1167 | }}, |
| 1168 | /* if IA32_MTRR_CAP[7:0] > 8 */ |
| 1169 | {0x210, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE8", "", { |
| 1170 | { BITS_EOT } |
| 1171 | }}, |
| 1172 | /* if IA32_MTRR_CAP[7:0] > 8 */ |
| 1173 | {0x211, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK8", "", { |
| 1174 | { BITS_EOT } |
| 1175 | }}, |
| 1176 | /* if IA32_MTRR_CAP[7:0] > 9 */ |
| 1177 | {0x212, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE9", "", { |
| 1178 | { BITS_EOT } |
| 1179 | }}, |
| 1180 | /* if IA32_MTRR_CAP[7:0] > 9 */ |
| 1181 | {0x213, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK9", "", { |
| 1182 | { BITS_EOT } |
| 1183 | }}, |
| 1184 | {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { |
| 1185 | { BITS_EOT } |
| 1186 | }}, |
| 1187 | {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { |
| 1188 | { BITS_EOT } |
| 1189 | }}, |
| 1190 | {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { |
| 1191 | { BITS_EOT } |
| 1192 | }}, |
| 1193 | {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { |
| 1194 | { BITS_EOT } |
| 1195 | }}, |
| 1196 | {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { |
| 1197 | { BITS_EOT } |
| 1198 | }}, |
| 1199 | {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { |
| 1200 | { BITS_EOT } |
| 1201 | }}, |
| 1202 | {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { |
| 1203 | { BITS_EOT } |
| 1204 | }}, |
| 1205 | {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { |
| 1206 | { BITS_EOT } |
| 1207 | }}, |
| 1208 | {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { |
| 1209 | { BITS_EOT } |
| 1210 | }}, |
| 1211 | {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { |
| 1212 | { BITS_EOT } |
| 1213 | }}, |
| 1214 | {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { |
| 1215 | { BITS_EOT } |
| 1216 | }}, |
| 1217 | {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { |
| 1218 | { 63, 5, RESERVED }, |
| 1219 | { 58, 3, "PA7", "R/W", PRESENT_BIN, { |
| 1220 | { BITVAL_EOT } |
| 1221 | }}, |
| 1222 | { 55, 5, RESERVED }, |
| 1223 | { 40, 3, "PA6", "R/W", PRESENT_BIN, { |
| 1224 | { BITVAL_EOT } |
| 1225 | }}, |
| 1226 | { 47, 5, RESERVED }, |
| 1227 | { 42, 3, "PA5", "R/W", PRESENT_BIN, { |
| 1228 | { BITVAL_EOT } |
| 1229 | }}, |
| 1230 | { 39, 5, RESERVED }, |
| 1231 | { 34, 3, "PA4", "R/W", PRESENT_BIN, { |
| 1232 | { BITVAL_EOT } |
| 1233 | }}, |
| 1234 | { 31, 5, RESERVED }, |
| 1235 | { 26, 3, "PA3", "R/W", PRESENT_BIN, { |
| 1236 | { BITVAL_EOT } |
| 1237 | }}, |
| 1238 | { 23, 5, RESERVED }, |
| 1239 | { 18, 3, "PA2", "R/W", PRESENT_BIN, { |
| 1240 | { BITVAL_EOT } |
| 1241 | }}, |
| 1242 | { 15, 5, RESERVED }, |
| 1243 | { 10, 3, "PA1", "R/W", PRESENT_BIN, { |
| 1244 | { BITVAL_EOT } |
| 1245 | }}, |
| 1246 | { 7, 5, RESERVED }, |
| 1247 | { 2, 3, "PA0", "R/W", PRESENT_BIN, { |
| 1248 | { BITVAL_EOT } |
| 1249 | }}, |
| 1250 | { BITS_EOT } |
| 1251 | }}, |
| 1252 | {0x282, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL2", "", { |
| 1253 | { 63, 33, RESERVED }, |
| 1254 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 1255 | { BITVAL_EOT } |
| 1256 | }}, |
| 1257 | { 29, 15, RESERVED }, |
| 1258 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 1259 | { BITVAL_EOT } |
| 1260 | }}, |
| 1261 | { BITS_EOT } |
| 1262 | }}, |
| 1263 | {0x283, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL2", "", { |
| 1264 | { 63, 33, RESERVED }, |
| 1265 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 1266 | { BITVAL_EOT } |
| 1267 | }}, |
| 1268 | { 29, 15, RESERVED }, |
| 1269 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 1270 | { BITVAL_EOT } |
| 1271 | }}, |
| 1272 | { BITS_EOT } |
| 1273 | }}, |
| 1274 | {0x284, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL2", "", { |
| 1275 | { 63, 33, RESERVED }, |
| 1276 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 1277 | { BITVAL_EOT } |
| 1278 | }}, |
| 1279 | { 29, 15, RESERVED }, |
| 1280 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 1281 | { BITVAL_EOT } |
| 1282 | }}, |
| 1283 | { BITS_EOT } |
| 1284 | }}, |
| 1285 | {0x285, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL2", "", { |
| 1286 | { 63, 33, RESERVED }, |
| 1287 | { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { |
| 1288 | { BITVAL_EOT } |
| 1289 | }}, |
| 1290 | { 29, 15, RESERVED }, |
| 1291 | { 14, 15, "Corrected error count threshold", "R/W", PRESENT_HEX, { |
| 1292 | { BITVAL_EOT } |
| 1293 | }}, |
| 1294 | { BITS_EOT } |
| 1295 | }}, |
| 1296 | {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", |
| 1297 | "Default Memory Types", { |
| 1298 | { 63, 52, RESERVED }, |
| 1299 | { 11, 1, "MTRR Enable", "R/W", PRESENT_BIN, { |
| 1300 | { BITVAL_EOT } |
| 1301 | }}, |
| 1302 | { 10, 1, "Fixed Range MTRR Enable", "R/W", PRESENT_BIN, { |
| 1303 | { BITVAL_EOT } |
| 1304 | }}, |
| 1305 | { 9, 7, RESERVED }, |
| 1306 | { 2, 3, "Default Memory Type", "R/W", PRESENT_HEX, { |
| 1307 | { BITVAL_EOT } |
| 1308 | }}, |
| 1309 | { BITS_EOT } |
| 1310 | }}, |
| 1311 | /* if CPUID.0AH: EDX[4:0] > 0 */ |
| 1312 | {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ |
| 1313 | Performance Counter Register 0: Counts Instr_Retired.Any", { |
| 1314 | /* Also known as MSR_PERF_FIXED_CTR0 */ |
| 1315 | { BITS_EOT } |
| 1316 | }}, |
| 1317 | /* if CPUID.0AH: EDX[4:0] > 1 */ |
| 1318 | {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ |
| 1319 | Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { |
| 1320 | /* Also known as MSR_PERF_FIXED_CTR1 */ |
| 1321 | { BITS_EOT } |
| 1322 | }}, |
| 1323 | /* if CPUID.0AH: EDX[4:0] > 2 */ |
| 1324 | {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ |
| 1325 | Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { |
| 1326 | /* Also known as MSR_PERF_FIXED_CTR2 */ |
| 1327 | { BITS_EOT } |
| 1328 | }}, |
| 1329 | /* if CPUID.01H: ECX[15] = 1 */ |
| 1330 | {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { |
| 1331 | /* Additional info available at Section 17.4.1 of |
| 1332 | * Intel 64 and IA-32 Architecures Software Developer's |
| 1333 | * Manual, Volume 3. |
| 1334 | */ |
| 1335 | { 63, 50, RESERVED }, |
| 1336 | { 13, 1, "Counter width", "R/O", PRESENT_BIN, { |
| 1337 | { MSR1(0), "Nothing" }, |
| 1338 | { MSR1(1), "Full width of counter writable via IA32_A_PMCx" }, |
| 1339 | { BITVAL_EOT } |
| 1340 | }}, |
| 1341 | { 12, 1, "SMM_FREEZE", "R/O", PRESENT_BIN, { |
| 1342 | { MSR1(0), "Nothing" }, |
| 1343 | { MSR1(1), "Freeze while SMM is supported" }, |
| 1344 | { BITVAL_EOT } |
| 1345 | }}, |
| 1346 | { 11, 4, "PEBS_REC_FORMAT", "R/O", PRESENT_HEX, { |
| 1347 | { BITVAL_EOT } |
| 1348 | }}, |
| 1349 | { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, { |
| 1350 | { BITVAL_EOT } |
| 1351 | }}, |
| 1352 | { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, { |
| 1353 | { BITVAL_EOT } |
| 1354 | }}, |
| 1355 | { 5, 6, "LBR Format", "R/O", PRESENT_HEX, { |
| 1356 | { BITVAL_EOT } |
| 1357 | }}, |
| 1358 | { BITS_EOT } |
| 1359 | }}, |
| 1360 | /* if CPUID.0AH: EAX[7:0] > 1*/ |
| 1361 | {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", |
| 1362 | "Fixed-Function-Counter Control Register", { |
| 1363 | /* Also known as MSR_PERF_FIXED_CTR_CTRL. |
| 1364 | * Counter increments while the results of ANDing respective enable bit |
| 1365 | * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits |
| 1366 | * in this MSR is true. */ |
| 1367 | { 63, 52, RESERVED }, |
| 1368 | { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, { |
| 1369 | { MSR1(0), "Nothing" }, |
| 1370 | { MSR1(1), "PMI when fixed counter 2 overflows is enabled" }, |
| 1371 | { BITVAL_EOT } |
| 1372 | }}, |
| 1373 | /* if CPUID.0AH EAX[7:0] > 2 */ |
| 1374 | { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { |
| 1375 | { MSR1(0), "Counter only increments the associated event \ |
| 1376 | conditions occuring in the logical processor which programmed the MSR" }, |
| 1377 | { MSR1(1), "Counting the associated event conditions \ |
| 1378 | occuring across all logical processors sharing a processor core" }, |
| 1379 | { BITVAL_EOT } |
| 1380 | }}, |
| 1381 | { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { |
| 1382 | { MSR1(0), "Nothing" }, |
| 1383 | { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" }, |
| 1384 | { BITVAL_EOT } |
| 1385 | }}, |
| 1386 | { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, { |
| 1387 | { MSR1(0), "Nothing" }, |
| 1388 | { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" }, |
| 1389 | { BITVAL_EOT } |
| 1390 | }}, |
| 1391 | { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, { |
| 1392 | { MSR1(0), "Nothing" }, |
| 1393 | { MSR1(1), "PMI when fixed counter 1 overflows is enabled" }, |
| 1394 | { BITVAL_EOT } |
| 1395 | }}, |
| 1396 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 1397 | { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { |
| 1398 | { MSR1(0), "Counter only increments the associated event \ |
| 1399 | conditions occuring in the logical processor which programmed the MSR" }, |
| 1400 | { MSR1(1), "Counting the associated event conditions \ |
| 1401 | occuring across all logical processors sharing a processor core" }, |
| 1402 | { BITVAL_EOT } |
| 1403 | }}, |
| 1404 | { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { |
| 1405 | { MSR1(0), "Nothing" }, |
| 1406 | { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" }, |
| 1407 | { BITVAL_EOT } |
| 1408 | }}, |
| 1409 | { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, { |
| 1410 | { MSR1(0), "Nothing" }, |
| 1411 | { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" }, |
| 1412 | { BITVAL_EOT } |
| 1413 | }}, |
| 1414 | { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, { |
| 1415 | { MSR1(0), "Nothing" }, |
| 1416 | { MSR1(1), "PMI when fixed counter 0 overflows is enabled" }, |
| 1417 | { BITVAL_EOT } |
| 1418 | }}, |
| 1419 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 1420 | { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { |
| 1421 | { MSR1(0), "Counter only increments the associated event \ |
| 1422 | conditions occuring in the logical processor which programmed the MSR" }, |
| 1423 | { MSR1(1), "Counting the associated event conditions \ |
| 1424 | occuring across all logical processors sharing a processor core" }, |
| 1425 | { BITVAL_EOT } |
| 1426 | }}, |
| 1427 | { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { |
| 1428 | { MSR1(0), "Nothing" }, |
| 1429 | { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" }, |
| 1430 | { BITVAL_EOT } |
| 1431 | }}, |
| 1432 | { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, { |
| 1433 | { MSR1(0), "Nothing" }, |
| 1434 | { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" }, |
| 1435 | { BITVAL_EOT } |
| 1436 | }}, |
| 1437 | { BITS_EOT } |
| 1438 | }}, |
| 1439 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1440 | {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", |
| 1441 | "Global Performance Counter Status", { |
| 1442 | /* Also known as MSR_PERF_GLOBAL_STATUS */ |
| 1443 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1444 | { 63, 1, "CondChg: Status bits of this register has changed", |
| 1445 | "R/O", PRESENT_BIN, { |
| 1446 | { BITVAL_EOT } |
| 1447 | }}, |
| 1448 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1449 | { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status", |
| 1450 | "R/O", PRESENT_BIN, { |
| 1451 | { BITVAL_EOT } |
| 1452 | }}, |
| 1453 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 1454 | { 61, 1, "Ovf_Uncore: Uncore counter overflow status", |
| 1455 | "R/O", PRESENT_BIN, { |
| 1456 | { BITVAL_EOT } |
| 1457 | }}, |
| 1458 | { 60, 26, RESERVED }, |
| 1459 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1460 | { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2", |
| 1461 | "R/O", PRESENT_BIN, { |
| 1462 | { BITVAL_EOT } |
| 1463 | }}, |
| 1464 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1465 | { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1", |
| 1466 | "R/O", PRESENT_BIN, { |
| 1467 | { BITVAL_EOT } |
| 1468 | }}, |
| 1469 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1470 | { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0", |
| 1471 | "R/O", PRESENT_BIN, { |
| 1472 | { BITVAL_EOT } |
| 1473 | }}, |
| 1474 | { 31, 28, RESERVED }, |
| 1475 | /* presented only in 06_2EH Nehalem model */ |
| 1476 | { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, { |
| 1477 | { BITVAL_EOT } |
| 1478 | }}, |
| 1479 | /* presented only in 06_2EH Nehalem model */ |
| 1480 | { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, { |
| 1481 | { BITVAL_EOT } |
| 1482 | }}, |
| 1483 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1484 | { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, { |
| 1485 | { BITVAL_EOT } |
| 1486 | }}, |
| 1487 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1488 | { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, { |
| 1489 | { BITVAL_EOT } |
| 1490 | }}, |
| 1491 | { BITS_EOT } |
| 1492 | }}, |
| 1493 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1494 | {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", |
| 1495 | "Global Performance Counter Control", { |
| 1496 | /* Counter increments while the result of ANDing respective |
| 1497 | * enable bit in this MSR with corresponding OS or USR bits |
| 1498 | * in general-purpose or fixed counter control MSR is true. |
| 1499 | */ |
| 1500 | { 63, 29, RESERVED }, |
| 1501 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1502 | { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, { |
| 1503 | { BITVAL_EOT } |
| 1504 | }}, |
| 1505 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1506 | { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, { |
| 1507 | { BITVAL_EOT } |
| 1508 | }}, |
| 1509 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1510 | { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, { |
| 1511 | { BITVAL_EOT } |
| 1512 | }}, |
| 1513 | { 31, 30, RESERVED }, |
| 1514 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1515 | { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, { |
| 1516 | { BITVAL_EOT } |
| 1517 | }}, |
| 1518 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1519 | { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, { |
| 1520 | { BITVAL_EOT } |
| 1521 | }}, |
| 1522 | { BITS_EOT } |
| 1523 | }}, |
| 1524 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1525 | {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", |
| 1526 | "Global Performance Counter Overflow Control", { |
| 1527 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1528 | { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { |
| 1529 | { BITVAL_EOT } |
| 1530 | }}, |
| 1531 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1532 | { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, { |
| 1533 | { BITVAL_EOT } |
| 1534 | }}, |
| 1535 | /* Presented only in 06_2EH Nehalem model */ |
| 1536 | { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, { |
| 1537 | { BITVAL_EOT } |
| 1538 | }}, |
| 1539 | { 60, 26, RESERVED }, |
| 1540 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1541 | { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, { |
| 1542 | { BITVAL_EOT } |
| 1543 | }}, |
| 1544 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1545 | { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, { |
| 1546 | { BITVAL_EOT } |
| 1547 | }}, |
| 1548 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 1549 | { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, { |
| 1550 | { BITVAL_EOT } |
| 1551 | }}, |
| 1552 | { 31, 30, RESERVED }, |
| 1553 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1554 | { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, { |
| 1555 | { BITVAL_EOT } |
| 1556 | }}, |
| 1557 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 1558 | { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, { |
| 1559 | { BITVAL_EOT } |
| 1560 | }}, |
| 1561 | { BITS_EOT } |
| 1562 | }}, |
| 1563 | /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures |
| 1564 | * Software Developer's Manual, Volume 3, |
| 1565 | * "Precise Event Based Sampling (PEBS)". |
| 1566 | */ |
| 1567 | {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { |
| 1568 | { 63, 28, RESERVED }, |
| 1569 | { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { |
| 1570 | { MSR1(0), "Disabled" }, |
| 1571 | { MSR1(1), "Enabled" }, |
| 1572 | { BITVAL_EOT } |
| 1573 | }}, |
| 1574 | { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, { |
| 1575 | { MSR1(0), "Disabled" }, |
| 1576 | { MSR1(1), "Enabled" }, |
| 1577 | { BITVAL_EOT } |
| 1578 | }}, |
| 1579 | { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, { |
| 1580 | { MSR1(0), "Disabled" }, |
| 1581 | { MSR1(1), "Enabled" }, |
| 1582 | { BITVAL_EOT } |
| 1583 | }}, |
| 1584 | { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, { |
| 1585 | { MSR1(0), "Disabled" }, |
| 1586 | { MSR1(1), "Enabled" }, |
| 1587 | { BITVAL_EOT } |
| 1588 | }}, |
| 1589 | { 31, 28, RESERVED }, |
| 1590 | { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, { |
| 1591 | { MSR1(0), "Disabled" }, |
| 1592 | { MSR1(1), "Enabled" }, |
| 1593 | { BITVAL_EOT } |
| 1594 | }}, |
| 1595 | { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, { |
| 1596 | { MSR1(0), "Disabled" }, |
| 1597 | { MSR1(1), "Enabled" }, |
| 1598 | { BITVAL_EOT } |
| 1599 | }}, |
| 1600 | { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, { |
| 1601 | { MSR1(0), "Disabled" }, |
| 1602 | { MSR1(1), "Enabled" }, |
| 1603 | { BITVAL_EOT } |
| 1604 | }}, |
| 1605 | { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, { |
| 1606 | { MSR1(0), "Disabled" }, |
| 1607 | { MSR1(1), "Enabled" }, |
| 1608 | { BITVAL_EOT } |
| 1609 | }}, |
| 1610 | { BITS_EOT } |
| 1611 | }}, |
| 1612 | {0x3f6, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_LD_LAT", "", { |
| 1613 | /* See Section 18.6.1.2 of Intel's manual |
| 1614 | * for additional information. |
| 1615 | */ |
| 1616 | { 63, 28, RESERVED }, |
| 1617 | { 35, 20, RESERVED }, |
| 1618 | { 15, 16, "Minimum threshold latency value of tagged \ |
| 1619 | load operation that will be counted", "R/W", PRESENT_DEC, { |
| 1620 | { BITVAL_EOT } |
| 1621 | }}, |
| 1622 | { BITS_EOT } |
| 1623 | }}, |
| 1624 | {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", { |
| 1625 | { BITS_EOT } |
| 1626 | }}, |
| 1627 | {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", { |
| 1628 | { BITS_EOT } |
| 1629 | }}, |
| 1630 | {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", { |
| 1631 | { BITS_EOT } |
| 1632 | }}, |
| 1633 | {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { |
| 1634 | { BITS_EOT } |
| 1635 | }}, |
| 1636 | {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { |
| 1637 | { BITS_EOT } |
| 1638 | }}, |
| 1639 | {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { |
| 1640 | { BITS_EOT } |
| 1641 | }}, |
| 1642 | {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { |
| 1643 | { BITS_EOT } |
| 1644 | }}, |
| 1645 | {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { |
| 1646 | { BITS_EOT } |
| 1647 | }}, |
| 1648 | {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { |
| 1649 | { BITS_EOT } |
| 1650 | }}, |
| 1651 | {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { |
| 1652 | { BITS_EOT } |
| 1653 | }}, |
| 1654 | {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { |
| 1655 | { BITS_EOT } |
| 1656 | }}, |
| 1657 | {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { |
| 1658 | { BITS_EOT } |
| 1659 | }}, |
| 1660 | {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { |
| 1661 | { BITS_EOT } |
| 1662 | }}, |
| 1663 | {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { |
| 1664 | { BITS_EOT } |
| 1665 | }}, |
| 1666 | {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { |
| 1667 | { BITS_EOT } |
| 1668 | }}, |
| 1669 | {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { |
| 1670 | { BITS_EOT } |
| 1671 | }}, |
| 1672 | {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { |
| 1673 | { BITS_EOT } |
| 1674 | }}, |
| 1675 | {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { |
| 1676 | { BITS_EOT } |
| 1677 | }}, |
| 1678 | {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { |
| 1679 | { BITS_EOT } |
| 1680 | }}, |
| 1681 | {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { |
| 1682 | { BITS_EOT } |
| 1683 | }}, |
| 1684 | {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { |
| 1685 | { BITS_EOT } |
| 1686 | }}, |
| 1687 | {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", { |
| 1688 | { BITS_EOT } |
| 1689 | }}, |
| 1690 | {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", { |
| 1691 | { BITS_EOT } |
| 1692 | }}, |
| 1693 | {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", { |
| 1694 | { BITS_EOT } |
| 1695 | }}, |
| 1696 | {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", |
| 1697 | "Reporting Register of Basic VMX Capabilities", { |
| 1698 | /* Additional info available at |
| 1699 | * Appendix A.1, "Basic VMX Information" */ |
| 1700 | { 63, 10, RESERVED }, |
| 1701 | { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, { |
| 1702 | { BITVAL_EOT } |
| 1703 | }}, |
| 1704 | { 49, 1, "Support of dual-treatment of system-management functions", |
| 1705 | "R/O", PRESENT_BIN, { |
| 1706 | { BITVAL_EOT } |
| 1707 | }}, |
| 1708 | { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, { |
| 1709 | { BITVAL_EOT } |
| 1710 | }}, |
| 1711 | { 47, 3, RESERVED }, |
| 1712 | { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, { |
| 1713 | { BITVAL_EOT } |
| 1714 | }}, |
| 1715 | { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, { |
| 1716 | { BITVAL_EOT } |
| 1717 | }}, |
| 1718 | { BITS_EOT } |
| 1719 | }}, |
| 1720 | {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", |
| 1721 | "Capability Reporting Register of \ |
| 1722 | Pin-based VM-execution Controls", { |
| 1723 | /* Additional info available at Appendix A.3, |
| 1724 | * "VM-Execution Controls" */ |
| 1725 | { BITS_EOT } |
| 1726 | }}, |
| 1727 | {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", |
| 1728 | "Capability Reporting Register of \ |
| 1729 | Primary Processor-based VM-execution Controls", { |
| 1730 | /* Additional info available at Appendix A.3, |
| 1731 | * "VM-Execution Controls" */ |
| 1732 | { BITS_EOT } |
| 1733 | }}, |
| 1734 | {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", |
| 1735 | "Capability Reporting Register of VM-exit Controls", { |
| 1736 | /* Additional info available at Appendix A.4, |
| 1737 | * "VM-Exit Controls" */ |
| 1738 | { BITS_EOT } |
| 1739 | }}, |
| 1740 | {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", |
| 1741 | "Capability Reporting Register of VM-entry Controls", { |
| 1742 | /* Additional info available at Appendix A.5, |
| 1743 | * "VM-Entry Controls" */ |
| 1744 | { BITS_EOT } |
| 1745 | }}, |
| 1746 | {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", |
| 1747 | "Reporting Register of Miscellaneous VMX Capabilities", { |
| 1748 | /* Additional info available at Appendix A.6, |
| 1749 | * "Miscellaneous Data" */ |
| 1750 | { BITS_EOT } |
| 1751 | }}, |
| 1752 | {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", |
| 1753 | "Capability Reporting Register of CR0 Bits Fixed to 0", { |
| 1754 | /* Additional info available at Appendix A.7, |
| 1755 | * "VMX-Fixed Bits in CR0" */ |
| 1756 | { BITS_EOT } |
| 1757 | }}, |
| 1758 | {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", |
| 1759 | "Capability Reporting Register of CR0 Bits Fixed to 1", { |
| 1760 | /* Additional info available at Appendix A.7, |
| 1761 | * "VMX-Fixed Bits in CR0" */ |
| 1762 | { BITS_EOT } |
| 1763 | }}, |
| 1764 | {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", |
| 1765 | "Capability Reporting Register of CR4 Bits Fixed to 0", { |
| 1766 | /* Additional info available at Appendix A.8, |
| 1767 | * "VMX-Fixed Bits in CR4" */ |
| 1768 | { BITS_EOT } |
| 1769 | }}, |
| 1770 | {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", |
| 1771 | "Capability Reporting Register of CR4 Bits Fixed to 1", { |
| 1772 | /* Additional info available at Appendix A.8, |
| 1773 | * "VMX-Fixed Bits in CR4" */ |
| 1774 | { BITS_EOT } |
| 1775 | }}, |
| 1776 | {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", |
| 1777 | "Capability Reporting Register of VMCS Field Enumeration", { |
| 1778 | /* Additional info available at Appendix A.9, |
| 1779 | * "VMCS Enumeration" */ |
| 1780 | { BITS_EOT } |
| 1781 | }}, |
| 1782 | {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", |
| 1783 | "Capability Reporting Register of Secondary \ |
| 1784 | Processor-based VM-execution Controls", { |
| 1785 | /* Additional info available at Appendix A.3, |
| 1786 | * "VM-Execution Controls" */ |
| 1787 | { BITS_EOT } |
| 1788 | }}, |
| 1789 | /* Undocumented PECI control register */ |
| 1790 | {0x5a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_PECI_CTL", |
| 1791 | "PECI Control Register", { |
| 1792 | { BITS_EOT } |
| 1793 | }}, |
| 1794 | {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { |
| 1795 | /* Additional info available at Section 18.10.4 of Intel 64 |
| 1796 | * and IA-32 Architectures Software Developer's Manual, |
| 1797 | * "Debug Store (DS) Mechanism". |
| 1798 | */ |
| 1799 | { 63, 32, RESERVED }, // reserved if not in IA-32e mode |
| 1800 | { 31, 32, "Linear address of DS buffer management area", |
| 1801 | "R/W", PRESENT_HEX, { |
| 1802 | { BITVAL_EOT } |
| 1803 | }}, |
| 1804 | { BITS_EOT } |
| 1805 | }}, |
| 1806 | |
| 1807 | /* 16 registers - first |
| 1808 | * registers in sixteen pairs |
| 1809 | * of last branch record registers |
| 1810 | * on the last branch record stack |
| 1811 | */ |
| 1812 | {0x680, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "R/W", { |
| 1813 | { BITS_EOT } |
| 1814 | }}, |
| 1815 | {0x681, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "R/W", { |
| 1816 | { BITS_EOT } |
| 1817 | }}, |
| 1818 | {0x682, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "R/W", { |
| 1819 | { BITS_EOT } |
| 1820 | }}, |
| 1821 | {0x683, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "R/W", { |
| 1822 | { BITS_EOT } |
| 1823 | }}, |
| 1824 | {0x684, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "R/W", { |
| 1825 | { BITS_EOT } |
| 1826 | }}, |
| 1827 | {0x685, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_FROM_IP", "R/W", { |
| 1828 | { BITS_EOT } |
| 1829 | }}, |
| 1830 | {0x686, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "R/W", { |
| 1831 | { BITS_EOT } |
| 1832 | }}, |
| 1833 | {0x687, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_FROM_IP", "R/W", { |
| 1834 | { BITS_EOT } |
| 1835 | }}, |
| 1836 | {0x688, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_FROM_IP", "R/W", { |
| 1837 | { BITS_EOT } |
| 1838 | }}, |
| 1839 | {0x689, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_9_FROM_IP", "R/W", { |
| 1840 | { BITS_EOT } |
| 1841 | }}, |
| 1842 | {0x68a, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_FROM_IP", "R/W", { |
| 1843 | { BITS_EOT } |
| 1844 | }}, |
| 1845 | {0x68b, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_11_FROM_IP", "R/W", { |
| 1846 | { BITS_EOT } |
| 1847 | }}, |
| 1848 | {0x68c, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_FROM_IP", "R/W", { |
| 1849 | { BITS_EOT } |
| 1850 | }}, |
| 1851 | {0x68d, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_13_FROM_IP", "R/W", { |
| 1852 | { BITS_EOT } |
| 1853 | }}, |
| 1854 | {0x68e, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_FROM_IP", "R/W", { |
| 1855 | { BITS_EOT } |
| 1856 | }}, |
| 1857 | {0x68f, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_15_FROM_IP", "R/W", { |
| 1858 | { BITS_EOT } |
| 1859 | }}, |
| 1860 | |
| 1861 | /* 16 registers - second |
| 1862 | * registers in sixteen pairs |
| 1863 | * of last branch record registers |
| 1864 | * on the last branch record stack |
| 1865 | */ |
| 1866 | {0x6c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "R/W", { |
| 1867 | { BITS_EOT } |
| 1868 | }}, |
| 1869 | {0x6c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "R/W", { |
| 1870 | { BITS_EOT } |
| 1871 | }}, |
| 1872 | {0x6c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "R/W", { |
| 1873 | { BITS_EOT } |
| 1874 | }}, |
| 1875 | {0x6c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "R/W", { |
| 1876 | { BITS_EOT } |
| 1877 | }}, |
| 1878 | {0x6c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_LIP", "R/W", { |
| 1879 | { BITS_EOT } |
| 1880 | }}, |
| 1881 | {0x6c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_TO_LIP", "R/W", { |
| 1882 | { BITS_EOT } |
| 1883 | }}, |
| 1884 | {0x6c6, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_LIP", "R/W", { |
| 1885 | { BITS_EOT } |
| 1886 | }}, |
| 1887 | {0x6c7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_TO_LIP", "R/W", { |
| 1888 | { BITS_EOT } |
| 1889 | }}, |
| 1890 | {0x6c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_TO_LIP", "R/W", { |
| 1891 | { BITS_EOT } |
| 1892 | }}, |
| 1893 | {0x6c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_9_TO_LIP", "R/W", { |
| 1894 | { BITS_EOT } |
| 1895 | }}, |
| 1896 | {0x6ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_TO_LIP", "R/W", { |
| 1897 | { BITS_EOT } |
| 1898 | }}, |
| 1899 | {0x6cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_11_TO_LIP", "R/W", { |
| 1900 | { BITS_EOT } |
| 1901 | }}, |
| 1902 | {0x6cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_TO_LIP", "R/W", { |
| 1903 | { BITS_EOT } |
| 1904 | }}, |
| 1905 | {0x6cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_13_TO_LIP", "R/W", { |
| 1906 | { BITS_EOT } |
| 1907 | }}, |
| 1908 | {0x6ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_TO_LIP", "R/W", { |
| 1909 | { BITS_EOT } |
| 1910 | }}, |
| 1911 | {0x6cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_15_TO_LIP", "R/W", { |
| 1912 | { BITS_EOT } |
| 1913 | }}, |
| 1914 | |
| 1915 | /* x2APIC registers - see Intel 64 Architecture x2APIC Specification */ |
| 1916 | |
| 1917 | {0x802, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_APICID", |
| 1918 | "x2APIC ID register", { |
| 1919 | { BITS_EOT } |
| 1920 | }}, |
| 1921 | {0x803, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_VERSION", |
| 1922 | /* Same version between extended and legacy modes. |
| 1923 | * Bit 24 is available only to an x2APIC unit. */ |
| 1924 | "x2APIC Version register", { |
| 1925 | { 31, 7, RESERVED }, |
| 1926 | { 24, 1, "Directed EOI Support", "R/W", PRESENT_BIN, { |
| 1927 | { BITVAL_EOT } |
| 1928 | }}, |
| 1929 | { 23, 8, "Max LVT Entry", "R/W", PRESENT_HEX, { |
| 1930 | { BITVAL_EOT } |
| 1931 | }}, |
| 1932 | { 15, 8, RESERVED }, |
| 1933 | { 7, 8, "Vector", "R/W", PRESENT_HEX, { |
| 1934 | { BITVAL_EOT } |
| 1935 | }}, |
| 1936 | { BITS_EOT } |
| 1937 | }}, |
| 1938 | {0x808, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_TPR", |
| 1939 | "x2APIC Task Priority register", { |
| 1940 | { 31, 24, RESERVED }, |
| 1941 | { 7, 8, "TPR", "R/W", PRESENT_HEX, { |
| 1942 | { BITVAL_EOT } |
| 1943 | }}, |
| 1944 | { BITS_EOT } |
| 1945 | }}, |
| 1946 | {0x80a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_PPR", |
| 1947 | "x2APIC Processor Priority register", { |
| 1948 | { BITS_EOT } |
| 1949 | }}, |
| 1950 | {0x80b, MSRTYPE_WRONLY, MSR2(0,0), "IA32_X2APIC_EOI", |
| 1951 | /* 0 is the only valid value to write. GP fault |
| 1952 | * on non-zero write. */ |
| 1953 | "x2APIC EOI register", { |
| 1954 | { BITS_EOT } |
| 1955 | }}, |
| 1956 | {0x80d, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_LDR", |
| 1957 | /* Read Only in x2APIC mode, Read-Write in xAPIC mode. */ |
| 1958 | "x2APIC Logical Destination register", { |
| 1959 | { BITS_EOT } |
| 1960 | }}, |
| 1961 | {0x80f, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_SIVR", |
| 1962 | "x2APIC Spurious Interrupt Vector register", { |
| 1963 | { 31, 19, RESERVED }, |
| 1964 | { 12, 1, "EOI Broadcast Disable", "R/W", PRESENT_BIN, { |
| 1965 | { BITVAL_EOT } |
| 1966 | }}, |
| 1967 | { 11, 3, RESERVED }, |
| 1968 | { 8, 1, "APIC Software Enable/Disable", "R/W", PRESENT_BIN, { |
| 1969 | { MSR1(0), "APIC Disabled" }, |
| 1970 | { MSR1(1), "APIC Enabled" }, |
| 1971 | { BITVAL_EOT } |
| 1972 | }}, |
| 1973 | { 7, 8, "Spurious Vector", "R/W", PRESENT_HEX, { |
| 1974 | { BITVAL_EOT } |
| 1975 | }}, |
| 1976 | { BITS_EOT } |
| 1977 | }}, |
| 1978 | {0x810, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_0", |
| 1979 | "x2APIC In-Service register bits [31:0]", { |
| 1980 | { BITS_EOT } |
| 1981 | }}, |
| 1982 | {0x811, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_1", |
| 1983 | "x2APIC In-Service register bits [63:32]", { |
| 1984 | { BITS_EOT } |
| 1985 | }}, |
| 1986 | {0x812, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_2", |
| 1987 | "x2APIC In-Service register bits [95:64]", { |
| 1988 | { BITS_EOT } |
| 1989 | }}, |
| 1990 | {0x813, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_3", |
| 1991 | "x2APIC In-Service register bits [127:96]", { |
| 1992 | { BITS_EOT } |
| 1993 | }}, |
| 1994 | {0x814, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_4", |
| 1995 | "x2APIC In-Service register bits [159:128]", { |
| 1996 | { BITS_EOT } |
| 1997 | }}, |
| 1998 | {0x815, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_5", |
| 1999 | "x2APIC In-Service register bits [191:160]", { |
| 2000 | { BITS_EOT } |
| 2001 | }}, |
| 2002 | {0x816, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_6", |
| 2003 | "x2APIC In-Service register bits [223:192]", { |
| 2004 | { BITS_EOT } |
| 2005 | }}, |
| 2006 | {0x817, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_7", |
| 2007 | "x2APIC In-Service register bits [255:224]", { |
| 2008 | { BITS_EOT } |
| 2009 | }}, |
| 2010 | {0x818, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR0", |
| 2011 | "x2APIC Trigger Mode register bits [31:0]", { |
| 2012 | { BITS_EOT } |
| 2013 | }}, |
| 2014 | {0x819, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR1", |
| 2015 | "x2APIC Trigger Mode register bits [63:32]", { |
| 2016 | { BITS_EOT } |
| 2017 | }}, |
| 2018 | {0x81a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR2", |
| 2019 | "x2APIC Trigger Mode register bits [95:64]", { |
| 2020 | { BITS_EOT } |
| 2021 | }}, |
| 2022 | {0x81b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR3", |
| 2023 | "x2APIC Trigger Mode register bits [127:96]", { |
| 2024 | { BITS_EOT } |
| 2025 | }}, |
| 2026 | {0x81c, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR4", |
| 2027 | "x2APIC Trigger Mode register bits [159:128]", { |
| 2028 | { BITS_EOT } |
| 2029 | }}, |
| 2030 | {0x81d, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR5", |
| 2031 | "x2APIC Trigger Mode register bits [191:160]", { |
| 2032 | { BITS_EOT } |
| 2033 | }}, |
| 2034 | {0x81e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR6", |
| 2035 | "x2APIC Trigger Mode register bits [223:192]", { |
| 2036 | { BITS_EOT } |
| 2037 | }}, |
| 2038 | {0x81f, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR7", |
| 2039 | "x2APIC Trigger Mode register bits [255:224]", { |
| 2040 | { BITS_EOT } |
| 2041 | }}, |
| 2042 | {0x820, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR0", |
| 2043 | "x2APIC Interrupt Request register bits [31:0]", { |
| 2044 | { BITS_EOT } |
| 2045 | }}, |
| 2046 | {0x821, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR1", |
| 2047 | "x2APIC Trigger Mode register bits [63:32]", { |
| 2048 | { BITS_EOT } |
| 2049 | }}, |
| 2050 | {0x822, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR2", |
| 2051 | "x2APIC Trigger Mode register bits [95:64]", { |
| 2052 | { BITS_EOT } |
| 2053 | }}, |
| 2054 | {0x823, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR3", |
| 2055 | "x2APIC Trigger Mode register bits [127:96]", { |
| 2056 | { BITS_EOT } |
| 2057 | }}, |
| 2058 | {0x824, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR4", |
| 2059 | "x2APIC Trigger Mode register bits [159:128]", { |
| 2060 | { BITS_EOT } |
| 2061 | }}, |
| 2062 | {0x825, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR5", |
| 2063 | "x2APIC Trigger Mode register bits [191:160]", { |
| 2064 | { BITS_EOT } |
| 2065 | }}, |
| 2066 | {0x826, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR6", |
| 2067 | "x2APIC Trigger Mode register bits [223:192]", { |
| 2068 | { BITS_EOT } |
| 2069 | }}, |
| 2070 | {0x827, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR7", |
| 2071 | "x2APIC Trigger Mode register bits [255:224]", { |
| 2072 | { BITS_EOT } |
| 2073 | }}, |
| 2074 | {0x828, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_ESR", |
| 2075 | /* GP fault on non-zero writes. */ |
| 2076 | "x2APIC Error Status register", { |
| 2077 | { 31, 24, RESERVED }, |
| 2078 | { 7, 1, "Illegal Register Address", "R/O", PRESENT_BIN, { |
| 2079 | { BITVAL_EOT } |
| 2080 | }}, |
| 2081 | { 6, 1, "Received Illegal Vector", "R/O", PRESENT_BIN, { |
| 2082 | { BITVAL_EOT } |
| 2083 | }}, |
| 2084 | { 5, 1, "Send Illegal Vector", "R/O", PRESENT_BIN, { |
| 2085 | { BITVAL_EOT } |
| 2086 | }}, |
| 2087 | { 4, 1, "Redirectible IPI", "R/O", PRESENT_BIN, { |
| 2088 | { BITVAL_EOT } |
| 2089 | }}, |
| 2090 | { 3, 4, RESERVED }, |
| 2091 | { BITS_EOT } |
| 2092 | }}, |
| 2093 | {0x82f, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_CMCI", |
| 2094 | "x2APIC LVT Corrected Machine Check Interrupt register", { |
| 2095 | { BITS_EOT } |
| 2096 | }}, |
| 2097 | {0x830, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_ICR", |
| 2098 | "x2APIC Interrupt Command register", { |
| 2099 | { 63, 32, "Destination field", "R/W", PRESENT_HEX, { |
| 2100 | { BITVAL_EOT } |
| 2101 | }}, |
| 2102 | { 31, 12, RESERVED }, |
| 2103 | { 19, 2, "Destination Shorthand", "R/W", PRESENT_BIN, { |
| 2104 | { MSR1(0), "No Shorthand" }, |
| 2105 | { MSR1(1), "Self" }, |
| 2106 | { MSR1(2), "All including Self" }, |
| 2107 | { MSR1(3), "All excluding Self" }, |
| 2108 | { BITVAL_EOT } |
| 2109 | }}, |
| 2110 | { 17, 2, RESERVED }, |
| 2111 | { 15, 1, "Trigger Mode", "R/W", PRESENT_BIN, { |
| 2112 | { MSR1(0), "Edge" }, |
| 2113 | { MSR1(1), "Level" }, |
| 2114 | { BITVAL_EOT } |
| 2115 | }}, |
| 2116 | { 14, 1, "Level", "R/W", PRESENT_BIN, { |
| 2117 | { MSR1(0), "De-assert" }, |
| 2118 | { MSR1(1), "Assert" }, |
| 2119 | { BITVAL_EOT } |
| 2120 | }}, |
| 2121 | { 13, 2, RESERVED }, |
| 2122 | { 11, 1, "Destination Mode", "R/W", PRESENT_BIN, { |
| 2123 | { MSR1(0), "Physical" }, |
| 2124 | { MSR1(1), "Logical" }, |
| 2125 | { BITVAL_EOT } |
| 2126 | }}, |
| 2127 | { 10, 3, "Delivery Mode", "R/W", PRESENT_BIN, { |
| 2128 | { MSR1(0), "Fixed" }, |
| 2129 | { MSR1(1), "Reserved" }, |
| 2130 | { MSR1(2), "SMI" }, |
| 2131 | { MSR1(3), "Reserved" }, |
| 2132 | { MSR1(4), "NMI" }, |
| 2133 | { MSR1(5), "INIT" }, |
| 2134 | { MSR1(6), "Start Up" }, |
| 2135 | { MSR1(7), "Reserved" }, |
| 2136 | { BITVAL_EOT } |
| 2137 | }}, |
| 2138 | { 7, 8, "Vector", "R/W", PRESENT_HEX, { |
| 2139 | { BITVAL_EOT } |
| 2140 | }}, |
| 2141 | { BITS_EOT } |
| 2142 | }}, |
| 2143 | {0x832, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_TIMER", |
| 2144 | "x2APIC LVT Timer Interrupt register", { |
| 2145 | { BITS_EOT } |
| 2146 | }}, |
| 2147 | {0x833, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_THERMAL", |
| 2148 | "x2APIC LVT Thermal Sensor Interrupt register", { |
| 2149 | { BITS_EOT } |
| 2150 | }}, |
| 2151 | {0x834, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_PMI", |
| 2152 | "x2APIC LVT Performance Monitor register", { |
| 2153 | { BITS_EOT } |
| 2154 | }}, |
| 2155 | {0x835, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_LINT0", |
| 2156 | "x2APIC LVT LINT0 register", { |
| 2157 | { BITS_EOT } |
| 2158 | }}, |
| 2159 | {0x836, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_LINT1", |
| 2160 | "x2APIC LVT LINT1 register", { |
| 2161 | { BITS_EOT } |
| 2162 | }}, |
| 2163 | {0x837, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_ERROR", |
| 2164 | "x2APIC LVT Error register", { |
| 2165 | { BITS_EOT } |
| 2166 | }}, |
| 2167 | {0x838, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_INIT_COUNT", |
| 2168 | "x2APIC Initial Count register", { |
| 2169 | { BITS_EOT } |
| 2170 | }}, |
| 2171 | {0x839, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_CUR_COUNT", |
| 2172 | "x2APIC Current Count register", { |
| 2173 | { BITS_EOT } |
| 2174 | }}, |
| 2175 | {0x83e, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_DIV_CONF", |
| 2176 | "x2APIC Divide Configuration register", { |
| 2177 | { BITS_EOT } |
| 2178 | }}, |
| 2179 | {0x83f, MSRTYPE_WRONLY, MSR2(0,0), "IA32_X2APIC_SELF_IPI", |
| 2180 | "x2APIC Self IPI register", { |
| 2181 | /* Only in x2APIC mode. */ |
| 2182 | { 31, 24, RESERVED }, |
| 2183 | { 7, 8, "Vector", "R/W", PRESENT_HEX, { |
| 2184 | { BITVAL_EOT } |
| 2185 | }}, |
| 2186 | { BITS_EOT } |
| 2187 | }}, |
| 2188 | {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", { |
| 2189 | { BITS_EOT } |
| 2190 | }}, |
| 2191 | {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", { |
| 2192 | { BITS_EOT } |
| 2193 | }}, |
| 2194 | {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", { |
| 2195 | { BITS_EOT } |
| 2196 | }}, |
| 2197 | {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", { |
| 2198 | { BITS_EOT } |
| 2199 | }}, |
| 2200 | {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", { |
| 2201 | { BITS_EOT } |
| 2202 | }}, |
| 2203 | {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", { |
| 2204 | { BITS_EOT } |
| 2205 | }}, |
| 2206 | {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", { |
| 2207 | { BITS_EOT } |
| 2208 | }}, |
| 2209 | {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", { |
| 2210 | { BITS_EOT } |
| 2211 | }}, |
| 2212 | {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", { |
| 2213 | { BITS_EOT } |
| 2214 | }}, |
| 2215 | /* if CPUID.80000001H: EDX[29] = 1 or CPUID.80000001H: EDX[27] = 1 */ |
| 2216 | {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", |
| 2217 | "Extended Feature Enables", { |
| 2218 | { 63, 52, RESERVED }, |
| 2219 | { 11, 1, "Execute Disable Bit", "R/O", PRESENT_BIN, { |
| 2220 | { MSR1(0), "NX bit disabled" }, |
| 2221 | { MSR1(1), "NX bit enabled" }, |
| 2222 | { BITVAL_EOT } |
| 2223 | }}, |
| 2224 | { 10, 1, "IA-32e Mode", "R/O", PRESENT_BIN, { |
| 2225 | { MSR1(0), "IA-32e Mode Inactive" }, |
| 2226 | { MSR1(1), "IA-32e Mode Active" }, |
| 2227 | { BITVAL_EOT } |
| 2228 | }}, |
| 2229 | { 9, 1, RESERVED }, |
| 2230 | { 8, 1, "IA-32e Mode Control", "R/W", PRESENT_BIN, { |
| 2231 | /* Enable IA-32e Mode operation */ |
| 2232 | { BITVAL_EOT } |
| 2233 | }}, |
| 2234 | { 7, 7, RESERVED }, |
| 2235 | { 0, 1, "SYSCALL Control", "R/W", PRESENT_BIN, { |
| 2236 | /* Enable SYSCALL/SYSRET instructions |
| 2237 | * in 64-bit mode. */ |
| 2238 | { BITVAL_EOT } |
| 2239 | }}, |
| 2240 | { BITS_EOT } |
| 2241 | }}, |
| 2242 | /* if CPUID.80000001H: EDX[29] = 1 */ |
| 2243 | {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", |
| 2244 | "System Call Target Address", { |
| 2245 | { BITS_EOT } |
| 2246 | }}, |
| 2247 | /* if CPUID.80000001H: EDX[29] = 1 */ |
| 2248 | {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", |
| 2249 | "IA32e Mode System Call Target Address", { |
| 2250 | { BITS_EOT } |
| 2251 | }}, |
| 2252 | /* if CPUID.80000001H: EDX[29] = 1 */ |
| 2253 | {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", |
| 2254 | "System Call Flag Mask", { |
| 2255 | { BITS_EOT } |
| 2256 | }}, |
| 2257 | /* if CPUID.80000001H: EDX[29] = 1 */ |
| 2258 | {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", |
| 2259 | "Map of BASE Address of FS", { |
| 2260 | { BITS_EOT } |
| 2261 | }}, |
| 2262 | /* if CPUID.80000001H: EDX[29] = 1 */ |
| 2263 | {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", |
| 2264 | "Map of BASE Address of GS", { |
| 2265 | { BITS_EOT } |
| 2266 | }}, |
| 2267 | /* if CPUID.80000001H: EDX[29] = 1 */ |
| 2268 | {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", |
| 2269 | "Swap Target of BASE Address of GS", { |
| 2270 | { BITS_EOT } |
| 2271 | }}, |
| 2272 | /* if CPUID.80000001H: EDX[27] = 1 */ |
| 2273 | {0xc0000103, MSRTYPE_RDWR, MSR2(0,0), "IA32_TSC_AUX", |
| 2274 | "AUXILIARY TSC Signature", { |
| 2275 | { BITS_EOT } |
| 2276 | }}, |
| 2277 | { MSR_EOT } |
| 2278 | }; |
| 2279 | |
| 2280 | |