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Ed Swierka9faea82008-03-16 23:36:00 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 Arastra, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00007 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
Ed Swierka9faea82008-03-16 23:36:00 +00009 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010017 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ed Swierka9faea82008-03-16 23:36:00 +000018 */
19
Stefan Reinauer6f57b512010-07-08 16:41:05 +000020#ifndef __I3100_H__
21#define __I3100_H__
22
Ed Swierka9faea82008-03-16 23:36:00 +000023#define IURBASE 0X14
24#define MCHCFG0 0X50
25#define MCHSCRB 0X52
26#define FDHC 0X58
27#define PAM 0X59
28#define DRB 0X60
29#define DRA 0X70
30#define DRT 0X78
31#define DRC 0X7C
32#define DRM 0X80
33#define DRORC 0X82
34#define ECCDIAG 0X84
35#define SDRC 0X88
36#define CKDIS 0X8C
37#define CKEDIS 0X8D
38#define DDRCSR 0X9A
39#define DEVPRES 0X9C
40#define DEVPRES_D0F0 (1 << 0)
41#define DEVPRES_D1F0 (1 << 1)
42#define DEVPRES_D2F0 (1 << 2)
43#define DEVPRES_D3F0 (1 << 3)
44#define DEVPRES_D4F0 (1 << 4)
45#define DEVPRES_D5F0 (1 << 5)
46#define DEVPRES_D6F0 (1 << 6)
47#define DEVPRES_D7F0 (1 << 7)
48#define ESMRC 0X9D
49#define SMRC 0X9E
50#define EXSMRC 0X9F
51#define DDR2ODTC 0XB0
52#define TOLM 0XC4
53#define REMAPBASE 0XC6
54#define REMAPLIMIT 0XC8
55#define REMAPOFFSET 0XCA
56#define TOM 0XCC
57#define EXPECBASE 0XCE
58#define DEVPRES1 0XF4
59#define DEVPRES1_D0F1 (1 << 5)
60#define DEVPRES1_D8F0 (1 << 1)
61#define MSCFG 0XF6
Thomas Jourdan1a692d82009-07-01 17:01:17 +000062
63/* DRC */
64#define DRC_NOECC_MODE (0 << 20)
65#define DRC_72BIT_ECC (1 << 20)
Stefan Reinauer6f57b512010-07-08 16:41:05 +000066
Patrick Georgic2bf26d2010-11-15 19:44:42 +000067#define RCBA 0xF0
68#define DEFAULT_RCBA 0xFEA00000
Stefan Reinauer6f57b512010-07-08 16:41:05 +000069
Stefan Reinauer6f57b512010-07-08 16:41:05 +000070int bios_reset_detected(void);
Stefan Reinauer6f57b512010-07-08 16:41:05 +000071
72#endif