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review.coreboot.org / coreboot / c5b87c8f895502b235e1619a23bd89dda955000e / . / src / mainboard / iwill / dk8_htx / mptable.c
blob: 14df3163e1956f3047c723429128b818a5def495 [file] [log] [blame]
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]1#include <console/console.h>
2#include <arch/smp/mpspec.h>
3#include <device/pci.h>
4#include <string.h>
5#include <stdint.h>
6#if CONFIG_LOGICAL_CPUS==1
Stefan Reinauer9a16e3e2010-03-29 14:45:36 +0000[diff] [blame]7#include <cpu/amd/multicore.h>
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]8#endif
9
10#include <cpu/amd/amdk8_sysconf.h>
11#include "mb_sysconf.h"
12
Stefan Reinauere9de1e22010-04-07 15:30:11 +0000[diff] [blame]13
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]14
Stefan Reinauer50776fa2010-03-17 04:40:15 +0000[diff] [blame]15static void *smp_write_config_table(void *v)
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]16{
17 static const char sig[4] = "PCMP";
Stefan Reinauerd6532112010-04-16 00:31:44 +0000[diff] [blame]18 static const char oem[8] = "COREBOOT";
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]19 static const char productid[12] = "DK8-HTX ";
20 struct mp_config_table *mc;
21
22 unsigned char bus_num;
23 int i, j;
24 struct mb_sysconf_t *m;
25
26 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
27 memset(mc, 0, sizeof(*mc));
28
29 memcpy(mc->mpc_signature, sig, sizeof(sig));
30 mc->mpc_length = sizeof(*mc); /* initially just the header */
31 mc->mpc_spec = 0x04;
32 mc->mpc_checksum = 0; /* not yet computed */
33 memcpy(mc->mpc_oem, oem, sizeof(oem));
34 memcpy(mc->mpc_productid, productid, sizeof(productid));
35 mc->mpc_oemptr = 0;
36 mc->mpc_oemsize = 0;
37 mc->mpc_entry_count = 0; /* No entries yet... */
38 mc->mpc_lapic = LAPIC_ADDR;
39 mc->mpe_length = 0;
40 mc->mpe_checksum = 0;
41 mc->reserved = 0;
42
43 smp_write_processors(mc);
44
45 get_bus_conf();
46
47 m = sysconf.mb;
48
49/*Bus: Bus ID Type*/
50 /* define bus and isa numbers */
51 for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
52 smp_write_bus(mc, bus_num, "PCI ");
53 }
54 smp_write_bus(mc, m->bus_isa, "ISA ");
55
56/*I/O APICs: APIC ID Version State Address*/
57 smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
58 {
59 device_t dev;
60 struct resource *res;
61 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
62 if (dev) {
63 res = find_resource(dev, PCI_BASE_ADDRESS_0);
64 if (res) {
65 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
66 }
67 }
68 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
69 if (dev) {
70 res = find_resource(dev, PCI_BASE_ADDRESS_0);
71 if (res) {
72 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
73 }
74 }
75
76 j = 0;
77
78 for(i=1; i< sysconf.hc_possible_num; i++) {
79 if(!(sysconf.pci1234[i] & 0x1) ) continue;
80
81 switch(sysconf.hcid[i]) {
82 case 1: // 8132
83 case 3: // 8131
84 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
85 if (dev) {
86 res = find_resource(dev, PCI_BASE_ADDRESS_0);
87 if (res) {
88 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
89 }
90 }
91 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
92 if (dev) {
93 res = find_resource(dev, PCI_BASE_ADDRESS_0);
94 if (res) {
95 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
96 }
97 }
98 break;
99 }
100 j++;
101 }
102
103 }
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]104
Patrick Georgic5b87c82010-05-20 15:28:19 +0000[diff] [blame^]105 mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
106
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]107//??? What
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
109
110// Onboard AMD USB
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
112
113// Onboard VGA
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
115
116//Slot 5 PCI 32
117 for(i=0;i<4;i++) {
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
119 }
120
121//Slot 6 PCI 32
122 for(i=0;i<4;i++) {
123 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
124 }
125//Slot 1: HTX
126
127//Slot 2 PCI-X 133/100/66
128 for(i=0;i<4;i++) {
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30
130 }
131
132//Slot 3 PCI-X 133/100/66
133 for(i=0;i<4;i++) {
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
135 }
136
137//Slot 4 PCI-X 133/100/66
138 for(i=0;i<4;i++) {
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]139 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]140 }
141
142//Onboard NICS
143 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27
144 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
145
Stefan Reinauer14e22772010-04-27 06:56:47 +0000[diff] [blame]146//Onboard SATA
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
148
149 j = 0;
150
151 for(i=1; i< sysconf.hc_possible_num; i++) {
152 if(!(sysconf.pci1234[i] & 0x1) ) continue;
153 int ii;
154 device_t dev;
155 struct resource *res;
156 switch(sysconf.hcid[i]) {
157 case 1:
158 case 3:
159 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
160 if (dev) {
161 res = find_resource(dev, PCI_BASE_ADDRESS_0);
162 if (res) {
163 //Slot 1 PCI-X 133/100/66
164 for(ii=0;ii<4;ii++) {
165 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
166 }
167 }
168 }
169
170 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
171 if (dev) {
172 res = find_resource(dev, PCI_BASE_ADDRESS_0);
173 if (res) {
174 //Slot 2 PCI-X 133/100/66
175 for(ii=0;ii<4;ii++) {
176 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
177 }
178 }
179 }
180
181 break;
182 case 2:
183
184 // Slot AGP
185 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
186 break;
187 }
188
189 j++;
190 }
191
192
193
194/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
195 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
196 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
197 /* There is no extension information... */
198
199 /* Compute the checksums */
200 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
201 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +0000[diff] [blame]202 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame]203 mc, smp_next_mpe_entry(mc));
204 return smp_next_mpe_entry(mc);
205}
206
207unsigned long write_smp_table(unsigned long addr)
208{
209 void *v;
210 v = smp_write_floating_table(addr);
211 return (unsigned long)smp_write_config_table(v);
212}