| Dave Frodin | c43bce5 | 2014-12-03 08:22:46 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/pci.h> |
| 22 | #include <string.h> |
| 23 | #include <stdint.h> |
| 24 | #include <arch/pirq_routing.h> |
| 25 | #include <cpu/amd/amdfam16.h> |
| 26 | |
| 27 | static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, |
| 28 | u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, |
| 29 | u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, |
| 30 | u8 slot, u8 rfu) |
| 31 | { |
| 32 | pirq_info->bus = bus; |
| 33 | pirq_info->devfn = devfn; |
| 34 | pirq_info->irq[0].link = link0; |
| 35 | pirq_info->irq[0].bitmap = bitmap0; |
| 36 | pirq_info->irq[1].link = link1; |
| 37 | pirq_info->irq[1].bitmap = bitmap1; |
| 38 | pirq_info->irq[2].link = link2; |
| 39 | pirq_info->irq[2].bitmap = bitmap2; |
| 40 | pirq_info->irq[3].link = link3; |
| 41 | pirq_info->irq[3].bitmap = bitmap3; |
| 42 | pirq_info->slot = slot; |
| 43 | pirq_info->rfu = rfu; |
| 44 | } |
| 45 | |
| 46 | |
| 47 | unsigned long write_pirq_routing_table(unsigned long addr) |
| 48 | { |
| 49 | struct irq_routing_table *pirq; |
| 50 | struct irq_info *pirq_info; |
| 51 | u32 slot_num; |
| 52 | u8 *v; |
| 53 | |
| 54 | u8 sum = 0; |
| 55 | int i; |
| 56 | |
| 57 | /* Align the table to be 16 byte aligned. */ |
| 58 | addr += 15; |
| 59 | addr &= ~15; |
| 60 | |
| 61 | /* This table must be between 0xf0000 & 0x100000 */ |
| 62 | printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); |
| 63 | |
| 64 | pirq = (void *)(addr); |
| 65 | v = (u8 *) (addr); |
| 66 | |
| 67 | pirq->signature = PIRQ_SIGNATURE; |
| 68 | pirq->version = PIRQ_VERSION; |
| 69 | |
| 70 | pirq->rtr_bus = 0; |
| 71 | pirq->rtr_devfn = PCI_DEVFN(0x14, 4); |
| 72 | |
| 73 | pirq->exclusive_irqs = 0; |
| 74 | |
| 75 | pirq->rtr_vendor = 0x1002; |
| 76 | pirq->rtr_device = 0x4384; |
| 77 | |
| 78 | pirq->miniport_data = 0; |
| 79 | |
| 80 | memset(pirq->rfu, 0, sizeof(pirq->rfu)); |
| 81 | |
| 82 | pirq_info = (void *)(&pirq->checksum + 1); |
| 83 | slot_num = 0; |
| 84 | |
| 85 | /* pci bridge */ |
| 86 | write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), |
| 87 | 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, |
| 88 | 0); |
| 89 | pirq_info++; |
| 90 | |
| 91 | slot_num++; |
| 92 | |
| 93 | pirq->size = 32 + 16 * slot_num; |
| 94 | |
| 95 | for (i = 0; i < pirq->size; i++) |
| 96 | sum += v[i]; |
| 97 | |
| 98 | sum = pirq->checksum - sum; |
| 99 | |
| 100 | if (sum != pirq->checksum) { |
| 101 | pirq->checksum = sum; |
| 102 | } |
| 103 | |
| 104 | printk(BIOS_INFO, "write_pirq_routing_table done.\n"); |
| 105 | |
| 106 | return (unsigned long)pirq_info; |
| 107 | } |