Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Damien Roth | bedbd67 | 2016-01-18 13:59:26 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 2446c1e | 2020-07-09 07:13:37 +0300 | [diff] [blame] | 3 | #include <amdblocks/biosram.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
Tobias Diedrich | c292467 | 2010-11-09 22:31:11 +0000 | [diff] [blame] | 6 | #include <arch/cpu.h> |
Arthur Heymans | 7e27202 | 2021-10-28 10:13:39 +0200 | [diff] [blame] | 7 | #include <cpu/cpu.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 8 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | 190011e | 2013-03-25 12:48:49 +0200 | [diff] [blame] | 9 | #include <cpu/x86/msr.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 10 | #include <cpu/amd/mtrr.h> |
| 11 | #include <cpu/x86/cache.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 12 | |
Kyösti Mälkki | dbc4739 | 2012-08-05 12:11:40 +0300 | [diff] [blame] | 13 | /* These will likely move to some device node or cbmem. */ |
| 14 | static uint64_t amd_topmem = 0; |
| 15 | static uint64_t amd_topmem2 = 0; |
| 16 | |
| 17 | uint64_t bsp_topmem(void) |
| 18 | { |
| 19 | return amd_topmem; |
| 20 | } |
| 21 | |
| 22 | uint64_t bsp_topmem2(void) |
| 23 | { |
| 24 | return amd_topmem2; |
| 25 | } |
| 26 | |
| 27 | /* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, |
| 28 | * so they can be distributed to AP CPUs. Not strictly MTRRs, |
| 29 | * but this is not that bad a place to have this code. |
| 30 | */ |
| 31 | void setup_bsp_ramtop(void) |
| 32 | { |
| 33 | msr_t msr, msr2; |
| 34 | |
| 35 | /* TOP_MEM: the top of DRAM below 4G */ |
| 36 | msr = rdmsr(TOP_MEM); |
| 37 | printk(BIOS_INFO, |
| 38 | "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 39 | __func__, msr.lo, msr.hi); |
| 40 | |
| 41 | /* TOP_MEM2: the top of DRAM above 4G */ |
| 42 | msr2 = rdmsr(TOP_MEM2); |
| 43 | printk(BIOS_INFO, |
| 44 | "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 45 | __func__, msr2.lo, msr2.hi); |
| 46 | |
Elyes HAOUAS | 168ef39 | 2017-06-27 22:54:42 +0200 | [diff] [blame] | 47 | amd_topmem = (uint64_t) msr.hi << 32 | msr.lo; |
| 48 | amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo; |
Kyösti Mälkki | dbc4739 | 2012-08-05 12:11:40 +0300 | [diff] [blame] | 49 | } |
| 50 | |
Kyösti Mälkki | 17bb225 | 2017-04-19 19:55:54 +0300 | [diff] [blame] | 51 | void add_uma_resource_below_tolm(struct device *nb, int idx) |
| 52 | { |
| 53 | uint32_t topmem = bsp_topmem(); |
Kyösti Mälkki | 70d92b9 | 2017-04-19 19:57:01 +0300 | [diff] [blame] | 54 | uint32_t top_of_cacheable = restore_top_of_low_cacheable(); |
Kyösti Mälkki | 17bb225 | 2017-04-19 19:55:54 +0300 | [diff] [blame] | 55 | |
| 56 | if (top_of_cacheable == topmem) |
| 57 | return; |
| 58 | |
| 59 | uint32_t uma_base = top_of_cacheable; |
| 60 | uint32_t uma_size = topmem - top_of_cacheable; |
| 61 | |
| 62 | printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", |
| 63 | __func__, uma_size, uma_base); |
| 64 | |
| 65 | uma_resource(nb, idx, uma_base / KiB, uma_size / KiB); |
| 66 | } |