blob: 885bc0fbb1ebe763b6d2c6ddfd3c65952272b409 [file] [log] [blame]
Aaron Durbin15921692013-11-12 16:44:18 -06001/*
2 * This file is part of the coreboot project.
3 *
Aaron Durbin15921692013-11-12 16:44:18 -06004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
Aaron Durbin15921692013-11-12 16:44:18 -060013 */
14
15#include <stdint.h>
Aaron Durbin15921692013-11-12 16:44:18 -060016#include <console/console.h>
17#include <device/device.h>
18#include <device/pci.h>
19#include <device/pci_ids.h>
20#include <reg_script.h>
21
Julius Werner18ea2d32014-10-07 16:42:17 -070022#include <soc/iosf.h>
23#include <soc/nvs.h>
24#include <soc/pci_devs.h>
25#include <soc/ramstage.h>
Duncan Laurie430bf0d2013-12-10 14:37:42 -080026#include "chip.h"
Aaron Durbin15921692013-11-12 16:44:18 -060027
28static const struct reg_script emmc_ops[] = {
29 /* Enable 2ms card stable feature. */
30 REG_PCI_OR32(0xa8, (1 << 24)),
31 /* Enable HS200 */
32 REG_PCI_WRITE32(0xa0, 0x446cc801),
33 REG_PCI_WRITE32(0xa4, 0x80000807),
34 /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */
35 REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)),
36 /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */
37 REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)),
38 /* Set slew for HS200 */
39 REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c),
40 REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c),
41 /* Max timeout */
42 REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e),
43 REG_SCRIPT_END,
44};
45
Elyes HAOUAS17a3ceb2018-05-22 10:42:28 +020046static void emmc_init(struct device *dev)
Aaron Durbin15921692013-11-12 16:44:18 -060047{
Kyösti Mälkki8950cfb2019-07-13 22:16:25 +030048 struct soc_intel_baytrail_config *config = config_of(dev);
Duncan Laurie430bf0d2013-12-10 14:37:42 -080049
Aaron Durbin616f3942013-12-10 17:12:44 -080050 printk(BIOS_DEBUG, "eMMC init\n");
51 reg_script_run_on_dev(dev, emmc_ops);
Duncan Lauriec29d6b82013-12-12 16:55:36 -080052
53 if (config->scc_acpi_mode)
54 scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC);
Aaron Durbin15921692013-11-12 16:44:18 -060055}
56
57static struct device_operations device_ops = {
58 .read_resources = pci_dev_read_resources,
59 .set_resources = pci_dev_set_resources,
60 .enable_resources = pci_dev_enable_resources,
61 .init = emmc_init,
Aaron Durbin15921692013-11-12 16:44:18 -060062 .ops_pci = &soc_pci_ops,
63};
64
65static const struct pci_driver southcluster __pci_driver = {
66 .ops = &device_ops,
67 .vendor = PCI_VENDOR_ID_INTEL,
68 .device = MMC_DEVID,
69};