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review.coreboot.org / coreboot / c34e3ab71e79dc1acf5effcba2830241b2ff7f7e / . / src / mainboard / Iwill / dk8_htx / mptable.c
blob: c191580efe672384e5509369bf27cc79bed28c79 [file] [log] [blame]
Yinghai Luc34e3ab2006-10-12 00:58:20 +0000[diff] [blame^]1#include <console/console.h>
2#include <arch/smp/mpspec.h>
3#include <device/pci.h>
4#include <string.h>
5#include <stdint.h>
6#if CONFIG_LOGICAL_CPUS==1
7#include <cpu/amd/dualcore.h>
8#endif
9
10#include <cpu/amd/amdk8_sysconf.h>
11#include "mb_sysconf.h"
12
13extern void get_bus_conf(void);
14
15void *smp_write_config_table(void *v)
16{
17 static const char sig[4] = "PCMP";
18 static const char oem[8] = "IWILL ";
19 static const char productid[12] = "DK8-HTX ";
20 struct mp_config_table *mc;
21
22 unsigned char bus_num;
23 int i, j;
24 struct mb_sysconf_t *m;
25
26 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
27 memset(mc, 0, sizeof(*mc));
28
29 memcpy(mc->mpc_signature, sig, sizeof(sig));
30 mc->mpc_length = sizeof(*mc); /* initially just the header */
31 mc->mpc_spec = 0x04;
32 mc->mpc_checksum = 0; /* not yet computed */
33 memcpy(mc->mpc_oem, oem, sizeof(oem));
34 memcpy(mc->mpc_productid, productid, sizeof(productid));
35 mc->mpc_oemptr = 0;
36 mc->mpc_oemsize = 0;
37 mc->mpc_entry_count = 0; /* No entries yet... */
38 mc->mpc_lapic = LAPIC_ADDR;
39 mc->mpe_length = 0;
40 mc->mpe_checksum = 0;
41 mc->reserved = 0;
42
43 smp_write_processors(mc);
44
45 get_bus_conf();
46
47 m = sysconf.mb;
48
49/*Bus: Bus ID Type*/
50 /* define bus and isa numbers */
51 for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
52 smp_write_bus(mc, bus_num, "PCI ");
53 }
54 smp_write_bus(mc, m->bus_isa, "ISA ");
55
56/*I/O APICs: APIC ID Version State Address*/
57 smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
58 {
59 device_t dev;
60 struct resource *res;
61 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
62 if (dev) {
63 res = find_resource(dev, PCI_BASE_ADDRESS_0);
64 if (res) {
65 smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
66 }
67 }
68 dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
69 if (dev) {
70 res = find_resource(dev, PCI_BASE_ADDRESS_0);
71 if (res) {
72 smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
73 }
74 }
75
76 j = 0;
77
78 for(i=1; i< sysconf.hc_possible_num; i++) {
79 if(!(sysconf.pci1234[i] & 0x1) ) continue;
80
81 switch(sysconf.hcid[i]) {
82 case 1: // 8132
83 case 3: // 8131
84 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
85 if (dev) {
86 res = find_resource(dev, PCI_BASE_ADDRESS_0);
87 if (res) {
88 smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
89 }
90 }
91 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
92 if (dev) {
93 res = find_resource(dev, PCI_BASE_ADDRESS_0);
94 if (res) {
95 smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
96 }
97 }
98 break;
99 }
100 j++;
101 }
102
103 }
104
105/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
106 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0);
107 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1);
108 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2);
109 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_8111, 0x3);
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_8111, 0x4);
111 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x5, m->apicid_8111, 0x5);
112 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_8111, 0x6);
113 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_8111, 0x7);
114 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_8111, 0x8);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x9, m->apicid_8111, 0x9);
116 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_8111, 0xc);
117 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_8111, 0xd);
118 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_8111, 0xe);
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_8111, 0xf);
120//??? What
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
122
123// Onboard AMD USB
124 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
125
126// Onboard VGA
127 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
128
129//Slot 5 PCI 32
130 for(i=0;i<4;i++) {
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
132 }
133
134//Slot 6 PCI 32
135 for(i=0;i<4;i++) {
136 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
137 }
138//Slot 1: HTX
139
140//Slot 2 PCI-X 133/100/66
141 for(i=0;i<4;i++) {
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30
143 }
144
145//Slot 3 PCI-X 133/100/66
146 for(i=0;i<4;i++) {
147 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
148 }
149
150//Slot 4 PCI-X 133/100/66
151 for(i=0;i<4;i++) {
152 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26
153 }
154
155//Onboard NICS
156 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27
157 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
158
159//Onboard SATA
160 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
161
162 j = 0;
163
164 for(i=1; i< sysconf.hc_possible_num; i++) {
165 if(!(sysconf.pci1234[i] & 0x1) ) continue;
166 int ii;
167 device_t dev;
168 struct resource *res;
169 switch(sysconf.hcid[i]) {
170 case 1:
171 case 3:
172 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
173 if (dev) {
174 res = find_resource(dev, PCI_BASE_ADDRESS_0);
175 if (res) {
176 //Slot 1 PCI-X 133/100/66
177 for(ii=0;ii<4;ii++) {
178 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
179 }
180 }
181 }
182
183 dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
184 if (dev) {
185 res = find_resource(dev, PCI_BASE_ADDRESS_0);
186 if (res) {
187 //Slot 2 PCI-X 133/100/66
188 for(ii=0;ii<4;ii++) {
189 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
190 }
191 }
192 }
193
194 break;
195 case 2:
196
197 // Slot AGP
198 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
199 break;
200 }
201
202 j++;
203 }
204
205
206
207/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
208 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
209 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
210 /* There is no extension information... */
211
212 /* Compute the checksums */
213 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
214 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
215 printk_debug("Wrote the mp table end at: %p - %p\n",
216 mc, smp_next_mpe_entry(mc));
217 return smp_next_mpe_entry(mc);
218}
219
220unsigned long write_smp_table(unsigned long addr)
221{
222 void *v;
223 v = smp_write_floating_table(addr);
224 return (unsigned long)smp_write_config_table(v);
225}