Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
Lijian Zhao | c3e75b4 | 2019-01-15 17:37:50 -0800 | [diff] [blame] | 6 | * Copyright (C) 2017-2019 Intel Corporation. |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 18 | #include <bootstate.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 19 | #include <chip.h> |
| 20 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 21 | #include <device/mmio.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 22 | #include <device/device.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 24 | #include <intelblocks/pmc.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 25 | #include <intelblocks/pmclib.h> |
| 26 | #include <intelblocks/rtc.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
| 28 | #include <soc/pm.h> |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 29 | |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 30 | /* |
| 31 | * Set which power state system will be after reapplying |
| 32 | * the power (from G3 State) |
| 33 | */ |
Duncan Laurie | 26bc328 | 2019-01-23 14:58:23 -0800 | [diff] [blame] | 34 | void pmc_set_afterg3(struct device *dev, int s5pwr) |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 35 | { |
| 36 | uint8_t reg8; |
Lijian Zhao | c3e75b4 | 2019-01-15 17:37:50 -0800 | [diff] [blame] | 37 | uint8_t *pmcbase = pmc_mmio_regs(); |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 38 | |
Lijian Zhao | c3e75b4 | 2019-01-15 17:37:50 -0800 | [diff] [blame] | 39 | reg8 = read8(pmcbase + GEN_PMCON_A); |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 40 | |
| 41 | switch (s5pwr) { |
| 42 | case MAINBOARD_POWER_STATE_OFF: |
| 43 | reg8 |= 1; |
| 44 | break; |
| 45 | case MAINBOARD_POWER_STATE_ON: |
| 46 | reg8 &= ~1; |
| 47 | break; |
| 48 | case MAINBOARD_POWER_STATE_PREVIOUS: |
| 49 | default: |
| 50 | break; |
| 51 | } |
| 52 | |
Lijian Zhao | c3e75b4 | 2019-01-15 17:37:50 -0800 | [diff] [blame] | 53 | write8(pmcbase + GEN_PMCON_A, reg8); |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 54 | } |
| 55 | |
| 56 | /* |
| 57 | * Set PMC register to know which state system should be after |
| 58 | * power reapplied |
| 59 | */ |
| 60 | void pmc_soc_restore_power_failure(void) |
| 61 | { |
Nico Huber | a70ed00 | 2018-11-17 23:43:24 +0100 | [diff] [blame] | 62 | pmc_set_afterg3(PCH_DEV_PMC, CONFIG_MAINBOARD_POWER_FAILURE_STATE); |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 63 | } |
| 64 | |
Krzysztof Sywula | 42a66fb | 2019-03-13 16:48:56 -0700 | [diff] [blame] | 65 | static void pm1_enable_pwrbtn_smi(void *unused) |
| 66 | { |
| 67 | /* |
| 68 | * Enable power button SMI only before jumping to payload. This ensures |
| 69 | * that: |
| 70 | * 1. Power button SMI is enabled only after coreboot is done. |
| 71 | * 2. On resume path, power button SMI is not enabled and thus avoids |
| 72 | * any shutdowns because of power button presses due to power button |
| 73 | * press in resume path. |
| 74 | */ |
| 75 | pmc_update_pm1_enable(PWRBTN_EN); |
| 76 | } |
| 77 | |
| 78 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); |
| 79 | |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 80 | static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) |
| 81 | { |
| 82 | uint32_t reg; |
| 83 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 84 | |
| 85 | printk(BIOS_DEBUG, "%sabling Deep S%c\n", |
| 86 | enable ? "En" : "Dis", sx + '0'); |
| 87 | reg = read32(pmcbase + offset); |
| 88 | if (enable) |
| 89 | reg |= mask; |
| 90 | else |
| 91 | reg &= ~mask; |
| 92 | write32(pmcbase + offset, reg); |
| 93 | } |
| 94 | |
| 95 | static void config_deep_s5(int on_ac, int on_dc) |
| 96 | { |
| 97 | /* Treat S4 the same as S5. */ |
| 98 | config_deep_sX(S4_PWRGATE_POL, S4AC_GATE_SUS, 4, on_ac); |
| 99 | config_deep_sX(S4_PWRGATE_POL, S4DC_GATE_SUS, 4, on_dc); |
| 100 | config_deep_sX(S5_PWRGATE_POL, S5AC_GATE_SUS, 5, on_ac); |
| 101 | config_deep_sX(S5_PWRGATE_POL, S5DC_GATE_SUS, 5, on_dc); |
| 102 | } |
| 103 | |
| 104 | static void config_deep_s3(int on_ac, int on_dc) |
| 105 | { |
| 106 | config_deep_sX(S3_PWRGATE_POL, S3AC_GATE_SUS, 3, on_ac); |
| 107 | config_deep_sX(S3_PWRGATE_POL, S3DC_GATE_SUS, 3, on_dc); |
| 108 | } |
| 109 | |
| 110 | static void config_deep_sx(uint32_t deepsx_config) |
| 111 | { |
| 112 | uint32_t reg; |
| 113 | uint8_t *pmcbase = pmc_mmio_regs(); |
| 114 | |
| 115 | reg = read32(pmcbase + DSX_CFG); |
| 116 | reg &= ~DSX_CFG_MASK; |
| 117 | reg |= deepsx_config; |
| 118 | write32(pmcbase + DSX_CFG, reg); |
| 119 | } |
| 120 | |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 121 | static void pch_power_options(struct device *dev) |
| 122 | { |
| 123 | const char *state; |
| 124 | |
Nico Huber | a70ed00 | 2018-11-17 23:43:24 +0100 | [diff] [blame] | 125 | const int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 126 | |
| 127 | /* |
| 128 | * Which state do we want to goto after g3 (power restored)? |
| 129 | * 0 == S5 Soft Off |
| 130 | * 1 == S0 Full On |
| 131 | * 2 == Keep Previous State |
| 132 | */ |
| 133 | switch (pwr_on) { |
| 134 | case MAINBOARD_POWER_STATE_OFF: |
| 135 | state = "off"; |
| 136 | break; |
| 137 | case MAINBOARD_POWER_STATE_ON: |
| 138 | state = "on"; |
| 139 | break; |
| 140 | case MAINBOARD_POWER_STATE_PREVIOUS: |
| 141 | state = "state keep"; |
| 142 | break; |
| 143 | default: |
| 144 | state = "undefined"; |
| 145 | } |
| 146 | pmc_set_afterg3(dev, pwr_on); |
| 147 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
| 148 | |
| 149 | /* Set up GPE configuration. */ |
| 150 | pmc_gpe_init(); |
| 151 | } |
| 152 | |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 153 | static void pmc_init(void *unused) |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 154 | { |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 155 | struct device *dev = PCH_DEV_PMC; |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 156 | config_t *config = dev->chip_info; |
| 157 | |
| 158 | rtc_init(); |
| 159 | |
| 160 | /* Initialize power management */ |
Subrata Banik | 33cd28e | 2017-12-19 12:33:59 +0530 | [diff] [blame] | 161 | pch_power_options(dev); |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 162 | |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 163 | config_deep_s3(config->deep_s3_enable_ac, config->deep_s3_enable_dc); |
| 164 | config_deep_s5(config->deep_s5_enable_ac, config->deep_s5_enable_dc); |
| 165 | config_deep_sx(config->deep_sx_config); |
| 166 | } |
| 167 | |
Subrata Banik | 0baad61 | 2017-11-23 13:58:34 +0530 | [diff] [blame] | 168 | /* |
| 169 | * Initialize PMC controller. |
| 170 | * |
| 171 | * PMC controller gets hidden from PCI bus during FSP-Silicon init call. |
| 172 | * Hence PCI enumeration can't be used to initialize bus device and |
| 173 | * allocate resources. |
| 174 | */ |
| 175 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL); |
Furquan Shaikh | ac8c60e | 2019-02-25 16:01:25 -0800 | [diff] [blame] | 176 | |
Furquan Shaikh | 67a489f | 2019-02-27 00:59:06 -0800 | [diff] [blame] | 177 | static void soc_acpi_mode_init(void *unused) |
Furquan Shaikh | ac8c60e | 2019-02-25 16:01:25 -0800 | [diff] [blame] | 178 | { |
| 179 | /* |
| 180 | * PMC initialization happens earlier for this SoC because FSP-Silicon |
| 181 | * init hides PMC from PCI bus. However, pmc_set_acpi_mode, which |
| 182 | * disables ACPI mode doesn't need to happen that early and can be |
Furquan Shaikh | 67a489f | 2019-02-27 00:59:06 -0800 | [diff] [blame] | 183 | * delayed till typical BS_DEV_INIT. This ensures that ACPI mode |
| 184 | * disabling happens the same way for all SoCs and hence the ordering of |
| 185 | * events is the same. |
Furquan Shaikh | ac8c60e | 2019-02-25 16:01:25 -0800 | [diff] [blame] | 186 | * |
| 187 | * This is important to ensure that the ordering does not break the |
| 188 | * assumptions of any other drivers (e.g. ChromeEC) which could be |
| 189 | * taking different actions based on disabling of ACPI (e.g. flushing of |
| 190 | * all EC hostevent bits). |
Furquan Shaikh | 67a489f | 2019-02-27 00:59:06 -0800 | [diff] [blame] | 191 | * |
| 192 | * P.S.: This cannot be done as part of pmc_soc_init as PMC device is |
| 193 | * hidden and hence the PMC driver never gets enumerated and so init is |
| 194 | * not called for it. |
Furquan Shaikh | ac8c60e | 2019-02-25 16:01:25 -0800 | [diff] [blame] | 195 | */ |
| 196 | pmc_set_acpi_mode(); |
| 197 | } |
Furquan Shaikh | 67a489f | 2019-02-27 00:59:06 -0800 | [diff] [blame] | 198 | |
| 199 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_acpi_mode_init, NULL); |