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Mono9b908242014-03-02 18:40:36 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
9 * the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Mono9b908242014-03-02 18:40:36 +010015 */
16
17#include <device/device.h>
18#include <device/pci.h>
Mono9b908242014-03-02 18:40:36 +010019#include <arch/smp/mpspec.h>
20#include <arch/ioapic.h>
Mono9b908242014-03-02 18:40:36 +010021#include <stdint.h>
22
23static void *smp_write_config_table(void *v)
24{
Elyes HAOUAS8da96e52016-09-22 21:20:54 +020025 struct mp_config_table *mc;
Mono9b908242014-03-02 18:40:36 +010026 int isa_bus;
27
Elyes HAOUAS8da96e52016-09-22 21:20:54 +020028 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
Mono9b908242014-03-02 18:40:36 +010029
30 mptable_init(mc, LOCAL_APIC_ADDR);
31
Elyes HAOUAS8da96e52016-09-22 21:20:54 +020032 smp_write_processors(mc);
Mono9b908242014-03-02 18:40:36 +010033
34 mptable_write_buses(mc, NULL, &isa_bus);
35
36 /* I/O APICs: APIC ID Version State Address */
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080037 smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
Mono9b908242014-03-02 18:40:36 +010038
39 /* Legacy Interrupts */
40 mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
41
42 smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00);
43 smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01);
Kyösti Mälkkic32a92e2019-01-04 06:02:22 +020044 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x01, 0x00, 0x02, 0x10); /* PCIe root 0.01.0 */
45 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x02, 0x00, 0x02, 0x10); /* VGA 0.02.0 */
46 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1b, 0x00, 0x02, 0x16); /* HD Audio 0:1b.0 */
47 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x00, 0x02, 0x11); /* PCIe 0:1c.0 */
48 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x01, 0x02, 0x10); /* PCIe 0:1c.1 */
49 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x02, 0x02, 0x12); /* PCIe 0:1c.2 */
50 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1c, 0x03, 0x02, 0x13); /* PCIe 0:1c.3 */
51 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x00, 0x02, 0x15); /* USB 0:1d.0 */
52 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x01, 0x02, 0x13); /* USB 0:1d.1 */
53 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x02, 0x02, 0x12); /* USB 0:1d.2 */
54 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1d, 0x03, 0x02, 0x10); /* USB 0:1d.3 */
55 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x00, 0x02, 0x12); /* LPC 0:1f.0 */
56 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x01, 0x02, 0x13); /* IDE 0:1f.1 */
57 smp_write_pci_intsrc(mc, mp_INT, 0x00, 0x1f, 0x03, 0x02, 0x10); /* SATA 0:1f.3 */
58 smp_write_pci_intsrc(mc, mp_INT, 0x03, 0x03, 0x00, 0x02, 0x13); /* Firewire 3:03.0 */
Mono9b908242014-03-02 18:40:36 +010059
60 mptable_lintsrc(mc, isa_bus);
61 return mptable_finalize(mc);
62}
63
64unsigned long write_smp_table(unsigned long addr)
65{
66 void *v;
67 v = smp_write_floating_table(addr, 0);
68 return (unsigned long)smp_write_config_table(v);
69}