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review.coreboot.org / coreboot / c2418552407fee39965ecd6dbad52cb39c76b656 / . / src / southbridge / rdc / r8610 / r8610.c
blob: 328f3bef8ca223b6272c7e44bf0c90c00c39b52a [file] [log] [blame]
Rudolf Marek6b89b4c2012-03-25 18:16:11 +0200[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +0100[diff] [blame]17 * Foundation, Inc.
Rudolf Marek6b89b4c2012-03-25 18:16:11 +0200[diff] [blame]18 */
19
20#include <arch/io.h>
21#include <console/console.h>
22#include <device/device.h>
23#include <device/pci.h>
24#include <device/pci_ids.h>
25#include <pc80/i8259.h>
26#include <stdlib.h>
27
28static const unsigned char enetIrqs[4] = { 10, 0, 0, 0 };
29static const unsigned char usbIrqs[4] = { 15, 14, 0, 0 };
30
31static void pci_routing_fixup(struct device *dev)
32{
33 pci_assign_irqs(0, 0x8, enetIrqs);
34 pci_assign_irqs(0, 0xa, usbIrqs);
35}
36
37static void r8610_init(struct device *dev)
38{
39 device_t nb_dev;
40 u32 tmp;
41
42 printk(BIOS_DEBUG, "r8610 init\n");
43
44 /* clear DMA? */
45 outb(0x4, 0x8);
46 outb(0x4, 0x10);
47
48 outb(0xfc, 0x61);
49
50 /* Set serial base */
51 pci_write_config32(dev, 0x54, 0x3f8);
52 /* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
53 pci_write_config32(dev, 0x50, 0x84101012);
54
55 /* Enable internal Port92, enable chipselect for flash */
56 tmp = pci_read_config32(dev, 0x40);
57 pci_write_config32(dev, 0x40, tmp | 0x07FF0600);
58
59 /* buffer strength SB pins */
60 pci_write_config32(dev, 0x5c, 0x2315);
61
62 /* EHCI 14, OHCI 15, MAC1 disable, MAC0 10, INTD 9, INTC 9, INTB 12, INTA INT10 */
63 pci_write_config32(dev, 0x58, 0xdf0311b3);
64
65 /* USB PHY control */
66 nb_dev = dev_find_device(PCI_VENDOR_ID_RDC,
67 PCI_DEVICE_ID_RDC_R8610_NB, 0);
68
69 tmp = pci_read_config32(nb_dev, 0xc0);
70 tmp |= 0x40000;
71 pci_write_config32(nb_dev, 0xc0, tmp);
72
73 setup_i8259();
74}
75
76static void r8610_read_resources(device_t dev)
77{
78 struct resource *res;
79
80 pci_dev_read_resources(dev);
81
82 res = new_resource(dev, 1);
83 res->base = 0x0UL;
84 res->size = 0x1000UL;
85 res->limit = 0xffffUL;
86 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
87
88 /* Reserve space for flash */
89 res = new_resource(dev, 2);
90 res->base = 0xff800000;
91 res->size = 8*1024*1024;
92 res->limit = 0xffffffffUL;
93 res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
94 IORESOURCE_ASSIGNED;
95}
96
97static void southbridge_init(struct device *dev)
98{
99 r8610_init(dev);
100 pci_routing_fixup(dev);
101}
102
103static struct device_operations r8610_sb_ops = {
104 .read_resources = r8610_read_resources,
105 .set_resources = pci_dev_set_resources,
106 .enable_resources = pci_dev_enable_resources,
107 .init = &southbridge_init,
Rudolf Marek6b89b4c2012-03-25 18:16:11 +0200[diff] [blame]108 .enable = 0,
109 .ops_pci = 0,
110};
111
112static const struct pci_driver lpc_driver __pci_driver = {
113 .ops = &r8610_sb_ops,
114 .vendor = PCI_VENDOR_ID_RDC,
115 .device = PCI_DEVICE_ID_RDC_R8610_SB,
116};