blob: 266883ec24514d6c4920f98441cdab1f4e64c6dd [file] [log] [blame]
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2013, 2014 Vladimir Serbinenko
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 or (at your option)
9 * any later version of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010018 * Foundation, Inc.
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020019 */
20
21#include <arch/io.h>
22#include <console/console.h>
23#include <delay.h>
24#include <device/device.h>
25#include <string.h>
26
27#include <drivers/intel/gma/edid.h>
28#include <drivers/intel/gma/i915.h>
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020029#include "gma.h"
30#include "chip.h"
31#include <pc80/vga.h>
32#include <pc80/vga_io.h>
33#include <device/pci_def.h>
34#include <device/pci_rom.h>
35
36#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
37
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080038static void train_link(u8 *mmio)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020039{
40 /* Clear interrupts. */
41 write32(mmio + DEIIR, 0xffffffff);
42
43 write32(mmio + 0xf000c, 0x2040);
44 write32(mmio + 0xf000c, 0x2050);
45 write32(mmio + 0x60100, 0x44000);
46 write32(mmio + 0xf000c, 0x22050);
47
48 mdelay(1);
49
50 write32(mmio + 0x000f0018, 0x0000008ff);
51 write32(mmio + 0x000f1018, 0x0000008ff);
52
53 write32(mmio + 0x000f000c, 0x001a2050);
54 write32(mmio + 0x00060100, 0x001c4000);
55
56 write32(mmio + 0x00060100, 0x801c4000);
57 write32(mmio + 0x000f000c, 0x801a2050);
58
59 write32(mmio + 0x00060100, 0x801c4000);
60 write32(mmio + 0x000f000c, 0x801a2050);
61 mdelay(1);
62
63 read32(mmio + 0x000f0014); // = 0x00000100
64 write32(mmio + 0x000f0014, 0x00000100);
65 write32(mmio + 0x00060100, 0x901c4000);
66 write32(mmio + 0x000f000c, 0x801a2150);
67 mdelay(1);
68 read32(mmio + 0x000f0014); // = 0x00000600
69}
70
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -080071static void power_port(u8 *mmio)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +020072{
73 read32(mmio + 0x000e1100); // = 0x00000000
74 write32(mmio + 0x000e1100, 0x00000000);
75 write32(mmio + 0x000e1100, 0x00010000);
76 read32(mmio + 0x000e1100); // = 0x00010000
77 read32(mmio + 0x000e1100); // = 0x00010000
78 read32(mmio + 0x000e1100); // = 0x00000000
79 write32(mmio + 0x000e1100, 0x00000000);
80 read32(mmio + 0x000e1100); // = 0x00000000
81 read32(mmio + 0x000e4200); // = 0x0000001c
82 write32(mmio + 0x000e4210, 0x8004003e);
83 write32(mmio + 0x000e4214, 0x80060002);
84 write32(mmio + 0x000e4218, 0x01000000);
85 read32(mmio + 0x000e4210); // = 0x5144003e
86 write32(mmio + 0x000e4210, 0x5344003e);
87 read32(mmio + 0x000e4210); // = 0x0144003e
88 write32(mmio + 0x000e4210, 0x8074003e);
89 read32(mmio + 0x000e4210); // = 0x5144003e
90 read32(mmio + 0x000e4210); // = 0x5144003e
91 write32(mmio + 0x000e4210, 0x5344003e);
92 read32(mmio + 0x000e4210); // = 0x0144003e
93 write32(mmio + 0x000e4210, 0x8074003e);
94 read32(mmio + 0x000e4210); // = 0x5144003e
95 read32(mmio + 0x000e4210); // = 0x5144003e
96 write32(mmio + 0x000e4210, 0x5344003e);
97 read32(mmio + 0x000e4210); // = 0x0144003e
98 write32(mmio + 0x000e4210, 0x8074003e);
99 read32(mmio + 0x000e4210); // = 0x5144003e
100 read32(mmio + 0x000e4210); // = 0x5144003e
101 write32(mmio + 0x000e4210, 0x5344003e);
102 write32(mmio + 0x000e4f00, 0x0100030c);
103 write32(mmio + 0x000e4f04, 0x00b8230c);
104 write32(mmio + 0x000e4f08, 0x06f8930c);
105 write32(mmio + 0x000e4f0c, 0x09f8e38e);
106 write32(mmio + 0x000e4f10, 0x00b8030c);
107 write32(mmio + 0x000e4f14, 0x0b78830c);
108 write32(mmio + 0x000e4f18, 0x0ff8d3cf);
109 write32(mmio + 0x000e4f1c, 0x01e8030c);
110 write32(mmio + 0x000e4f20, 0x0ff863cf);
111 write32(mmio + 0x000e4f24, 0x0ff803cf);
112 write32(mmio + 0x000c4030, 0x00001000);
113 read32(mmio + 0x000c4000); // = 0x00000000
114 write32(mmio + 0x000c4030, 0x00001000);
115 read32(mmio + 0x000e1150); // = 0x0000001c
116 write32(mmio + 0x000e1150, 0x0000089c);
117 write32(mmio + 0x000fcc00, 0x01986f00);
118 write32(mmio + 0x000fcc0c, 0x01986f00);
119 write32(mmio + 0x000fcc18, 0x01986f00);
120 write32(mmio + 0x000fcc24, 0x01986f00);
121 read32(mmio + 0x000c4000); // = 0x00000000
122 read32(mmio + 0x000e1180); // = 0x40000002
123}
124
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200125int i915lightup_sandy(const struct i915_gpu_controller_info *info,
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800126 u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200127{
128 int i;
129 u8 edid_data[128];
130 struct edid edid;
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700131 struct edid_mode *mode;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200132 u32 hactive, vactive, right_border, bottom_border;
133 int hpolarity, vpolarity;
134 u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
135 u32 candp1, candn;
136 u32 best_delta = 0xffffffff;
137 u32 target_frequency;
138 u32 pixel_p1 = 1;
139 u32 pixel_n = 1;
140 u32 pixel_m1 = 1;
141 u32 pixel_m2 = 1;
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200142 u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200143 u32 data_m1;
144 u32 data_n1 = 0x00800000;
145 u32 link_m1;
146 u32 link_n1 = 0x00080000;
147
148 write32(mmio + 0x00070080, 0x00000000);
149 write32(mmio + DSPCNTR(0), 0x00000000);
150 write32(mmio + 0x00071180, 0x00000000);
151 write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
152 write32(mmio + 0x0007019c, 0x00000000);
153 write32(mmio + 0x0007119c, 0x00000000);
154 write32(mmio + 0x000ec008, 0x2c010000);
155 write32(mmio + 0x000ec020, 0x2c010000);
156 write32(mmio + 0x000ec038, 0x2c010000);
157 write32(mmio + 0x000ec050, 0x2c010000);
158 write32(mmio + 0x000ec408, 0x2c010000);
159 write32(mmio + 0x000ec420, 0x2c010000);
160 write32(mmio + 0x000ec438, 0x2c010000);
161 write32(mmio + 0x000ec450, 0x2c010000);
162 vga_gr_write(0x18, 0);
163 write32(mmio + 0x00042004, 0x02000000);
164 write32(mmio + 0x000fd034, 0x8421ffe0);
165
166 /* Setup GTT. */
167 for (i = 0; i < 0x2000; i++)
168 {
169 outl((i << 2) | 1, piobase);
170 outl(physbase + (i << 12) + 1, piobase + 4);
171 }
172
173 vga_misc_write(0x67);
174
175 const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
176 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
177 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
178 0xff
179 };
180 vga_cr_write(0x11, 0);
181
182 for (i = 0; i <= 0x18; i++)
183 vga_cr_write(i, cr[i]);
184
185 power_port(mmio);
186
187 intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700188 decode_edid(edid_data, sizeof(edid_data), &edid);
189 mode = &edid.mode;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200190
191 /* Disable screen memory to prevent garbage from appearing. */
192 vga_sr_write(1, vga_sr_read(1) | 0x20);
193
194 hactive = edid.x_resolution;
195 vactive = edid.y_resolution;
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700196 right_border = mode->hborder;
197 bottom_border = mode->vborder;
198 hpolarity = (mode->phsync == '-');
199 vpolarity = (mode->pvsync == '-');
200 vsync = mode->vspw;
201 hsync = mode->hspw;
202 vblank = mode->vbl;
203 hblank = mode->hbl;
204 hfront_porch = mode->hso;
205 vfront_porch = mode->vso;
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200206
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700207 target_frequency = info->lvds_dual_channel ? mode->pixel_clock
208 : (2 * mode->pixel_clock);
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200209#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
210 vga_textmode_init();
211#else
212 vga_sr_write(1, 1);
213 vga_sr_write(0x2, 0xf);
214 vga_sr_write(0x3, 0x0);
215 vga_sr_write(0x4, 0xe);
216 vga_gr_write(0, 0x0);
217 vga_gr_write(1, 0x0);
218 vga_gr_write(2, 0x0);
219 vga_gr_write(3, 0x0);
220 vga_gr_write(4, 0x0);
221 vga_gr_write(5, 0x0);
222 vga_gr_write(6, 0x5);
223 vga_gr_write(7, 0xf);
224 vga_gr_write(0x10, 0x1);
225 vga_gr_write(0x11, 0);
226
227
228 edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
229
230 write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
231 write32(mmio + DSPADDR(0), 0);
232 write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
233 write32(mmio + DSPSURF(0), 0);
234 for (i = 0; i < 0x100; i++)
235 write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
236#endif
237
238 /* Find suitable divisors. */
239 for (candp1 = 1; candp1 <= 8; candp1++) {
240 for (candn = 5; candn <= 10; candn++) {
241 u32 cur_frequency;
242 u32 m; /* 77 - 131. */
243 u32 denom; /* 35 - 560. */
244 u32 current_delta;
245
246 denom = candn * candp1 * 7;
247 /* Doesnt overflow for up to
248 5000000 kHz = 5 GHz. */
249 m = (target_frequency * denom + 60000) / 120000;
250
251 if (m < 77 || m > 131)
252 continue;
253
254 cur_frequency = (120000 * m) / denom;
255 if (target_frequency > cur_frequency)
256 current_delta = target_frequency - cur_frequency;
257 else
258 current_delta = cur_frequency - target_frequency;
259
260
261 if (best_delta > current_delta) {
262 best_delta = current_delta;
263 pixel_n = candn;
264 pixel_p1 = candp1;
265 pixel_m2 = ((m + 3) % 5) + 7;
266 pixel_m1 = (m - pixel_m2) / 5;
267 }
268 }
269 }
270
271 if (best_delta == 0xffffffff) {
272 printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
273 return 0;
274 }
275
Alexandru Gagniucc2418552015-09-02 09:00:45 -0700276 link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
277 data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200278 / (link_frequency * 8 * (info->lvds_num_lanes ? : 4));
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200279
280 printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
281 hactive, vactive);
282 printk(BIOS_DEBUG, "Borders %d x %d\n",
283 right_border, bottom_border);
284 printk(BIOS_DEBUG, "Blank %d x %d\n",
285 hblank, vblank);
286 printk(BIOS_DEBUG, "Sync %d x %d\n",
287 hsync, vsync);
288 printk(BIOS_DEBUG, "Front porch %d x %d\n",
289 hfront_porch, vfront_porch);
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200290 printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200291 ? "Spread spectrum clock\n" : "DREF clock\n"));
292 printk(BIOS_DEBUG,
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200293 info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200294 printk(BIOS_DEBUG, "Polarities %d, %d\n",
295 hpolarity, vpolarity);
296 printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
297 data_m1, data_n1);
298 printk(BIOS_DEBUG, "Link frequency %d kHz\n",
299 link_frequency);
300 printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
301 link_m1, link_n1);
302 printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
303 pixel_n, pixel_m1, pixel_m2, pixel_p1);
304 printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
305 120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
306 / (pixel_p1 * 7));
307
308 write32(mmio + PCH_LVDS,
309 (hpolarity << 20) | (vpolarity << 21)
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200310 | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200311 | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
312 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
313 | LVDS_DETECTED);
314 write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200315 write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200316 ? 0x1002 : 0x400));
317 mdelay(1);
318 write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
319 | (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
320 write32(mmio + _PCH_FP0(0),
321 ((pixel_n - 2) << 16)
322 | ((pixel_m1 - 2) << 8) | pixel_m2);
323 write32(mmio + PCH_DPLL_SEL, 8);
324 write32(mmio + _PCH_DPLL(0),
325 DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200326 | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200327 : DPLLB_LVDS_P2_CLOCK_DIV_14)
328 | (0x10000 << (pixel_p1 - 1))
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200329 | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200330 | (0x1 << (pixel_p1 - 1)));
331 mdelay(1);
332 write32(mmio + _PCH_DPLL(0),
333 DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200334 | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200335 : DPLLB_LVDS_P2_CLOCK_DIV_14)
336 | (0x10000 << (pixel_p1 - 1))
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200337 | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200338 | (0x1 << (pixel_p1 - 1)));
339 /* Re-lock the registers. */
340 write32(mmio + PCH_PP_CONTROL,
341 (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
342
343 write32(mmio + PCH_LVDS,
344 (hpolarity << 20) | (vpolarity << 21)
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200345 | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200346 | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
347 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
348 | LVDS_DETECTED);
349
350 write32(mmio + HTOTAL(0),
351 ((hactive + right_border + hblank - 1) << 16)
352 | (hactive - 1));
353 write32(mmio + HBLANK(0),
354 ((hactive + right_border + hblank - 1) << 16)
355 | (hactive + right_border - 1));
356 write32(mmio + HSYNC(0),
357 ((hactive + right_border + hfront_porch + hsync - 1) << 16)
358 | (hactive + right_border + hfront_porch - 1));
359
360 write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
361 | (vactive - 1));
362 write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
363 | (vactive + bottom_border - 1));
364 write32(mmio + VSYNC(0),
365 (vactive + bottom_border + vfront_porch + vsync - 1)
366 | (vactive + bottom_border + vfront_porch - 1));
367
368 write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
369
370 write32(mmio + PF_WIN_POS(0), 0);
371#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
372 write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
373 write32(mmio + PF_CTL(0),0);
374 write32(mmio + PF_WIN_SZ(0), 0);
375#else
376 write32(mmio + PIPESRC(0), (639 << 16) | 399);
377 write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
378 write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
379#endif
380
381 mdelay(1);
382
383 write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
384 write32(mmio + PIPE_DATA_N1(0), data_n1);
385 write32(mmio + PIPE_LINK_M1(0), link_m1);
386 write32(mmio + PIPE_LINK_N1(0), link_n1);
387
388 write32(mmio + 0x000f000c, 0x00002040);
389 mdelay(1);
390 write32(mmio + 0x000f000c, 0x00002050);
391 write32(mmio + 0x00060100, 0x00044000);
392 mdelay(1);
393 write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
394 write32(mmio + 0x000f000c, 0x00022050);
395 write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
396 write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
397
398#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
399 write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
400#else
401 write32(mmio + CPU_VGACNTRL, 0x20298e);
402#endif
403 train_link(mmio);
404
405#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
406 write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
407 mdelay(1);
408#endif
409
410 write32(mmio + TRANS_HTOTAL(0),
411 ((hactive + right_border + hblank - 1) << 16)
412 | (hactive - 1));
413 write32(mmio + TRANS_HBLANK(0),
414 ((hactive + right_border + hblank - 1) << 16)
415 | (hactive + right_border - 1));
416 write32(mmio + TRANS_HSYNC(0),
417 ((hactive + right_border + hfront_porch + hsync - 1) << 16)
418 | (hactive + right_border + hfront_porch - 1));
419
420 write32(mmio + TRANS_VTOTAL(0),
421 ((vactive + bottom_border + vblank - 1) << 16)
422 | (vactive - 1));
423 write32(mmio + TRANS_VBLANK(0),
424 ((vactive + bottom_border + vblank - 1) << 16)
425 | (vactive + bottom_border - 1));
426 write32(mmio + TRANS_VSYNC(0),
427 (vactive + bottom_border + vfront_porch + vsync - 1)
428 | (vactive + bottom_border + vfront_porch - 1));
429
430 write32(mmio + 0x00060100, 0xb01c4000);
431 write32(mmio + 0x000f000c, 0x801a2350);
432 mdelay(1);
433 write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
434#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
435 | TRANS_STATE_MASK
436#endif
437 );
438
439 write32(mmio + PCH_LVDS,
440 LVDS_PORT_ENABLE
441 | (hpolarity << 20) | (vpolarity << 21)
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200442 | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200443 | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
444 | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
445 | LVDS_DETECTED);
446
447 write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
448 write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
449 mdelay(1);
450 write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
451 | PANEL_POWER_ON | PANEL_POWER_RESET);
452
453 printk (BIOS_DEBUG, "waiting for panel powerup\n");
454 while (1) {
455 u32 reg32;
456 reg32 = read32(mmio + PCH_PP_STATUS);
457 if (((reg32 >> 28) & 3) == 0)
458 break;
459 }
460 printk (BIOS_DEBUG, "panel powered up\n");
461
462 write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
463
464 /* Enable screen memory. */
465 vga_sr_write(1, vga_sr_read(1) & ~0x20);
466
467 /* Clear interrupts. */
468 write32(mmio + DEIIR, 0xffffffff);
469 write32(mmio + SDEIIR, 0xffffffff);
470
471#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
472 memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
473 set_vbe_mode_info_valid(&edid, lfb);
474#endif
475
476 /* Linux relies on VBT for panel info. */
Vladimir Serbinenkoa71bdc32014-08-30 00:35:39 +0200477 generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
478 "$VBT SNB/IVB-MOBILE ");
Vladimir Serbinenko9ba922f2014-08-24 22:38:07 +0200479
480 return 1;
481}
482
483#endif