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Frank Vibrans2b4c8312011-02-14 18:30:54 +00001/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * mfParallelTraining.c
6 *
7 * This is the parallel training feature
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: (Mem/Feat/PARTRN)
12 * @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
13 *
14 **/
15/*
16 *****************************************************************************
17 *
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +100020 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +000021 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +100028 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
Frank Vibrans2b4c8312011-02-14 18:30:54 +000030 * from this software without specific prior written permission.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +100031 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +000032 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Edward O'Callaghan1542a6f2014-07-06 19:24:06 +100042 *
Frank Vibrans2b4c8312011-02-14 18:30:54 +000043 * ***************************************************************************
44 *
45 */
46
47
48
49
50#include "AGESA.h"
51#include "amdlib.h"
52#include "OptionMemory.h"
53#include "mm.h"
54#include "mn.h"
55#include "Ids.h"
56#include "cpuRegisters.h"
57#include "cpuApicUtilities.h"
58#include "mfParallelTraining.h"
59#include "heapManager.h"
60#include "GeneralServices.h"
61#include "Filecode.h"
62CODE_GROUP (G2_PEI)
63RDATA_GROUP (G2_PEI)
64
65#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE
66
67/*-----------------------------------------------------------------------------
68 * EXPORTED FUNCTIONS
69 *
70 *-----------------------------------------------------------------------------
71 */
72extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
73
74/* -----------------------------------------------------------------------------*/
75/**
76 *
77 *
78 * This is the main function to perform parallel training on all nodes.
79 * This is the routine which will run on the remote AP.
80 *
81 * @param[in,out] *EnvPtr - Pointer to the Training Environment Data
82 * @param[in,out] *StdHeader - Pointer to the Standard Header of the AP
83 *
84 * @return TRUE - This feature is enabled.
85 * @return FALSE - This feature is not enabled.
86 */
87BOOLEAN
88MemFParallelTraining (
89 IN OUT REMOTE_TRAINING_ENV *EnvPtr,
90 IN OUT AMD_CONFIG_PARAMS *StdHeader
91 )
92{
93 MEM_PARAMETER_STRUCT ParameterList;
94 MEM_NB_BLOCK NB;
95 MEM_TECH_BLOCK TB;
96 ALLOCATE_HEAP_PARAMS AllocHeapParams;
97 MEM_DATA_STRUCT *MemPtr;
98 DIE_STRUCT *MCTPtr;
99 UINT8 p;
100 UINT8 i;
101 UINT8 Dct;
102 UINT8 Channel;
103 UINT8 *BufferPtr;
104 UINT8 DctCount;
105 UINT8 ChannelCount;
106 UINT8 RowCount;
107 UINT8 ColumnCount;
108 UINT16 SizeOfNewBuffer;
109 AP_DATA_TRANSFER ReturnData;
110
111 //
112 // Initialize Parameters
113 //
114 ReturnData.DataPtr = NULL;
115 ReturnData.DataSizeInDwords = 0;
116 ReturnData.DataTransferFlags = 0;
117
118 ASSERT (EnvPtr != NULL);
119 //
120 // Replace Standard header of a AP
121 //
122 LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader));
123
124
125 //
126 // Allocate buffer for training data
127 //
128 BufferPtr = (UINT8 *) (&EnvPtr->DieStruct);
129 DctCount = EnvPtr->DieStruct.DctCount;
130 BufferPtr += sizeof (DIE_STRUCT);
131 ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount;
132 BufferPtr += DctCount * sizeof (DCT_STRUCT);
133 RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount;
134 ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount;
135
136 SizeOfNewBuffer = sizeof (DIE_STRUCT) +
137 DctCount * (
138 sizeof (DCT_STRUCT) + (
139 ChannelCount * (
140 sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
141 RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES +
142 (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
143 )
144 )
145 )
146 );
147 AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer;
148 AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0);
149 AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
150 if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
151 BufferPtr = AllocHeapParams.BufferPtr;
152 LibAmdMemCopy ( BufferPtr,
153 &(EnvPtr->DieStruct),
154 sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))),
155 StdHeader
156 );
157
158 //
159 // Fix up pointers
160 //
161 MCTPtr = (DIE_STRUCT *) BufferPtr;
162 BufferPtr += sizeof (DIE_STRUCT);
163 MCTPtr->DctData = (DCT_STRUCT *) BufferPtr;
164 BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT);
165 for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
166 MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr;
167 BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT);
168 for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
169 MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr;
170 MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct];
171 }
172 }
173 NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr;
174 BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK);
175
176 ReturnData.DataPtr = AllocHeapParams.BufferPtr;
177 ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4;
178 ReturnData.DataTransferFlags = 0;
179
180 //
181 // Allocate Memory for the MEM_DATA_STRUCT we will use
182 //
183 AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
184 AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
185 AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
186 if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
187 MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
188
189 LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader);
190
191 //
192 // Copy Parameters from environment
193 //
194 ParameterList.HoleBase = EnvPtr->HoleBase;
195 ParameterList.BottomIo = EnvPtr->BottomIo;
196 ParameterList.UmaSize = EnvPtr->UmaSize;
197 ParameterList.SysLimit = EnvPtr->SysLimit;
198 ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations;
199 ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration;
200 MemPtr->ParameterListPtr = &ParameterList;
201
202 for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
203 MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p];
204 }
205
206 MemPtr->ErrorHandling = EnvPtr->ErrorHandling;
207 //
208 // Create Local NBBlock and Tech Block
209 //
210 EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr);
211 NB.RefPtr = &ParameterList;
212 NB.MemPtr = MemPtr;
213 i = 0;
214 while (memTechInstalled[i] != NULL) {
215 if (memTechInstalled[i] (&TB, &NB)) {
216 break;
217 }
218 i++;
219 }
220 NB.TechPtr = &TB;
221 NB.TechBlockSwitch (&NB);
222
223 //
224 // Setup CPU Mem Type MSRs on the AP
225 //
226 NB.CpuMemTyping (&NB);
227
228 IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node);
229 //
230 // Call Technology Specific Training routine
231 //
232 NB.TrainingFlow (&NB);
233 //
234 // Copy training data to ReturnData buffer
235 //
236 LibAmdMemCopy ( BufferPtr,
237 MCTPtr->DctData[0].ChData[0].RcvEnDlys,
238 ((DctCount * ChannelCount) * (
239 (RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) +
240 (MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
241 )
242 ),
243 StdHeader);
244
245 HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
246 //
247 // Restore pointers
248 //
249 for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
250 for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
251 MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct;
252 MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct];
253
254 MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys;
255 MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys;
256 MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
257 MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys;
258 MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys;
259 MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys;
260 MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys;
261 MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys;
262 MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask;
263 }
264 MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData;
265 }
266 MCTPtr->DctData = EnvPtr->DieStruct.DctData;
267 }
268
269 //
270 // Signal to BSP that training is complete and Send Results
271 //
272 ASSERT (ReturnData.DataPtr != NULL);
273 ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader);
274
275 //
276 // Clean up and exit.
277 //
278 HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader);
279 } else {
280 MCTPtr = &EnvPtr->DieStruct;
281 PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader);
282 SetMemError (AGESA_FATAL, MCTPtr);
283 ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data
284 }
285 return TRUE;
286}