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Felix Held3f3eca92020-01-23 17:12:32 +01001/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* This file is part of the coreboot project. */
Edward O'Callaghandd2e8c32014-04-24 02:58:11 +10003
Edward O'Callaghandd2e8c32014-04-24 02:58:11 +10004#include <device/device.h>
5#include <device/pnp.h>
6#include "chip.h"
7#include "fintek_internal.h"
8
9#define MULTI_FUNC_SEL_REG1 0x28
10#define MULTI_FUNC_SEL_REG2 0x29
11#define MULTI_FUNC_SEL_REG3 0x2A
12#define MULTI_FUNC_SEL_REG4 0x2B
13#define MULTI_FUNC_SEL_REG5 0x2C
14
Edward O'Callaghan2c9d2cf2014-10-27 23:29:29 +110015void f71869ad_multifunc_init(struct device *dev)
Edward O'Callaghandd2e8c32014-04-24 02:58:11 +100016{
Edward O'Callaghanff7e6762014-07-09 04:12:42 +100017 const struct superio_fintek_f71869ad_config *conf = dev->chip_info;
Edward O'Callaghandd2e8c32014-04-24 02:58:11 +100018
19 pnp_enter_conf_mode(dev);
20
21 /* multi-func select reg1 */
22 pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
23 conf->multi_function_register_1);
24
Elyes HAOUAScf139502016-09-16 20:32:00 +020025 /* multi-func select reg2 (CLK_TUNE_EN = 0) */
Edward O'Callaghandd2e8c32014-04-24 02:58:11 +100026 pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
27 conf->multi_function_register_2);
28
Elyes HAOUAScf139502016-09-16 20:32:00 +020029 /* multi-func select reg3 (CLK_TUNE_EN = 0) */
Edward O'Callaghandd2e8c32014-04-24 02:58:11 +100030 pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
31 conf->multi_function_register_3);
32
Elyes HAOUAScf139502016-09-16 20:32:00 +020033 /* multi-func select reg4 (CLK_TUNE_EN = 0) */
Edward O'Callaghandd2e8c32014-04-24 02:58:11 +100034 pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
35 conf->multi_function_register_4);
36
Elyes HAOUAScf139502016-09-16 20:32:00 +020037 /* multi-func select reg5 (CLK_TUNE_EN = 0) */
Edward O'Callaghandd2e8c32014-04-24 02:58:11 +100038 pnp_write_config(dev, MULTI_FUNC_SEL_REG5,
39 conf->multi_function_register_5);
40
41 pnp_exit_conf_mode(dev);
42}