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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Patrick Georgi0588d192009-08-12 15:00:51 +000016
Uwe Hermannad8c95f2012-04-12 22:00:03 +020017mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Uwe Hermannc04be932009-10-05 13:55:28 +000019menu "General setup"
20
Lee Leahybb70c402017-04-03 07:38:20 -070021config COREBOOT_BUILD
22 bool
23 default y
24
Uwe Hermannc04be932009-10-05 13:55:28 +000025config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000026 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000027 help
28 Append an extra string to the end of the coreboot version.
29
Uwe Hermann168b11b2009-10-07 16:15:40 +000030 This can be useful if, for instance, you want to append the
31 respective board's hostname or some other identifying string to
32 the coreboot version number, so that you can easily distinguish
33 boot logs of different boards from each other.
34
Arthur Heymans6f751542019-06-08 11:28:52 +020035config CONFIGURABLE_CBFS_PREFIX
36 bool
37 help
38 Select this to prompt to use to configure the prefix for cbfs files.
39
Arthur Heymans6010eb22019-10-06 13:34:20 +020040choice
41 prompt "CBFS prefix to use"
42 depends on CONFIGURABLE_CBFS_PREFIX
43 default CBFS_PREFIX_FALLBACK
44
45config CBFS_PREFIX_FALLBACK
46 bool "fallback"
47
48config CBFS_PREFIX_NORMAL
49 bool "normal"
50
51config CBFS_PREFIX_DIY
52 bool "Define your own cbfs prefix"
53
54endchoice
55
Patrick Georgi4b8a2412010-02-09 19:35:16 +000056config CBFS_PREFIX
Arthur Heymans6010eb22019-10-06 13:34:20 +020057 string "CBFS prefix to use" if CBFS_PREFIX_DIY
58 default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
59 default "normal" if CBFS_PREFIX_NORMAL
Patrick Georgi4b8a2412010-02-09 19:35:16 +000060 help
61 Select the prefix to all files put into the image. It's "fallback"
62 by default, "normal" is a common alternative.
63
Patrick Georgi23d89cc2010-03-16 01:17:19 +000064choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020065 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000066 default COMPILER_GCC
67 help
68 This option allows you to select the compiler used for building
69 coreboot.
Martin Rotha5a628e82016-01-19 12:01:09 -070070 You must build the coreboot crosscompiler for the board that you
71 have selected.
72
73 To build all the GCC crosscompilers (takes a LONG time), run:
74 make crossgcc
75
76 For help on individual architectures, run the command:
77 make help_toolchain
Patrick Georgi23d89cc2010-03-16 01:17:19 +000078
79config COMPILER_GCC
80 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020081 help
82 Use the GNU Compiler Collection (GCC) to build coreboot.
83
84 For details see http://gcc.gnu.org.
85
Patrick Georgi23d89cc2010-03-16 01:17:19 +000086config COMPILER_LLVM_CLANG
Martin Rotha5a628e82016-01-19 12:01:09 -070087 bool "LLVM/clang (TESTING ONLY - Not currently working)"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020088 help
Martin Rotha5a628e82016-01-19 12:01:09 -070089 Use LLVM/clang to build coreboot. To use this, you must build the
90 coreboot version of the clang compiler. Run the command
91 make clang
92 Note that this option is not currently working correctly and should
93 really only be selected if you're trying to work on getting clang
94 operational.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020095
96 For details see http://clang.llvm.org.
97
Patrick Georgi23d89cc2010-03-16 01:17:19 +000098endchoice
99
Patrick Georgi9b0de712013-12-29 18:45:23 +0100100config ANY_TOOLCHAIN
101 bool "Allow building with any toolchain"
102 default n
Patrick Georgi9b0de712013-12-29 18:45:23 +0100103 help
104 Many toolchains break when building coreboot since it uses quite
105 unusual linker features. Unless developers explicitely request it,
106 we'll have to assume that they use their distro compiler by mistake.
107 Make sure that using patched compilers is a conscious decision.
108
Patrick Georgi516a2a72010-03-25 21:45:25 +0000109config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200110 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +0000111 default n
112 help
113 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200114
115 Requires the ccache utility in your system $PATH.
116
117 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +0000118
Sol Boucher69b88bf2015-02-26 11:47:19 -0800119config FMD_GENPARSER
120 bool "Generate flashmap descriptor parser using flex and bison"
121 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -0800122 help
123 Enable this option if you are working on the flashmap descriptor
124 parser and made changes to fmd_scanner.l or fmd_parser.y.
125
126 Otherwise, say N to use the provided pregenerated scanner/parser.
127
Martin Rothf411b702017-04-09 19:12:42 -0600128config UTIL_GENPARSER
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100129 bool "Generate SCONFIG & BINCFG parser using flex and bison"
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000130 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000131 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200132 Enable this option if you are working on the sconfig device tree
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100133 parser or bincfg and made changes to the .l or .y files.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200134
Sol Boucher69b88bf2015-02-26 11:47:19 -0800135 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000136
Joe Korty6d772522010-05-19 18:41:15 +0000137config USE_OPTION_TABLE
138 bool "Use CMOS for configuration values"
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000139 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000140 help
141 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200142 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000143
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600144config STATIC_OPTION_TABLE
145 bool "Load default configuration values into CMOS on each boot"
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600146 depends on USE_OPTION_TABLE
147 help
148 Enable this option to reset "CMOS" NVRAM values to default on
149 every boot. Use this if you want the NVRAM configuration to
150 never be modified from its default values.
151
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000152config COMPRESS_RAMSTAGE
153 bool "Compress ramstage with LZMA"
Subrata Banikb5962a92019-06-08 12:29:02 +0530154 depends on HAVE_RAMSTAGE
Martin Roth75e5cb72016-12-15 15:05:37 -0700155 # Default value set at the end of the file
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000156 help
Arthur Heymans7f229332019-11-08 11:59:25 +0100157 Compress ramstage to save memory in the flash image.
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000158
Julius Werner09f29212015-09-29 13:51:35 -0700159config COMPRESS_PRERAM_STAGES
160 bool "Compress romstage and verstage with LZ4"
Subrata Banikb5962a92019-06-08 12:29:02 +0530161 depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
Martin Roth75e5cb72016-12-15 15:05:37 -0700162 # Default value set at the end of the file
Julius Werner09f29212015-09-29 13:51:35 -0700163 help
164 Compress romstage and (if it exists) verstage with LZ4 to save flash
165 space and speed up boot, since the time for reading the image from SPI
166 (and in the vboot case verifying it) is usually much greater than the
167 time spent decompressing. Doesn't work for XIP stages (assume all
168 ARCH_X86 for now) for obvious reasons.
169
Julius Werner99f46832018-05-16 14:14:04 -0700170config COMPRESS_BOOTBLOCK
171 bool
Subrata Banikb5962a92019-06-08 12:29:02 +0530172 depends on HAVE_BOOTBLOCK
Julius Werner99f46832018-05-16 14:14:04 -0700173 help
174 This option can be used to compress the bootblock with LZ4 and attach
175 a small self-decompression stub to its front. This can drastically
176 reduce boot time on platforms where the bootblock is loaded over a
177 very slow connection and bootblock size trumps all other factors for
Jonathan Neuschäfer2930a722018-09-29 17:42:52 +0200178 speed. Since using this option usually requires changes to the
Julius Werner99f46832018-05-16 14:14:04 -0700179 SoC memlayout and possibly extra support code, it should not be
180 user-selectable. (There's no real point in offering this to the user
181 anyway... if it works and saves boot time, you would always want it.)
182
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200183config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200184 bool "Include the coreboot .config file into the ROM image"
Martin Roth75e5cb72016-12-15 15:05:37 -0700185 # Default value set at the end of the file
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200186 help
187 Include the .config file that was used to compile coreboot
188 in the (CBFS) ROM image. This is useful if you want to know which
189 options were used to build a specific coreboot.rom image.
190
Daniele Forsi53847a22014-07-22 18:00:56 +0200191 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200192
193 You can use the following command to easily list the options:
194
195 grep -a CONFIG_ coreboot.rom
196
197 Alternatively, you can also use cbfstool to print the image
198 contents (including the raw 'config' item we're looking for).
199
200 Example:
201
202 $ cbfstool coreboot.rom print
203 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
204 offset 0x0
205 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600206
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200207 Name Offset Type Size
Elyes HAOUAS2119d0b2020-02-16 10:01:33 +0100208 cmos_layout.bin 0x0 CMOS layout 1159
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200209 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200210 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200211 fallback/payload 0x80dc0 payload 51526
212 config 0x8d740 raw 3324
213 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200214
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700215config COLLECT_TIMESTAMPS
216 bool "Create a table of timestamps collected during boot"
Paul Menzel4e4a7632015-10-11 11:57:44 +0200217 default y if ARCH_X86
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700218 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200219 Make coreboot create a table of timer-ID/timer-value pairs to
220 allow measuring time spent at different phases of the boot process.
221
Martin Rothb22bbe22018-03-07 15:32:16 -0700222config TIMESTAMPS_ON_CONSOLE
223 bool "Print the timestamp values on the console"
224 default n
225 depends on COLLECT_TIMESTAMPS
226 help
Kyösti Mälkki8b93cb72020-01-09 08:41:46 +0200227 Print the timestamps to the debug console if enabled at level info.
Martin Rothb22bbe22018-03-07 15:32:16 -0700228
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200229config USE_BLOBS
230 bool "Allow use of binary-only repository"
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200231 help
232 This draws in the blobs repository, which contains binary files that
233 might be required for some chipsets or boards.
234 This flag ensures that a "Free" option remains available for users.
235
Marshall Dawson20ce4002019-10-28 15:55:03 -0600236config USE_AMD_BLOBS
237 bool "Allow AMD blobs repository (with license agreement)"
238 depends on USE_BLOBS
239 help
240 This draws in the amd_blobs repository, which contains binary files
241 distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
242 etc. Selecting this item to download or clone the repo implies your
243 agreement to the AMD license agreement. A copy of the license text
244 may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
245 and your copy of the license is present in the repo once downloaded.
246
247 Note that for some products, omitting PSP, SMU images, or other items
248 may result in a nonbooting coreboot.rom.
249
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800250config COVERAGE
251 bool "Code coverage support"
252 depends on COMPILER_GCC
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800253 help
254 Add code coverage support for coreboot. This will store code
255 coverage information in CBMEM for extraction from user space.
256 If unsure, say N.
257
Ryan Salsamendiab37e9a2017-06-11 21:07:31 -0700258config UBSAN
259 bool "Undefined behavior sanitizer support"
260 default n
261 help
262 Instrument the code with checks for undefined behavior. If unsure,
263 say N because it adds a small performance penalty and may abort
264 on code that happens to work in spite of the UB.
265
Stefan Reinauer58470e32014-10-17 13:08:36 +0200266config RELOCATABLE_RAMSTAGE
Kyösti Mälkki730df3c2016-06-18 07:39:31 +0300267 bool
Nico Huberd83bd532019-12-08 12:05:21 +0100268 default y if ARCH_X86
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200269 select RELOCATABLE_MODULES
Stefan Reinauer58470e32014-10-17 13:08:36 +0200270 help
271 The reloctable ramstage support allows for the ramstage to be built
272 as a relocatable module. The stage loader can identify a place
273 out of the OS way so that copying memory is unnecessary during an S3
274 wake. When selecting this option the romstage is responsible for
275 determing a stack location to use for loading the ramstage.
276
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200277choice
278 prompt "Stage Cache for ACPI S3 resume"
279 default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
280 default TSEG_STAGE_CACHE if SMM_TSEG
281
282config NO_STAGE_CACHE
283 bool "Disabled"
284 help
285 Do not save any component in stage cache for resume path. On resume,
286 all components would be read back from CBFS again.
287
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300288config TSEG_STAGE_CACHE
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200289 bool "TSEG"
290 depends on SMM_TSEG
Stefan Reinauer58470e32014-10-17 13:08:36 +0200291 help
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300292 The option enables stage cache support for platform. Platform
293 can stash copies of postcar, ramstage and raw runtime data
294 inside SMM TSEG, to be restored on S3 resume path.
295
296config CBMEM_STAGE_CACHE
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200297 bool "CBMEM"
298 depends on !SMM_TSEG
Kyösti Mälkki0a4457f2019-08-01 20:29:14 +0300299 help
300 The option enables stage cache support for platform. Platform
301 can stash copies of postcar, ramstage and raw runtime data
302 inside CBMEM.
303
304 While the approach is faster than reloading stages from boot media
305 it is also a possible attack scenario via which OS can possibly
306 circumvent SMM locks and SPI write protections.
307
308 If unsure, select 'N'
Stefan Reinauer58470e32014-10-17 13:08:36 +0200309
Kyösti Mälkki6766f4f2019-12-18 00:19:06 +0200310endchoice
311
Stefan Reinauer58470e32014-10-17 13:08:36 +0200312config UPDATE_IMAGE
313 bool "Update existing coreboot.rom image"
Stefan Reinauer58470e32014-10-17 13:08:36 +0200314 help
315 If this option is enabled, no new coreboot.rom file
316 is created. Instead it is expected that there already
317 is a suitable file for further processing.
318 The bootblock will not be modified.
319
Martin Roth5942e062016-01-20 14:59:21 -0700320 If unsure, select 'N'
321
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400322config BOOTSPLASH_IMAGE
323 bool "Add a bootsplash image"
324 help
325 Select this option if you have a bootsplash image that you would
326 like to add to your ROM.
327
328 This will only add the image to the ROM. To actually run it check
329 options under 'Display' section.
330
331config BOOTSPLASH_FILE
332 string "Bootsplash path and filename"
333 depends on BOOTSPLASH_IMAGE
Martin Roth75e5cb72016-12-15 15:05:37 -0700334 # Default value set at the end of the file
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400335 help
336 The path and filename of the file to use as graphical bootsplash
337 screen. The file format has to be jpg.
338
Nico Huber94cdec62019-06-06 19:36:02 +0200339config HAVE_RAMPAYLOAD
340 bool
341
Subrata Banik7e893a02019-05-06 14:17:41 +0530342config RAMPAYLOAD
343 bool "Enable coreboot flow without executing ramstage"
Subrata Banik86dbe0f2019-06-28 18:18:37 +0530344 default y if ARCH_X86
Nico Huber94cdec62019-06-06 19:36:02 +0200345 depends on HAVE_RAMPAYLOAD
Subrata Banik7e893a02019-05-06 14:17:41 +0530346 help
347 If this option is enabled, coreboot flow will skip ramstage
348 loading and execution of ramstage to load payload.
349
350 Instead it is expected to load payload from postcar stage itself.
351
352 In this flow coreboot will perform basic x86 initialization
353 (DRAM resource allocation), MTRR programming,
354 Skip PCI enumeration logic and only allocate BAR for fixed devices
355 (bootable devices, TPM over GSPI).
356
Subrata Banik37bead62020-02-09 19:13:52 +0530357config HAVE_CONFIGURABLE_RAMSTAGE
358 bool
359
Ronald G. Minnich466ca2c2019-10-22 02:02:24 +0000360config CONFIGURABLE_RAMSTAGE
361 bool "Enable a configurable ramstage."
362 default y if ARCH_X86
Subrata Banik37bead62020-02-09 19:13:52 +0530363 depends on HAVE_CONFIGURABLE_RAMSTAGE
Ronald G. Minnich466ca2c2019-10-22 02:02:24 +0000364 help
365 A configurable ramstage allows you to select which parts of the ramstage
366 to run. Currently, we can only select a minimal PCI scanning step.
367 The minimal PCI scanning will only check those parts that are enabled
368 in the devicetree.cb. By convention none of those devices should be bridges.
369
370config MINIMAL_PCI_SCANNING
371 bool "Enable minimal PCI scanning"
Subrata Banik1cb26a62020-02-09 19:35:16 +0530372 depends on CONFIGURABLE_RAMSTAGE && PCI
Ronald G. Minnich466ca2c2019-10-22 02:02:24 +0000373 help
Subrata Banik1cb26a62020-02-09 19:35:16 +0530374 If this option is enabled, coreboot will scan only PCI devices
Ronald G. Minnich466ca2c2019-10-22 02:02:24 +0000375 marked as mandatory in devicetree.cb
Uwe Hermannc04be932009-10-05 13:55:28 +0000376endmenu
377
Martin Roth026e4dc2015-06-19 23:17:15 -0600378menu "Mainboard"
379
Stefan Reinauera48ca842015-04-04 01:58:28 +0200380source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000381
Marshall Dawsone9375132016-09-04 08:38:33 -0600382config DEVICETREE
383 string
384 default "devicetree.cb"
385 help
386 This symbol allows mainboards to select a different file under their
387 mainboard directory for the devicetree.cb file. This allows the board
388 variants that need different devicetrees to be in the same directory.
389
390 Examples: "devicetree.variant.cb"
391 "variant/devicetree.cb"
392
Furquan Shaikhf2419982018-06-21 18:50:48 -0700393config OVERRIDE_DEVICETREE
394 string
395 default ""
396 help
397 This symbol allows variants to provide an override devicetree file to
398 override the registers and/or add new devices on top of the ones
399 provided by baseboard devicetree using CONFIG_DEVICETREE.
400
401 Examples: "devicetree.variant-override.cb"
402 "variant/devicetree-override.cb"
403
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200404config FMDFILE
405 string "fmap description file in fmd format"
Patrick Georgi5d7ab392015-12-12 00:23:15 +0100406 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200407 default ""
408 help
409 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
410 but in some cases more complex setups are required.
411 When an fmd is specified, it overrides the default format.
412
Arthur Heymans965881b2019-09-25 13:18:52 +0200413config CBFS_SIZE
414 hex "Size of CBFS filesystem in ROM"
415 depends on FMDFILE = ""
416 # Default value set at the end of the file
417 help
418 This is the part of the ROM actually managed by CBFS, located at the
419 end of the ROM (passed through cbfstool -o) on x86 and at at the start
420 of the ROM (passed through cbfstool -s) everywhere else. It defaults
421 to span the whole ROM on all but Intel systems that use an Intel Firmware
422 Descriptor. It can be overridden to make coreboot live alongside other
423 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
424 binaries. This symbol should only be used to generate a default FMAP and
425 is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
426
Martin Rothda1ca202015-12-26 16:51:16 -0700427endmenu
428
Martin Rothb09a5692016-01-24 19:38:33 -0700429# load site-local kconfig to allow user specific defaults and overrides
430source "site-local/Kconfig"
431
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200432config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600433 default n
434 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200435
Duncan Laurie8312df42019-02-01 11:33:57 -0800436config SYSTEM_TYPE_TABLET
437 default n
438 bool
439
440config SYSTEM_TYPE_DETACHABLE
441 default n
442 bool
443
444config SYSTEM_TYPE_CONVERTIBLE
445 default n
446 bool
447
Werner Zehc0fb3612016-01-14 15:08:36 +0100448config CBFS_AUTOGEN_ATTRIBUTES
449 default n
450 bool
451 help
452 If this option is selected, every file in cbfs which has a constraint
453 regarding position or alignment will get an additional file attribute
454 which describes this constraint.
455
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000456menu "Chipset"
457
Duncan Lauried2119762015-06-08 18:11:56 -0700458comment "SoC"
Chris Chingaa8e5d32017-10-20 10:43:39 -0600459source "src/soc/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000460comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200461source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000462comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200463source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000464comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200465source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000466comment "Super I/O"
Omar Pakker57603e22016-07-29 23:31:45 +0200467source "src/superio/*/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000468comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200469source "src/ec/acpi/Kconfig"
470source "src/ec/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000471
Martin Roth59aa2b12015-06-20 16:17:12 -0600472source "src/southbridge/intel/common/firmware/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600473source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600474
Martin Rothe1523ec2015-06-19 22:30:43 -0600475source "src/arch/*/Kconfig"
476
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000477endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000478
Stefan Reinauera48ca842015-04-04 01:58:28 +0200479source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800480
Rudolf Marekd9c25492010-05-16 15:31:53 +0000481menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200482source "src/drivers/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800483source "src/drivers/*/*/Kconfig"
Lee Leahy48dbc662017-05-08 16:56:03 -0700484source "src/commonlib/storage/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000485endmenu
486
Philipp Deppenwiese1899fbe2017-10-16 17:09:33 +0200487menu "Security"
488
489source "src/security/Kconfig"
Wim Vervoorne32d16f2019-11-14 14:10:28 +0100490source "src/vendorcode/eltan/security/Kconfig"
Philipp Deppenwiese1899fbe2017-10-16 17:09:33 +0200491
492endmenu
493
Martin Roth09210a12016-05-17 11:28:23 -0600494source "src/acpi/Kconfig"
495
Aaron Durbin4a36c4e2016-08-11 11:02:26 -0500496# This option is for the current boards/chipsets where SPI flash
497# is not the boot device. Currently nearly all boards/chipsets assume
498# SPI flash is the boot device.
499config BOOT_DEVICE_NOT_SPI_FLASH
500 bool
501 default n
502
503config BOOT_DEVICE_SPI_FLASH
504 bool
505 default y if !BOOT_DEVICE_NOT_SPI_FLASH
506 default n
507
Aaron Durbin16c173f2016-08-11 14:04:10 -0500508config BOOT_DEVICE_MEMORY_MAPPED
509 bool
510 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
511 default n
512 help
513 Inform system if SPI is memory-mapped or not.
514
Aaron Durbine8e118d2016-08-12 15:00:10 -0500515config BOOT_DEVICE_SUPPORTS_WRITES
516 bool
517 default n
518 help
519 Indicate that the platform has writable boot device
520 support.
521
Patrick Georgi0770f252015-04-22 13:28:21 +0200522config RTC
523 bool
524 default n
525
Patrick Georgi0588d192009-08-12 15:00:51 +0000526config HEAP_SIZE
527 hex
Marty E. Plummer0987e432019-04-22 20:46:27 -0500528 default 0x100000 if FLATTENED_DEVICE_TREE
Myles Watson04000f42009-10-16 19:12:49 +0000529 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000530
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700531config STACK_SIZE
532 hex
Julius Werner66a476a2015-10-12 16:45:21 -0700533 default 0x1000 if ARCH_X86
534 default 0x0
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700535
Patrick Georgi0588d192009-08-12 15:00:51 +0000536config MAX_CPUS
537 int
538 default 1
539
Stefan Reinauera48ca842015-04-04 01:58:28 +0200540source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000541
542config HAVE_ACPI_RESUME
543 bool
544 default n
Kyösti Mälkki7cd2c072018-06-03 23:04:28 +0300545 depends on RELOCATABLE_RAMSTAGE
Patrick Georgi0588d192009-08-12 15:00:51 +0000546
Wim Vervoornbccc7e72020-01-15 11:31:25 +0100547config DISABLE_ACPI_HIBERNATE
548 bool
549 default n
550 help
551 Removes S4 from the available sleepstates
552
Aaron Durbin87c9fae2016-01-22 15:26:04 -0600553config RESUME_PATH_SAME_AS_BOOT
554 bool
555 default y if ARCH_X86
556 depends on HAVE_ACPI_RESUME
557 help
558 This option indicates that when a system resumes it takes the
559 same path as a regular boot. e.g. an x86 system runs from the
560 reset vector at 0xfffffff0 on both resume and warm/cold boot.
561
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300562config NO_MONOTONIC_TIMER
Aaron Durbina4217912013-04-29 22:31:51 -0500563 def_bool n
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300564
565config HAVE_MONOTONIC_TIMER
566 bool
567 depends on !NO_MONOTONIC_TIMER
Kyösti Mälkkib28b6b52019-07-01 15:38:25 +0300568 default y
Aaron Durbina4217912013-04-29 22:31:51 -0500569 help
570 The board/chipset provides a monotonic timer.
571
Aaron Durbine5e36302014-09-25 10:05:15 -0500572config GENERIC_UDELAY
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300573 bool
Aaron Durbine5e36302014-09-25 10:05:15 -0500574 depends on HAVE_MONOTONIC_TIMER
Kyösti Mälkki76c43862019-07-01 17:25:41 +0300575 default y if !ARCH_X86
Aaron Durbine5e36302014-09-25 10:05:15 -0500576 help
577 The board/chipset uses a generic udelay function utilizing the
578 monotonic timer.
579
Aaron Durbin340ca912013-04-30 09:58:12 -0500580config TIMER_QUEUE
581 def_bool n
582 depends on HAVE_MONOTONIC_TIMER
583 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300584 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500585
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500586config COOP_MULTITASKING
587 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500588 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500589 help
590 Cooperative multitasking allows callbacks to be multiplexed on the
591 main thread of ramstage. With this enabled it allows for multiple
592 execution paths to take place when they have udelay() calls within
593 their code.
594
595config NUM_THREADS
596 int
597 default 4
598 depends on COOP_MULTITASKING
599 help
600 How many execution threads to cooperatively multitask with.
601
Patrick Georgi0588d192009-08-12 15:00:51 +0000602config HAVE_OPTION_TABLE
603 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000604 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000605 help
606 This variable specifies whether a given board has a cmos.layout
607 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000608 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000609
Patrick Georgi0588d192009-08-12 15:00:51 +0000610config PCI_IO_CFG_EXT
611 bool
612 default n
613
614config IOAPIC
615 bool
616 default n
617
Myles Watson45bb25f2009-09-22 18:49:08 +0000618config USE_WATCHDOG_ON_BOOT
619 bool
620 default n
621
Myles Watson45bb25f2009-09-22 18:49:08 +0000622config GFXUMA
623 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000624 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000625 help
626 Enable Unified Memory Architecture for graphics.
627
Myles Watsonb8e20272009-10-15 13:35:47 +0000628config HAVE_ACPI_TABLES
629 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000630 help
631 This variable specifies whether a given board has ACPI table support.
632 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000633
634config HAVE_MP_TABLE
635 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000636 help
637 This variable specifies whether a given board has MP table support.
638 It is usually set in mainboard/*/Kconfig.
639 Whether or not the MP table is actually generated by coreboot
640 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000641
642config HAVE_PIRQ_TABLE
643 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000644 help
645 This variable specifies whether a given board has PIRQ table support.
646 It is usually set in mainboard/*/Kconfig.
647 Whether or not the PIRQ table is actually generated by coreboot
648 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000649
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200650config COMMON_FADT
651 bool
652 default n
653
Aaron Durbin9420a522015-11-17 16:31:00 -0600654config ACPI_NHLT
655 bool
656 default n
657 help
658 Build support for NHLT (non HD Audio) ACPI table generation.
659
Marshall Dawson991467d2018-09-04 12:32:56 -0600660config ACPI_BERT
661 bool
662 depends on HAVE_ACPI_TABLES
663 help
664 Build an ACPI Boot Error Record Table.
665
Myles Watsond73c1b52009-10-26 15:14:07 +0000666#These Options are here to avoid "undefined" warnings.
667#The actual selection and help texts are in the following menu.
668
Uwe Hermann168b11b2009-10-07 16:15:40 +0000669menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000670
Myles Watsonb8e20272009-10-15 13:35:47 +0000671config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800672 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
673 bool
674 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000675 help
676 Generate an MP table (conforming to the Intel MultiProcessor
677 specification 1.4) for this board.
678
679 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000680
Myles Watsonb8e20272009-10-15 13:35:47 +0000681config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800682 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
683 bool
684 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000685 help
686 Generate a PIRQ table for this board.
687
688 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000689
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200690config GENERATE_SMBIOS_TABLES
691 depends on ARCH_X86
692 bool "Generate SMBIOS tables"
693 default y
694 help
695 Generate SMBIOS tables for this board.
696
697 If unsure, say Y.
698
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200699config SMBIOS_PROVIDED_BY_MOBO
700 bool
701 default n
702
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200703config MAINBOARD_SERIAL_NUMBER
Nico Huberebd8a4f2017-11-01 09:49:16 +0100704 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
705 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200706 depends on GENERATE_SMBIOS_TABLES
707 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600708 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200709 The Serial Number to store in SMBIOS structures.
710
711config MAINBOARD_VERSION
Nico Huberebd8a4f2017-11-01 09:49:16 +0100712 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
713 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200714 depends on GENERATE_SMBIOS_TABLES
715 default "1.0"
716 help
717 The Version Number to store in SMBIOS structures.
718
719config MAINBOARD_SMBIOS_MANUFACTURER
Nico Huberebd8a4f2017-11-01 09:49:16 +0100720 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
721 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200722 depends on GENERATE_SMBIOS_TABLES
723 default MAINBOARD_VENDOR
724 help
725 Override the default Manufacturer stored in SMBIOS structures.
726
727config MAINBOARD_SMBIOS_PRODUCT_NAME
Nico Huberebd8a4f2017-11-01 09:49:16 +0100728 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
729 string
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200730 depends on GENERATE_SMBIOS_TABLES
731 default MAINBOARD_PART_NUMBER
732 help
733 Override the default Product name stored in SMBIOS structures.
734
Julien Viard de Galbert9d231a92018-02-28 13:39:55 +0100735config SMBIOS_ENCLOSURE_TYPE
736 hex
737 depends on GENERATE_SMBIOS_TABLES
738 default 0x09 if SYSTEM_TYPE_LAPTOP
Duncan Laurie8312df42019-02-01 11:33:57 -0800739 default 0x1e if SYSTEM_TYPE_TABLET
740 default 0x1f if SYSTEM_TYPE_CONVERTIBLE
741 default 0x20 if SYSTEM_TYPE_DETACHABLE
Julien Viard de Galbert9d231a92018-02-28 13:39:55 +0100742 default 0x03
743 help
744 System Enclosure or Chassis Types as defined in SMBIOS specification.
Duncan Laurie8312df42019-02-01 11:33:57 -0800745 The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop,
746 convertible, or tablet enclosure will be used if the appropriate
747 system type is selected.
Julien Viard de Galbert9d231a92018-02-28 13:39:55 +0100748
Myles Watson45bb25f2009-09-22 18:49:08 +0000749endmenu
750
Martin Roth21c06502016-02-04 19:52:27 -0700751source "payloads/Kconfig"
Peter Stugea758ca22009-09-17 16:21:31 +0000752
Uwe Hermann168b11b2009-10-07 16:15:40 +0000753menu "Debugging"
754
Nico Huberd67edca2018-11-13 19:28:07 +0100755comment "CPU Debug Settings"
Arthur Heymansaae81902019-11-04 21:50:21 +0100756source "src/cpu/*/Kconfig.debug_cpu"
Nico Huberd67edca2018-11-13 19:28:07 +0100757
Arthur Heymans71bd7e42019-10-20 14:20:53 +0200758comment "BLOB Debug Settings"
759source "src/drivers/intel/fsp*/Kconfig.debug_blob"
760
Nico Huberd67edca2018-11-13 19:28:07 +0100761comment "General Debug Settings"
762
Uwe Hermann168b11b2009-10-07 16:15:40 +0000763# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000764config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000765 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200766 default n
Arthur Heymans8e980132019-11-04 09:33:04 +0100767 depends on DRIVERS_UART
Patrick Georgi0588d192009-08-12 15:00:51 +0000768 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000769 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000770 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000771
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200772config GDB_WAIT
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100773 bool "Wait for a GDB connection in the ramstage"
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200774 default n
775 depends on GDB_STUB
776 help
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100777 If enabled, coreboot will wait for a GDB connection in the ramstage.
778
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200779
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800780config FATAL_ASSERTS
781 bool "Halt when hitting a BUG() or assertion error"
782 default n
783 help
784 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
785
Nico Huber371a6672018-11-13 22:06:40 +0100786config HAVE_DEBUG_GPIO
787 bool
788
789config DEBUG_GPIO
790 bool "Output verbose GPIO debug messages"
791 depends on HAVE_DEBUG_GPIO
792
Stefan Reinauerfe422182012-05-02 16:33:18 -0700793config DEBUG_CBFS
794 bool "Output verbose CBFS debug messages"
795 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700796 help
797 This option enables additional CBFS related debug messages.
798
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000799config HAVE_DEBUG_RAM_SETUP
800 def_bool n
801
Uwe Hermann01ce6012010-03-05 10:03:50 +0000802config DEBUG_RAM_SETUP
803 bool "Output verbose RAM init debug messages"
804 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000805 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000806 help
807 This option enables additional RAM init related debug messages.
808 It is recommended to enable this when debugging issues on your
809 board which might be RAM init related.
810
811 Note: This option will increase the size of the coreboot image.
812
813 If unsure, say N.
814
Myles Watson80e914ff2010-06-01 19:25:31 +0000815config DEBUG_PIRQ
816 bool "Check PIRQ table consistency"
817 default n
818 depends on GENERATE_PIRQ_TABLE
819 help
820 If unsure, say N.
821
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000822config HAVE_DEBUG_SMBUS
823 def_bool n
824
Uwe Hermann01ce6012010-03-05 10:03:50 +0000825config DEBUG_SMBUS
826 bool "Output verbose SMBus debug messages"
827 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000828 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000829 help
830 This option enables additional SMBus (and SPD) debug messages.
831
832 Note: This option will increase the size of the coreboot image.
833
834 If unsure, say N.
835
836config DEBUG_SMI
837 bool "Output verbose SMI debug messages"
838 default n
839 depends on HAVE_SMI_HANDLER
Nico Huber9e53db42018-06-05 22:34:08 +0200840 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
Uwe Hermann01ce6012010-03-05 10:03:50 +0000841 help
842 This option enables additional SMI related debug messages.
843
844 Note: This option will increase the size of the coreboot image.
845
846 If unsure, say N.
847
Uwe Hermanna953f372010-11-10 00:14:32 +0000848# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
849# printk(BIOS_DEBUG, ...) calls.
850config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800851 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
852 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000853 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000854 help
855 This option enables additional malloc related debug messages.
856
857 Note: This option will increase the size of the coreboot image.
858
859 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300860
Kyösti Mälkki66277952018-12-31 15:22:34 +0200861config DEBUG_CONSOLE_INIT
862 bool "Debug console initialisation code"
863 default n
864 help
865 With this option printk()'s are attempted before console hardware
866 initialisation has been completed. Your mileage may vary.
867
868 Typically you will need to modify source in console_hw_init() such
869 that a working console appears before the one you want to debug.
870
871 If unsure, say N.
872
Uwe Hermanna953f372010-11-10 00:14:32 +0000873# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
874# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000875config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800876 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
877 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000878 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000879 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000880 help
881 This option enables additional x86emu related debug messages.
882
883 Note: This option will increase the time to emulate a ROM.
884
885 If unsure, say N.
886
Uwe Hermann01ce6012010-03-05 10:03:50 +0000887config X86EMU_DEBUG
888 bool "Output verbose x86emu debug messages"
889 default n
890 depends on PCI_OPTION_ROM_RUN_YABEL
891 help
892 This option enables additional x86emu related debug messages.
893
894 Note: This option will increase the size of the coreboot image.
895
896 If unsure, say N.
897
898config X86EMU_DEBUG_JMP
899 bool "Trace JMP/RETF"
900 default n
901 depends on X86EMU_DEBUG
902 help
903 Print information about JMP and RETF opcodes from x86emu.
904
905 Note: This option will increase the size of the coreboot image.
906
907 If unsure, say N.
908
909config X86EMU_DEBUG_TRACE
910 bool "Trace all opcodes"
911 default n
912 depends on X86EMU_DEBUG
913 help
914 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000915
Uwe Hermann01ce6012010-03-05 10:03:50 +0000916 WARNING: This will produce a LOT of output and take a long time.
917
918 Note: This option will increase the size of the coreboot image.
919
920 If unsure, say N.
921
922config X86EMU_DEBUG_PNP
923 bool "Log Plug&Play accesses"
924 default n
925 depends on X86EMU_DEBUG
926 help
927 Print Plug And Play accesses made by option ROMs.
928
929 Note: This option will increase the size of the coreboot image.
930
931 If unsure, say N.
932
933config X86EMU_DEBUG_DISK
934 bool "Log Disk I/O"
935 default n
936 depends on X86EMU_DEBUG
937 help
938 Print Disk I/O related messages.
939
940 Note: This option will increase the size of the coreboot image.
941
942 If unsure, say N.
943
944config X86EMU_DEBUG_PMM
945 bool "Log PMM"
946 default n
947 depends on X86EMU_DEBUG
948 help
949 Print messages related to POST Memory Manager (PMM).
950
951 Note: This option will increase the size of the coreboot image.
952
953 If unsure, say N.
954
955
956config X86EMU_DEBUG_VBE
957 bool "Debug VESA BIOS Extensions"
958 default n
959 depends on X86EMU_DEBUG
960 help
961 Print messages related to VESA BIOS Extension (VBE) functions.
962
963 Note: This option will increase the size of the coreboot image.
964
965 If unsure, say N.
966
967config X86EMU_DEBUG_INT10
968 bool "Redirect INT10 output to console"
969 default n
970 depends on X86EMU_DEBUG
971 help
972 Let INT10 (i.e. character output) calls print messages to debug output.
973
974 Note: This option will increase the size of the coreboot image.
975
976 If unsure, say N.
977
978config X86EMU_DEBUG_INTERRUPTS
979 bool "Log intXX calls"
980 default n
981 depends on X86EMU_DEBUG
982 help
983 Print messages related to interrupt handling.
984
985 Note: This option will increase the size of the coreboot image.
986
987 If unsure, say N.
988
989config X86EMU_DEBUG_CHECK_VMEM_ACCESS
990 bool "Log special memory accesses"
991 default n
992 depends on X86EMU_DEBUG
993 help
994 Print messages related to accesses to certain areas of the virtual
995 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
996
997 Note: This option will increase the size of the coreboot image.
998
999 If unsure, say N.
1000
1001config X86EMU_DEBUG_MEM
1002 bool "Log all memory accesses"
1003 default n
1004 depends on X86EMU_DEBUG
1005 help
1006 Print memory accesses made by option ROM.
1007 Note: This also includes accesses to fetch instructions.
1008
1009 Note: This option will increase the size of the coreboot image.
1010
1011 If unsure, say N.
1012
1013config X86EMU_DEBUG_IO
1014 bool "Log IO accesses"
1015 default n
1016 depends on X86EMU_DEBUG
1017 help
1018 Print I/O accesses made by option ROM.
1019
1020 Note: This option will increase the size of the coreboot image.
1021
1022 If unsure, say N.
1023
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001024config X86EMU_DEBUG_TIMINGS
1025 bool "Output timing information"
1026 default n
Kyösti Mälkki91945fb2019-07-10 15:10:22 +03001027 depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +02001028 help
1029 Print timing information needed by i915tool.
1030
1031 If unsure, say N.
1032
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -07001033config DEBUG_SPI_FLASH
1034 bool "Output verbose SPI flash debug messages"
1035 default n
1036 depends on SPI_FLASH
1037 help
1038 This option enables additional SPI flash related debug messages.
1039
Stefan Reinauer8e073822012-04-04 00:07:22 +02001040if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1041# Only visible with the right southbridge and loglevel.
1042config DEBUG_INTEL_ME
1043 bool "Verbose logging for Intel Management Engine"
1044 default n
1045 help
1046 Enable verbose logging for Intel Management Engine driver that
1047 is present on Intel 6-series chipsets.
1048endif
1049
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001050config TRACE
1051 bool "Trace function calls"
1052 default n
1053 help
1054 If enabled, every function will print information to console once
1055 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1056 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
Ben Gardner8420ad42015-11-18 10:46:53 -06001057 of calling function. Please note some printk related functions
Rudolf Marek7f0e9302011-09-02 23:23:41 +02001058 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -08001059
1060config DEBUG_COVERAGE
1061 bool "Debug code coverage"
1062 default n
1063 depends on COVERAGE
1064 help
1065 If enabled, the code coverage hooks in coreboot will output some
1066 information about the coverage data that is dumped.
1067
Jonathan Neuschäferfc04f9b2016-06-29 21:59:32 +02001068config DEBUG_BOOT_STATE
1069 bool "Debug boot state machine"
1070 default n
1071 help
1072 Control debugging of the boot state machine. When selected displays
1073 the state boundaries in ramstage.
1074
Nico Hubere84e6252016-10-05 17:43:56 +02001075config DEBUG_ADA_CODE
1076 bool "Compile debug code in Ada sources"
1077 default n
1078 help
1079 Add the compiler switch `-gnata` to compile code guarded by
1080 `pragma Debug`.
1081
Simon Glass46255f72018-07-12 15:26:07 -06001082config HAVE_EM100_SUPPORT
1083 bool "Platform can support the Dediprog EM100 SPI emulator"
1084 help
1085 This is enabled by platforms which can support using the EM100.
1086
1087config EM100
1088 bool "Configure image for EM100 usage"
1089 depends on HAVE_EM100_SUPPORT
1090 help
1091 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1092 over USB. However it only supports a maximum SPI clock of 20MHz and
1093 single data output. Enable this option to use a 20MHz SPI clock and
1094 disable "Dual Output Fast Read" Support.
1095
1096 On AMD platforms this changes the SPI speed at run-time if the
1097 mainboard code supports this. On supported Intel platforms this works
1098 by changing the settings in the descriptor.bin file.
1099
Uwe Hermann168b11b2009-10-07 16:15:40 +00001100endmenu
1101
Martin Roth8e4aafb2016-12-15 15:25:15 -07001102
1103###############################################################################
1104# Set variables with no prompt - these can be set anywhere, and putting at
1105# the end of this file gives the most flexibility.
Nico Huber3db76532017-05-18 18:07:34 +02001106
1107source "src/lib/Kconfig"
1108
Myles Watson2e672732009-11-12 16:38:03 +00001109config WARNINGS_ARE_ERRORS
1110 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001111 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001112
Peter Stuge51eafde2010-10-13 06:23:02 +00001113# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1114# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1115# mutually exclusive. One of these options must be selected in the
1116# mainboard Kconfig if the chipset supports enabling and disabling of
1117# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1118# in mainboard/Kconfig to know if the button should be enabled or not.
1119
1120config POWER_BUTTON_DEFAULT_ENABLE
1121 def_bool n
1122 help
1123 Select when the board has a power button which can optionally be
1124 disabled by the user.
1125
1126config POWER_BUTTON_DEFAULT_DISABLE
1127 def_bool n
1128 help
1129 Select when the board has a power button which can optionally be
1130 enabled by the user, e.g. when the board ships with a jumper over
1131 the power switch contacts.
1132
1133config POWER_BUTTON_FORCE_ENABLE
1134 def_bool n
1135 help
1136 Select when the board requires that the power button is always
1137 enabled.
1138
1139config POWER_BUTTON_FORCE_DISABLE
1140 def_bool n
1141 help
1142 Select when the board requires that the power button is always
1143 disabled, e.g. when it has been hardwired to ground.
1144
1145config POWER_BUTTON_IS_OPTIONAL
1146 bool
1147 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1148 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1149 help
1150 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001151
1152config REG_SCRIPT
1153 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001154 default n
1155 help
1156 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001157
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001158config MAX_REBOOT_CNT
1159 int
1160 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001161 help
1162 Internal option that sets the maximum number of bootblock executions allowed
1163 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001164 and switching to the fallback image.
Martin Roth59ff3402016-02-09 09:06:46 -07001165
Martin Roth8e4aafb2016-12-15 15:25:15 -07001166config UNCOMPRESSED_RAMSTAGE
1167 bool
1168
1169config NO_XIP_EARLY_STAGES
1170 bool
1171 default n if ARCH_X86
1172 default y
1173 help
1174 Identify if early stages are eXecute-In-Place(XIP).
1175
Martin Roth8e4aafb2016-12-15 15:25:15 -07001176config EARLY_CBMEM_LIST
1177 bool
1178 default n
1179 help
1180 Enable display of CBMEM during romstage and postcar.
1181
1182config RELOCATABLE_MODULES
1183 bool
1184 help
1185 If RELOCATABLE_MODULES is selected then support is enabled for
1186 building relocatable modules in the RAM stage. Those modules can be
1187 loaded anywhere and all the relocations are handled automatically.
1188
Martin Roth8e4aafb2016-12-15 15:25:15 -07001189config GENERIC_GPIO_LIB
1190 bool
1191 help
1192 If enabled, compile the generic GPIO library. A "generic" GPIO
1193 implies configurability usually found on SoCs, particularly the
1194 ability to control internal pull resistors.
1195
Martin Roth8e4aafb2016-12-15 15:25:15 -07001196config BOOTBLOCK_CUSTOM
1197 # To be selected by arch, SoC or mainboard if it does not want use the normal
1198 # src/lib/bootblock.c#main() C entry point.
1199 bool
1200
Martin Roth75e5cb72016-12-15 15:05:37 -07001201###############################################################################
1202# Set default values for symbols created before mainboards. This allows the
1203# option to be displayed in the general menu, but the default to be loaded in
1204# the mainboard if desired.
1205config COMPRESS_RAMSTAGE
1206 default y if !UNCOMPRESSED_RAMSTAGE
1207
1208config COMPRESS_PRERAM_STAGES
1209 depends on !ARCH_X86
1210 default y
1211
1212config INCLUDE_CONFIG_FILE
1213 default y
1214
Martin Roth75e5cb72016-12-15 15:05:37 -07001215config BOOTSPLASH_FILE
1216 depends on BOOTSPLASH_IMAGE
1217 default "bootsplash.jpg"
1218
1219config CBFS_SIZE
1220 default ROM_SIZE
Subrata Banikb5962a92019-06-08 12:29:02 +05301221
1222config HAVE_BOOTBLOCK
1223 bool
1224 default y
1225
1226config HAVE_VERSTAGE
1227 bool
1228 depends on VBOOT_SEPARATE_VERSTAGE
1229 default y
1230
1231config HAVE_ROMSTAGE
1232 bool
1233 default y
1234
Subrata Banikb5962a92019-06-08 12:29:02 +05301235config HAVE_RAMSTAGE
1236 bool
1237 default n if RAMPAYLOAD
1238 default y