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Patrick Georgi0588d192009-08-12 15:00:51 +00001##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00002## This file is part of the coreboot project.
Patrick Georgi0588d192009-08-12 15:00:51 +00003##
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -05004## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stefan Reinauer16f515a2010-01-20 18:44:30 +00005## Copyright (C) 2009-2010 coresystems GmbH
Patrick Georgi0588d192009-08-12 15:00:51 +00006##
Stefan Reinauer16f515a2010-01-20 18:44:30 +00007## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; version 2 of the License.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
Patrick Georgi0588d192009-08-12 15:00:51 +000016
Uwe Hermannad8c95f2012-04-12 22:00:03 +020017mainmenu "coreboot configuration"
Patrick Georgi0588d192009-08-12 15:00:51 +000018
Uwe Hermannc04be932009-10-05 13:55:28 +000019menu "General setup"
20
Lee Leahybb70c402017-04-03 07:38:20 -070021config COREBOOT_BUILD
22 bool
23 default y
24
Uwe Hermannc04be932009-10-05 13:55:28 +000025config LOCALVERSION
Uwe Hermann168b11b2009-10-07 16:15:40 +000026 string "Local version string"
Uwe Hermannc04be932009-10-05 13:55:28 +000027 help
28 Append an extra string to the end of the coreboot version.
29
Uwe Hermann168b11b2009-10-07 16:15:40 +000030 This can be useful if, for instance, you want to append the
31 respective board's hostname or some other identifying string to
32 the coreboot version number, so that you can easily distinguish
33 boot logs of different boards from each other.
34
Patrick Georgi4b8a2412010-02-09 19:35:16 +000035config CBFS_PREFIX
36 string "CBFS prefix to use"
37 default "fallback"
38 help
39 Select the prefix to all files put into the image. It's "fallback"
40 by default, "normal" is a common alternative.
41
Patrick Georgi23d89cc2010-03-16 01:17:19 +000042choice
Uwe Hermannad8c95f2012-04-12 22:00:03 +020043 prompt "Compiler to use"
Patrick Georgi23d89cc2010-03-16 01:17:19 +000044 default COMPILER_GCC
45 help
46 This option allows you to select the compiler used for building
47 coreboot.
Martin Rotha5a628e82016-01-19 12:01:09 -070048 You must build the coreboot crosscompiler for the board that you
49 have selected.
50
51 To build all the GCC crosscompilers (takes a LONG time), run:
52 make crossgcc
53
54 For help on individual architectures, run the command:
55 make help_toolchain
Patrick Georgi23d89cc2010-03-16 01:17:19 +000056
57config COMPILER_GCC
58 bool "GCC"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020059 help
60 Use the GNU Compiler Collection (GCC) to build coreboot.
61
62 For details see http://gcc.gnu.org.
63
Patrick Georgi23d89cc2010-03-16 01:17:19 +000064config COMPILER_LLVM_CLANG
Martin Rotha5a628e82016-01-19 12:01:09 -070065 bool "LLVM/clang (TESTING ONLY - Not currently working)"
Uwe Hermannad8c95f2012-04-12 22:00:03 +020066 help
Martin Rotha5a628e82016-01-19 12:01:09 -070067 Use LLVM/clang to build coreboot. To use this, you must build the
68 coreboot version of the clang compiler. Run the command
69 make clang
70 Note that this option is not currently working correctly and should
71 really only be selected if you're trying to work on getting clang
72 operational.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020073
74 For details see http://clang.llvm.org.
75
Patrick Georgi23d89cc2010-03-16 01:17:19 +000076endchoice
77
Patrick Georgi9b0de712013-12-29 18:45:23 +010078config ANY_TOOLCHAIN
79 bool "Allow building with any toolchain"
80 default n
Patrick Georgi9b0de712013-12-29 18:45:23 +010081 help
82 Many toolchains break when building coreboot since it uses quite
83 unusual linker features. Unless developers explicitely request it,
84 we'll have to assume that they use their distro compiler by mistake.
85 Make sure that using patched compilers is a conscious decision.
86
Patrick Georgi516a2a72010-03-25 21:45:25 +000087config CCACHE
Uwe Hermannad8c95f2012-04-12 22:00:03 +020088 bool "Use ccache to speed up (re)compilation"
Patrick Georgi516a2a72010-03-25 21:45:25 +000089 default n
90 help
91 Enables the use of ccache for faster builds.
Uwe Hermannad8c95f2012-04-12 22:00:03 +020092
93 Requires the ccache utility in your system $PATH.
94
95 For details see https://ccache.samba.org.
Patrick Georgi516a2a72010-03-25 21:45:25 +000096
Sol Boucher69b88bf2015-02-26 11:47:19 -080097config FMD_GENPARSER
98 bool "Generate flashmap descriptor parser using flex and bison"
99 default n
Sol Boucher69b88bf2015-02-26 11:47:19 -0800100 help
101 Enable this option if you are working on the flashmap descriptor
102 parser and made changes to fmd_scanner.l or fmd_parser.y.
103
104 Otherwise, say N to use the provided pregenerated scanner/parser.
105
Martin Rothf411b702017-04-09 19:12:42 -0600106config UTIL_GENPARSER
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100107 bool "Generate SCONFIG & BINCFG parser using flex and bison"
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000108 default n
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000109 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200110 Enable this option if you are working on the sconfig device tree
Denis 'GNUtoo' Carikli780e9312018-01-10 14:35:55 +0100111 parser or bincfg and made changes to the .l or .y files.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200112
Sol Boucher69b88bf2015-02-26 11:47:19 -0800113 Otherwise, say N to use the provided pregenerated scanner/parser.
Stefan Reinauer9bf78102010-08-09 13:28:18 +0000114
Joe Korty6d772522010-05-19 18:41:15 +0000115config USE_OPTION_TABLE
116 bool "Use CMOS for configuration values"
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000117 depends on HAVE_OPTION_TABLE
Joe Korty6d772522010-05-19 18:41:15 +0000118 help
119 Enable this option if coreboot shall read options from the "CMOS"
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200120 NVRAM instead of using hard-coded values.
Joe Korty6d772522010-05-19 18:41:15 +0000121
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600122config STATIC_OPTION_TABLE
123 bool "Load default configuration values into CMOS on each boot"
Timothy Pearsonf20c6e82015-02-14 16:15:31 -0600124 depends on USE_OPTION_TABLE
125 help
126 Enable this option to reset "CMOS" NVRAM values to default on
127 every boot. Use this if you want the NVRAM configuration to
128 never be modified from its default values.
129
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000130config COMPRESS_RAMSTAGE
131 bool "Compress ramstage with LZMA"
Martin Roth75e5cb72016-12-15 15:05:37 -0700132 # Default value set at the end of the file
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000133 help
134 Compress ramstage to save memory in the flash image. Note
135 that decompression might slow down booting if the boot flash
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200136 is connected through a slow link (i.e. SPI).
Sven Schnelle8eee19d2011-05-02 19:53:04 +0000137
Julius Werner09f29212015-09-29 13:51:35 -0700138config COMPRESS_PRERAM_STAGES
139 bool "Compress romstage and verstage with LZ4"
Martin Rothf2e04612016-03-09 15:50:23 -0700140 depends on !ARCH_X86
Martin Roth75e5cb72016-12-15 15:05:37 -0700141 # Default value set at the end of the file
Julius Werner09f29212015-09-29 13:51:35 -0700142 help
143 Compress romstage and (if it exists) verstage with LZ4 to save flash
144 space and speed up boot, since the time for reading the image from SPI
145 (and in the vboot case verifying it) is usually much greater than the
146 time spent decompressing. Doesn't work for XIP stages (assume all
147 ARCH_X86 for now) for obvious reasons.
148
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200149config INCLUDE_CONFIG_FILE
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200150 bool "Include the coreboot .config file into the ROM image"
Martin Roth75e5cb72016-12-15 15:05:37 -0700151 # Default value set at the end of the file
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200152 help
153 Include the .config file that was used to compile coreboot
154 in the (CBFS) ROM image. This is useful if you want to know which
155 options were used to build a specific coreboot.rom image.
156
Daniele Forsi53847a22014-07-22 18:00:56 +0200157 Saying Y here will increase the image size by 2-3KB.
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200158
159 You can use the following command to easily list the options:
160
161 grep -a CONFIG_ coreboot.rom
162
163 Alternatively, you can also use cbfstool to print the image
164 contents (including the raw 'config' item we're looking for).
165
166 Example:
167
168 $ cbfstool coreboot.rom print
169 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
170 offset 0x0
171 Alignment: 64 bytes
Steve Goodrichf0269122012-05-18 11:18:47 -0600172
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200173 Name Offset Type Size
174 cmos_layout.bin 0x0 cmos layout 1159
175 fallback/romstage 0x4c0 stage 339756
Daniele Forsi53847a22014-07-22 18:00:56 +0200176 fallback/ramstage 0x53440 stage 186664
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200177 fallback/payload 0x80dc0 payload 51526
178 config 0x8d740 raw 3324
179 (empty) 0x8e480 null 3610440
Cristian Măgherușan-Stanciud367b002011-06-19 03:03:28 +0200180
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700181config COLLECT_TIMESTAMPS
182 bool "Create a table of timestamps collected during boot"
Paul Menzel4e4a7632015-10-11 11:57:44 +0200183 default y if ARCH_X86
Vadim Bendebury9202473d2011-09-21 14:46:43 -0700184 help
Uwe Hermannad8c95f2012-04-12 22:00:03 +0200185 Make coreboot create a table of timer-ID/timer-value pairs to
186 allow measuring time spent at different phases of the boot process.
187
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200188config USE_BLOBS
189 bool "Allow use of binary-only repository"
Patrick Georgi7e9b9d82012-04-30 21:06:10 +0200190 help
191 This draws in the blobs repository, which contains binary files that
192 might be required for some chipsets or boards.
193 This flag ensures that a "Free" option remains available for users.
194
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800195config COVERAGE
196 bool "Code coverage support"
197 depends on COMPILER_GCC
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800198 help
199 Add code coverage support for coreboot. This will store code
200 coverage information in CBMEM for extraction from user space.
201 If unsure, say N.
202
Ryan Salsamendiab37e9a2017-06-11 21:07:31 -0700203config UBSAN
204 bool "Undefined behavior sanitizer support"
205 default n
206 help
207 Instrument the code with checks for undefined behavior. If unsure,
208 say N because it adds a small performance penalty and may abort
209 on code that happens to work in spite of the UB.
210
Stefan Reinauer58470e32014-10-17 13:08:36 +0200211config RELOCATABLE_RAMSTAGE
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200212 depends on EARLY_CBMEM_INIT
Stefan Reinauer58470e32014-10-17 13:08:36 +0200213 bool "Build the ramstage to be relocatable in 32-bit address space."
Vladimir Serbinenko633352c2015-05-30 22:21:37 +0200214 select RELOCATABLE_MODULES
Stefan Reinauer58470e32014-10-17 13:08:36 +0200215 help
216 The reloctable ramstage support allows for the ramstage to be built
217 as a relocatable module. The stage loader can identify a place
218 out of the OS way so that copying memory is unnecessary during an S3
219 wake. When selecting this option the romstage is responsible for
220 determing a stack location to use for loading the ramstage.
221
222config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
223 depends on RELOCATABLE_RAMSTAGE
Arthur Heymans410f2562017-01-25 15:27:52 +0100224 bool
Stefan Reinauer58470e32014-10-17 13:08:36 +0200225 help
226 The relocated ramstage is saved in an area specified by the
227 by the board and/or chipset.
228
Stefan Reinauer58470e32014-10-17 13:08:36 +0200229config UPDATE_IMAGE
230 bool "Update existing coreboot.rom image"
Stefan Reinauer58470e32014-10-17 13:08:36 +0200231 help
232 If this option is enabled, no new coreboot.rom file
233 is created. Instead it is expected that there already
234 is a suitable file for further processing.
235 The bootblock will not be modified.
236
Martin Roth5942e062016-01-20 14:59:21 -0700237 If unsure, select 'N'
238
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400239config BOOTSPLASH_IMAGE
240 bool "Add a bootsplash image"
241 help
242 Select this option if you have a bootsplash image that you would
243 like to add to your ROM.
244
245 This will only add the image to the ROM. To actually run it check
246 options under 'Display' section.
247
248config BOOTSPLASH_FILE
249 string "Bootsplash path and filename"
250 depends on BOOTSPLASH_IMAGE
Martin Roth75e5cb72016-12-15 15:05:37 -0700251 # Default value set at the end of the file
Konstantin Aladyshev6544cb32015-01-24 18:52:10 +0400252 help
253 The path and filename of the file to use as graphical bootsplash
254 screen. The file format has to be jpg.
255
Uwe Hermannc04be932009-10-05 13:55:28 +0000256endmenu
257
Martin Roth026e4dc2015-06-19 23:17:15 -0600258menu "Mainboard"
259
Stefan Reinauera48ca842015-04-04 01:58:28 +0200260source "src/mainboard/Kconfig"
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +0000261
Marshall Dawsone9375132016-09-04 08:38:33 -0600262config DEVICETREE
263 string
264 default "devicetree.cb"
265 help
266 This symbol allows mainboards to select a different file under their
267 mainboard directory for the devicetree.cb file. This allows the board
268 variants that need different devicetrees to be in the same directory.
269
270 Examples: "devicetree.variant.cb"
271 "variant/devicetree.cb"
272
Martin Roth026e4dc2015-06-19 23:17:15 -0600273config CBFS_SIZE
274 hex "Size of CBFS filesystem in ROM"
Martin Roth75e5cb72016-12-15 15:05:37 -0700275 # Default value set at the end of the file
Martin Roth026e4dc2015-06-19 23:17:15 -0600276 help
277 This is the part of the ROM actually managed by CBFS, located at the
278 end of the ROM (passed through cbfstool -o) on x86 and at at the start
279 of the ROM (passed through cbfstool -s) everywhere else. It defaults
280 to span the whole ROM on all but Intel systems that use an Intel Firmware
281 Descriptor. It can be overridden to make coreboot live alongside other
282 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
283 binaries.
284
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200285config FMDFILE
286 string "fmap description file in fmd format"
Patrick Georgi5d7ab392015-12-12 00:23:15 +0100287 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
Patrick Georgi8a3592e2015-09-16 18:10:52 +0200288 default ""
289 help
290 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
291 but in some cases more complex setups are required.
292 When an fmd is specified, it overrides the default format.
293
Martin Rothda1ca202015-12-26 16:51:16 -0700294endmenu
295
Martin Rothb09a5692016-01-24 19:38:33 -0700296# load site-local kconfig to allow user specific defaults and overrides
297source "site-local/Kconfig"
298
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200299config SYSTEM_TYPE_LAPTOP
Martin Roth595e7772015-04-26 18:53:26 -0600300 default n
301 bool
Vladimir Serbinenkoa9db82f2014-10-16 13:21:47 +0200302
Werner Zehc0fb3612016-01-14 15:08:36 +0100303config CBFS_AUTOGEN_ATTRIBUTES
304 default n
305 bool
306 help
307 If this option is selected, every file in cbfs which has a constraint
308 regarding position or alignment will get an additional file attribute
309 which describes this constraint.
310
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000311menu "Chipset"
312
Duncan Lauried2119762015-06-08 18:11:56 -0700313comment "SoC"
Chris Chingaa8e5d32017-10-20 10:43:39 -0600314source "src/soc/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000315comment "CPU"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200316source "src/cpu/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000317comment "Northbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200318source "src/northbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000319comment "Southbridge"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200320source "src/southbridge/*/*/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000321comment "Super I/O"
Omar Pakker57603e22016-07-29 23:31:45 +0200322source "src/superio/*/*/Kconfig"
Sven Schnelle7592e8b2011-01-27 11:43:03 +0000323comment "Embedded Controllers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200324source "src/ec/acpi/Kconfig"
325source "src/ec/*/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800326# FIXME move to vendorcode
Marc Jones78687972015-04-22 23:16:31 -0600327source "src/drivers/intel/fsp1_0/Kconfig"
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000328
Martin Roth59aa2b12015-06-20 16:17:12 -0600329source "src/southbridge/intel/common/firmware/Kconfig"
Martin Rothe1523ec2015-06-19 22:30:43 -0600330source "src/vendorcode/*/Kconfig"
Martin Roth59aa2b12015-06-20 16:17:12 -0600331
Martin Rothe1523ec2015-06-19 22:30:43 -0600332source "src/arch/*/Kconfig"
333
Uwe Hermann63a8f2a2009-10-26 21:42:13 +0000334endmenu
Patrick Georgi0588d192009-08-12 15:00:51 +0000335
Stefan Reinauera48ca842015-04-04 01:58:28 +0200336source "src/device/Kconfig"
Stefan Reinauer95a63962012-11-13 17:00:01 -0800337
Rudolf Marekd9c25492010-05-16 15:31:53 +0000338menu "Generic Drivers"
Stefan Reinauera48ca842015-04-04 01:58:28 +0200339source "src/drivers/*/Kconfig"
Stefan Reinauer86ddd732016-03-11 20:22:28 -0800340source "src/drivers/*/*/Kconfig"
Lee Leahy48dbc662017-05-08 16:56:03 -0700341source "src/commonlib/storage/Kconfig"
Rudolf Marekd9c25492010-05-16 15:31:53 +0000342endmenu
343
Philipp Deppenwiese1899fbe2017-10-16 17:09:33 +0200344menu "Security"
345
346source "src/security/Kconfig"
347
348endmenu
349
Martin Roth09210a12016-05-17 11:28:23 -0600350source "src/acpi/Kconfig"
351
Aaron Durbin4a36c4e2016-08-11 11:02:26 -0500352# This option is for the current boards/chipsets where SPI flash
353# is not the boot device. Currently nearly all boards/chipsets assume
354# SPI flash is the boot device.
355config BOOT_DEVICE_NOT_SPI_FLASH
356 bool
357 default n
358
359config BOOT_DEVICE_SPI_FLASH
360 bool
361 default y if !BOOT_DEVICE_NOT_SPI_FLASH
362 default n
363
Aaron Durbin16c173f2016-08-11 14:04:10 -0500364config BOOT_DEVICE_MEMORY_MAPPED
365 bool
366 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
367 default n
368 help
369 Inform system if SPI is memory-mapped or not.
370
Aaron Durbine8e118d2016-08-12 15:00:10 -0500371config BOOT_DEVICE_SUPPORTS_WRITES
372 bool
373 default n
374 help
375 Indicate that the platform has writable boot device
376 support.
377
Patrick Georgi0770f252015-04-22 13:28:21 +0200378config RTC
379 bool
380 default n
381
Patrick Georgi0588d192009-08-12 15:00:51 +0000382config HEAP_SIZE
383 hex
Myles Watson04000f42009-10-16 19:12:49 +0000384 default 0x4000
Patrick Georgi0588d192009-08-12 15:00:51 +0000385
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700386config STACK_SIZE
387 hex
Julius Werner66a476a2015-10-12 16:45:21 -0700388 default 0x1000 if ARCH_X86
389 default 0x0
Julius Wernerc3e7c4e2014-09-19 13:18:16 -0700390
Patrick Georgi0588d192009-08-12 15:00:51 +0000391config MAX_CPUS
392 int
393 default 1
394
Stefan Reinauera48ca842015-04-04 01:58:28 +0200395source "src/console/Kconfig"
Patrick Georgi0588d192009-08-12 15:00:51 +0000396
397config HAVE_ACPI_RESUME
398 bool
399 default n
400
Kyösti Mälkki9d6f3652016-06-28 07:38:46 +0300401config ACPI_HUGE_LOWMEM_BACKUP
402 bool
Kyösti Mälkki43e9c932016-11-10 11:50:21 +0200403 default n
Kyösti Mälkki9d6f3652016-06-28 07:38:46 +0300404 help
405 On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
406
Aaron Durbin87c9fae2016-01-22 15:26:04 -0600407config RESUME_PATH_SAME_AS_BOOT
408 bool
409 default y if ARCH_X86
410 depends on HAVE_ACPI_RESUME
411 help
412 This option indicates that when a system resumes it takes the
413 same path as a regular boot. e.g. an x86 system runs from the
414 reset vector at 0xfffffff0 on both resume and warm/cold boot.
415
Patrick Georgi0588d192009-08-12 15:00:51 +0000416config HAVE_HARD_RESET
417 bool
Uwe Hermann748475b2009-10-09 11:47:21 +0000418 default n
Patrick Georgi37bdb872010-02-27 08:39:04 +0000419 help
420 This variable specifies whether a given board has a hard_reset
421 function, no matter if it's provided by board code or chipset code.
422
Timothy Pearson44d53422015-05-18 16:04:10 -0500423config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
424 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300425 depends on EARLY_CBMEM_INIT
Timothy Pearson44d53422015-05-18 16:04:10 -0500426 default n
427
Timothy Pearson7b22d842015-08-28 19:52:05 -0500428config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
429 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300430 depends on EARLY_CBMEM_INIT
Timothy Pearson7b22d842015-08-28 19:52:05 -0500431 default n
432 help
433 This should be enabled on certain plaforms, such as the AMD
434 SR565x, that cannot handle concurrent CBFS accesses from
435 multiple APs during early startup.
436
Timothy Pearsonc764c742015-08-28 20:48:17 -0500437config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
438 bool
Kyösti Mälkkib5664de2016-07-08 13:33:00 +0300439 depends on EARLY_CBMEM_INIT
Timothy Pearsonc764c742015-08-28 20:48:17 -0500440 default n
441
Aaron Durbina4217912013-04-29 22:31:51 -0500442config HAVE_MONOTONIC_TIMER
443 def_bool n
444 help
445 The board/chipset provides a monotonic timer.
446
Aaron Durbine5e36302014-09-25 10:05:15 -0500447config GENERIC_UDELAY
448 def_bool n
449 depends on HAVE_MONOTONIC_TIMER
450 help
451 The board/chipset uses a generic udelay function utilizing the
452 monotonic timer.
453
Aaron Durbin340ca912013-04-30 09:58:12 -0500454config TIMER_QUEUE
455 def_bool n
456 depends on HAVE_MONOTONIC_TIMER
457 help
Kyösti Mälkkiecd84242013-09-13 07:57:49 +0300458 Provide a timer queue for performing time-based callbacks.
Aaron Durbin340ca912013-04-30 09:58:12 -0500459
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500460config COOP_MULTITASKING
461 def_bool n
Aaron Durbin38c326d2013-05-06 12:22:23 -0500462 depends on TIMER_QUEUE && ARCH_X86
Aaron Durbin4409a5e2013-05-06 12:20:52 -0500463 help
464 Cooperative multitasking allows callbacks to be multiplexed on the
465 main thread of ramstage. With this enabled it allows for multiple
466 execution paths to take place when they have udelay() calls within
467 their code.
468
469config NUM_THREADS
470 int
471 default 4
472 depends on COOP_MULTITASKING
473 help
474 How many execution threads to cooperatively multitask with.
475
Patrick Georgi0588d192009-08-12 15:00:51 +0000476config HAVE_OPTION_TABLE
477 bool
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000478 default n
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000479 help
480 This variable specifies whether a given board has a cmos.layout
481 file containing NVRAM/CMOS bit definitions.
Edwin Beasanteb50c7d2010-07-06 21:05:04 +0000482 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
Patrick Georgi0588d192009-08-12 15:00:51 +0000483
Patrick Georgi0588d192009-08-12 15:00:51 +0000484config PIRQ_ROUTE
485 bool
486 default n
487
488config HAVE_SMI_HANDLER
489 bool
490 default n
491
492config PCI_IO_CFG_EXT
493 bool
494 default n
495
496config IOAPIC
497 bool
498 default n
499
Kyösti Mälkki107f72e2014-01-06 11:06:26 +0200500config CACHE_ROM_SIZE_OVERRIDE
Stefan Reinauer5b635792012-08-16 14:05:42 -0700501 hex
Martin Roth3b878122016-09-30 14:43:01 -0600502 default 0x0
Stefan Reinauer5b635792012-08-16 14:05:42 -0700503
Myles Watson45bb25f2009-09-22 18:49:08 +0000504config USE_WATCHDOG_ON_BOOT
505 bool
506 default n
507
Myles Watson45bb25f2009-09-22 18:49:08 +0000508config GFXUMA
509 bool
Myles Watsond73c1b52009-10-26 15:14:07 +0000510 default n
Myles Watson45bb25f2009-09-22 18:49:08 +0000511 help
512 Enable Unified Memory Architecture for graphics.
513
Myles Watsonb8e20272009-10-15 13:35:47 +0000514config HAVE_ACPI_TABLES
515 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000516 help
517 This variable specifies whether a given board has ACPI table support.
518 It is usually set in mainboard/*/Kconfig.
Myles Watsonb8e20272009-10-15 13:35:47 +0000519
520config HAVE_MP_TABLE
521 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000522 help
523 This variable specifies whether a given board has MP table support.
524 It is usually set in mainboard/*/Kconfig.
525 Whether or not the MP table is actually generated by coreboot
526 is configurable by the user via GENERATE_MP_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000527
528config HAVE_PIRQ_TABLE
529 bool
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000530 help
531 This variable specifies whether a given board has PIRQ table support.
532 It is usually set in mainboard/*/Kconfig.
533 Whether or not the PIRQ table is actually generated by coreboot
534 is configurable by the user via GENERATE_PIRQ_TABLE.
Myles Watsonb8e20272009-10-15 13:35:47 +0000535
Alexandru Gagniuc70c660f2012-08-23 02:32:58 -0500536config MAX_PIRQ_LINKS
537 int
538 default 4
539 help
540 This variable specifies the number of PIRQ interrupt links which are
541 routable. On most chipsets, this is 4, INTA through INTD. Some
542 chipsets offer more than four links, commonly up to INTH. They may
543 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
544 table specifies links greater than 4, pirq_route_irqs will not
545 function properly, unless this variable is correctly set.
546
Vladimir Serbinenkoc21e0732014-10-16 12:48:19 +0200547config COMMON_FADT
548 bool
549 default n
550
Aaron Durbin9420a522015-11-17 16:31:00 -0600551config ACPI_NHLT
552 bool
553 default n
554 help
555 Build support for NHLT (non HD Audio) ACPI table generation.
556
Myles Watsond73c1b52009-10-26 15:14:07 +0000557#These Options are here to avoid "undefined" warnings.
558#The actual selection and help texts are in the following menu.
559
Uwe Hermann168b11b2009-10-07 16:15:40 +0000560menu "System tables"
Myles Watson45bb25f2009-09-22 18:49:08 +0000561
Myles Watsonb8e20272009-10-15 13:35:47 +0000562config GENERATE_MP_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800563 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
564 bool
565 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000566 help
567 Generate an MP table (conforming to the Intel MultiProcessor
568 specification 1.4) for this board.
569
570 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000571
Myles Watsonb8e20272009-10-15 13:35:47 +0000572config GENERATE_PIRQ_TABLE
Stefan Reinauer56cd70b2012-11-13 17:33:08 -0800573 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
574 bool
575 default HAVE_PIRQ_TABLE
Uwe Hermann6ba13bb2009-10-15 17:49:07 +0000576 help
577 Generate a PIRQ table for this board.
578
579 If unsure, say Y.
Myles Watson45bb25f2009-09-22 18:49:08 +0000580
Sven Schnelle164bcfd2011-08-14 20:56:34 +0200581config GENERATE_SMBIOS_TABLES
582 depends on ARCH_X86
583 bool "Generate SMBIOS tables"
584 default y
585 help
586 Generate SMBIOS tables for this board.
587
588 If unsure, say Y.
589
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200590config SMBIOS_PROVIDED_BY_MOBO
591 bool
592 default n
593
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200594config MAINBOARD_SERIAL_NUMBER
595 string "SMBIOS Serial Number"
596 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200597 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200598 default "123456789"
Martin Roth595e7772015-04-26 18:53:26 -0600599 help
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200600 The Serial Number to store in SMBIOS structures.
601
602config MAINBOARD_VERSION
603 string "SMBIOS Version Number"
604 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200605 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200606 default "1.0"
607 help
608 The Version Number to store in SMBIOS structures.
609
610config MAINBOARD_SMBIOS_MANUFACTURER
611 string "SMBIOS Manufacturer"
612 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200613 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200614 default MAINBOARD_VENDOR
615 help
616 Override the default Manufacturer stored in SMBIOS structures.
617
618config MAINBOARD_SMBIOS_PRODUCT_NAME
619 string "SMBIOS Product name"
620 depends on GENERATE_SMBIOS_TABLES
Vladimir Serbinenko0afdec42015-05-30 23:08:26 +0200621 depends on !SMBIOS_PROVIDED_BY_MOBO
Stefan Reinauer6023ca42014-10-17 13:28:15 +0200622 default MAINBOARD_PART_NUMBER
623 help
624 Override the default Product name stored in SMBIOS structures.
625
Myles Watson45bb25f2009-09-22 18:49:08 +0000626endmenu
627
Martin Roth21c06502016-02-04 19:52:27 -0700628source "payloads/Kconfig"
Peter Stugea758ca22009-09-17 16:21:31 +0000629
Uwe Hermann168b11b2009-10-07 16:15:40 +0000630menu "Debugging"
631
632# TODO: Better help text and detailed instructions.
Patrick Georgi0588d192009-08-12 15:00:51 +0000633config GDB_STUB
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000634 bool "GDB debugging support"
Rudolf Marek65888022012-03-25 20:51:16 +0200635 default n
Denis 'GNUtoo' Carikli3747ba12015-12-10 22:04:56 +0100636 depends on CONSOLE_SERIAL
Patrick Georgi0588d192009-08-12 15:00:51 +0000637 help
Uwe Hermann5ec2c2b2009-08-25 00:53:22 +0000638 If enabled, you will be able to set breakpoints for gdb debugging.
Stefan Reinauer8677a232010-12-11 20:33:41 +0000639 See src/arch/x86/lib/c_start.S for details.
Patrick Georgi0588d192009-08-12 15:00:51 +0000640
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200641config GDB_WAIT
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100642 bool "Wait for a GDB connection in the ramstage"
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200643 default n
644 depends on GDB_STUB
645 help
Denis 'GNUtoo' Carikli7d234f22015-12-10 21:58:52 +0100646 If enabled, coreboot will wait for a GDB connection in the ramstage.
647
Denis 'GNUtoo' Cariklie4cece02012-06-22 15:56:37 +0200648
Julius Wernerd82e0cf2015-02-17 17:27:23 -0800649config FATAL_ASSERTS
650 bool "Halt when hitting a BUG() or assertion error"
651 default n
652 help
653 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
654
Stefan Reinauerfe422182012-05-02 16:33:18 -0700655config DEBUG_CBFS
656 bool "Output verbose CBFS debug messages"
657 default n
Stefan Reinauerfe422182012-05-02 16:33:18 -0700658 help
659 This option enables additional CBFS related debug messages.
660
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000661config HAVE_DEBUG_RAM_SETUP
662 def_bool n
663
Uwe Hermann01ce6012010-03-05 10:03:50 +0000664config DEBUG_RAM_SETUP
665 bool "Output verbose RAM init debug messages"
666 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000667 depends on HAVE_DEBUG_RAM_SETUP
Uwe Hermann01ce6012010-03-05 10:03:50 +0000668 help
669 This option enables additional RAM init related debug messages.
670 It is recommended to enable this when debugging issues on your
671 board which might be RAM init related.
672
673 Note: This option will increase the size of the coreboot image.
674
675 If unsure, say N.
676
Patrick Georgie82618d2010-10-01 14:50:12 +0000677config HAVE_DEBUG_CAR
678 def_bool n
679
Peter Stuge5015f792010-11-10 02:00:32 +0000680config DEBUG_CAR
681 def_bool n
682 depends on HAVE_DEBUG_CAR
683
684if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
Uwe Hermanna953f372010-11-10 00:14:32 +0000685# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
686# printk(BIOS_DEBUG, ...) calls.
Patrick Georgie82618d2010-10-01 14:50:12 +0000687config DEBUG_CAR
688 bool "Output verbose Cache-as-RAM debug messages"
689 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000690 depends on HAVE_DEBUG_CAR
Patrick Georgie82618d2010-10-01 14:50:12 +0000691 help
692 This option enables additional CAR related debug messages.
Peter Stuge5015f792010-11-10 02:00:32 +0000693endif
Patrick Georgie82618d2010-10-01 14:50:12 +0000694
Myles Watson80e914ff2010-06-01 19:25:31 +0000695config DEBUG_PIRQ
696 bool "Check PIRQ table consistency"
697 default n
698 depends on GENERATE_PIRQ_TABLE
699 help
700 If unsure, say N.
701
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000702config HAVE_DEBUG_SMBUS
703 def_bool n
704
Uwe Hermann01ce6012010-03-05 10:03:50 +0000705config DEBUG_SMBUS
706 bool "Output verbose SMBus debug messages"
707 default n
Jens Rottmann0d11f2d2010-08-26 12:46:02 +0000708 depends on HAVE_DEBUG_SMBUS
Uwe Hermann01ce6012010-03-05 10:03:50 +0000709 help
710 This option enables additional SMBus (and SPD) debug messages.
711
712 Note: This option will increase the size of the coreboot image.
713
714 If unsure, say N.
715
716config DEBUG_SMI
717 bool "Output verbose SMI debug messages"
718 default n
719 depends on HAVE_SMI_HANDLER
Martin Roth3a543182015-09-28 15:27:24 -0600720 select SPI_FLASH_SMM if SPI_CONSOLE
Uwe Hermann01ce6012010-03-05 10:03:50 +0000721 help
722 This option enables additional SMI related debug messages.
723
724 Note: This option will increase the size of the coreboot image.
725
726 If unsure, say N.
727
Stefan Reinauerbc0f7a62010-08-01 15:41:14 +0000728config DEBUG_SMM_RELOCATION
729 bool "Debug SMM relocation code"
730 default n
731 depends on HAVE_SMI_HANDLER
732 help
733 This option enables additional SMM handler relocation related
734 debug messages.
735
736 Note: This option will increase the size of the coreboot image.
737
738 If unsure, say N.
739
Uwe Hermanna953f372010-11-10 00:14:32 +0000740# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
741# printk(BIOS_DEBUG, ...) calls.
742config DEBUG_MALLOC
Stefan Reinauer95a63962012-11-13 17:00:01 -0800743 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
744 bool
Uwe Hermanna953f372010-11-10 00:14:32 +0000745 default n
Uwe Hermanna953f372010-11-10 00:14:32 +0000746 help
747 This option enables additional malloc related debug messages.
748
749 Note: This option will increase the size of the coreboot image.
750
751 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300752
753# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
754# printk(BIOS_DEBUG, ...) calls.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300755config DEBUG_ACPI
Stefan Reinauer95a63962012-11-13 17:00:01 -0800756 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
757 bool
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300758 default n
759 help
760 This option enables additional ACPI related debug messages.
761
762 Note: This option will slightly increase the size of the coreboot image.
763
764 If unsure, say N.
Cristian Măgherușan-Stanciu9f52ea42011-07-02 00:44:39 +0300765
Uwe Hermanna953f372010-11-10 00:14:32 +0000766# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
767# printk(BIOS_DEBUG, ...) calls.
Myles Watson6c9bc012010-09-07 22:30:15 +0000768config REALMODE_DEBUG
Stefan Reinauer95a63962012-11-13 17:00:01 -0800769 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
770 bool
Myles Watson6c9bc012010-09-07 22:30:15 +0000771 default n
Peter Stuge5015f792010-11-10 02:00:32 +0000772 depends on PCI_OPTION_ROM_RUN_REALMODE
Myles Watson6c9bc012010-09-07 22:30:15 +0000773 help
774 This option enables additional x86emu related debug messages.
775
776 Note: This option will increase the time to emulate a ROM.
777
778 If unsure, say N.
779
Uwe Hermann01ce6012010-03-05 10:03:50 +0000780config X86EMU_DEBUG
781 bool "Output verbose x86emu debug messages"
782 default n
783 depends on PCI_OPTION_ROM_RUN_YABEL
784 help
785 This option enables additional x86emu related debug messages.
786
787 Note: This option will increase the size of the coreboot image.
788
789 If unsure, say N.
790
791config X86EMU_DEBUG_JMP
792 bool "Trace JMP/RETF"
793 default n
794 depends on X86EMU_DEBUG
795 help
796 Print information about JMP and RETF opcodes from x86emu.
797
798 Note: This option will increase the size of the coreboot image.
799
800 If unsure, say N.
801
802config X86EMU_DEBUG_TRACE
803 bool "Trace all opcodes"
804 default n
805 depends on X86EMU_DEBUG
806 help
807 Print _all_ opcodes that are executed by x86emu.
Stefan Reinauer14e22772010-04-27 06:56:47 +0000808
Uwe Hermann01ce6012010-03-05 10:03:50 +0000809 WARNING: This will produce a LOT of output and take a long time.
810
811 Note: This option will increase the size of the coreboot image.
812
813 If unsure, say N.
814
815config X86EMU_DEBUG_PNP
816 bool "Log Plug&Play accesses"
817 default n
818 depends on X86EMU_DEBUG
819 help
820 Print Plug And Play accesses made by option ROMs.
821
822 Note: This option will increase the size of the coreboot image.
823
824 If unsure, say N.
825
826config X86EMU_DEBUG_DISK
827 bool "Log Disk I/O"
828 default n
829 depends on X86EMU_DEBUG
830 help
831 Print Disk I/O related messages.
832
833 Note: This option will increase the size of the coreboot image.
834
835 If unsure, say N.
836
837config X86EMU_DEBUG_PMM
838 bool "Log PMM"
839 default n
840 depends on X86EMU_DEBUG
841 help
842 Print messages related to POST Memory Manager (PMM).
843
844 Note: This option will increase the size of the coreboot image.
845
846 If unsure, say N.
847
848
849config X86EMU_DEBUG_VBE
850 bool "Debug VESA BIOS Extensions"
851 default n
852 depends on X86EMU_DEBUG
853 help
854 Print messages related to VESA BIOS Extension (VBE) functions.
855
856 Note: This option will increase the size of the coreboot image.
857
858 If unsure, say N.
859
860config X86EMU_DEBUG_INT10
861 bool "Redirect INT10 output to console"
862 default n
863 depends on X86EMU_DEBUG
864 help
865 Let INT10 (i.e. character output) calls print messages to debug output.
866
867 Note: This option will increase the size of the coreboot image.
868
869 If unsure, say N.
870
871config X86EMU_DEBUG_INTERRUPTS
872 bool "Log intXX calls"
873 default n
874 depends on X86EMU_DEBUG
875 help
876 Print messages related to interrupt handling.
877
878 Note: This option will increase the size of the coreboot image.
879
880 If unsure, say N.
881
882config X86EMU_DEBUG_CHECK_VMEM_ACCESS
883 bool "Log special memory accesses"
884 default n
885 depends on X86EMU_DEBUG
886 help
887 Print messages related to accesses to certain areas of the virtual
888 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
889
890 Note: This option will increase the size of the coreboot image.
891
892 If unsure, say N.
893
894config X86EMU_DEBUG_MEM
895 bool "Log all memory accesses"
896 default n
897 depends on X86EMU_DEBUG
898 help
899 Print memory accesses made by option ROM.
900 Note: This also includes accesses to fetch instructions.
901
902 Note: This option will increase the size of the coreboot image.
903
904 If unsure, say N.
905
906config X86EMU_DEBUG_IO
907 bool "Log IO accesses"
908 default n
909 depends on X86EMU_DEBUG
910 help
911 Print I/O accesses made by option ROM.
912
913 Note: This option will increase the size of the coreboot image.
914
915 If unsure, say N.
916
Denis 'GNUtoo' Carikli4cdc5d62013-05-15 00:19:49 +0200917config X86EMU_DEBUG_TIMINGS
918 bool "Output timing information"
919 default n
920 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
921 help
922 Print timing information needed by i915tool.
923
924 If unsure, say N.
925
Stefan Reinauer1c56d9b2012-05-10 11:27:32 -0700926config DEBUG_SPI_FLASH
927 bool "Output verbose SPI flash debug messages"
928 default n
929 depends on SPI_FLASH
930 help
931 This option enables additional SPI flash related debug messages.
932
Kyösti Mälkki3be80cc2013-06-06 10:46:37 +0300933config DEBUG_USBDEBUG
934 bool "Output verbose USB 2.0 EHCI debug dongle messages"
935 default n
936 depends on USBDEBUG
937 help
938 This option enables additional USB 2.0 debug dongle related messages.
939
940 Select this to debug the connection of usbdebug dongle. Note that
941 you need some other working console to receive the messages.
942
Stefan Reinauer8e073822012-04-04 00:07:22 +0200943if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
944# Only visible with the right southbridge and loglevel.
945config DEBUG_INTEL_ME
946 bool "Verbose logging for Intel Management Engine"
947 default n
948 help
949 Enable verbose logging for Intel Management Engine driver that
950 is present on Intel 6-series chipsets.
951endif
952
Rudolf Marek7f0e9302011-09-02 23:23:41 +0200953config TRACE
954 bool "Trace function calls"
955 default n
956 help
957 If enabled, every function will print information to console once
958 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
959 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
Ben Gardner8420ad42015-11-18 10:46:53 -0600960 of calling function. Please note some printk related functions
Rudolf Marek7f0e9302011-09-02 23:23:41 +0200961 are omitted from trace to have good looking console dumps.
Stefan Reinauerd37ab452012-12-18 16:23:28 -0800962
963config DEBUG_COVERAGE
964 bool "Debug code coverage"
965 default n
966 depends on COVERAGE
967 help
968 If enabled, the code coverage hooks in coreboot will output some
969 information about the coverage data that is dumped.
970
Jonathan Neuschäferfc04f9b2016-06-29 21:59:32 +0200971config DEBUG_BOOT_STATE
972 bool "Debug boot state machine"
973 default n
974 help
975 Control debugging of the boot state machine. When selected displays
976 the state boundaries in ramstage.
977
Jonathan Neuschäfer538e4462016-08-22 19:37:15 +0200978config DEBUG_PRINT_PAGE_TABLES
979 bool "Print the page tables after construction"
980 default n
981 depends on ARCH_RISCV
982 help
983 After the page tables have been built, print them on the debug
984 console.
985
Nico Hubere84e62542016-10-05 17:43:56 +0200986config DEBUG_ADA_CODE
987 bool "Compile debug code in Ada sources"
988 default n
989 help
990 Add the compiler switch `-gnata` to compile code guarded by
991 `pragma Debug`.
992
Uwe Hermann168b11b2009-10-07 16:15:40 +0000993endmenu
994
Martin Roth8e4aafb2016-12-15 15:25:15 -0700995
996###############################################################################
997# Set variables with no prompt - these can be set anywhere, and putting at
998# the end of this file gives the most flexibility.
Nico Huber3db76532017-05-18 18:07:34 +0200999
1000source "src/lib/Kconfig"
1001
Myles Watsond73c1b52009-10-26 15:14:07 +00001002config ENABLE_APIC_EXT_ID
1003 bool
1004 default n
Myles Watson2e672732009-11-12 16:38:03 +00001005
1006config WARNINGS_ARE_ERRORS
1007 bool
Edward O'Callaghan63f6dc72014-11-18 03:17:54 +11001008 default y
Patrick Georgi436f99b2009-11-27 16:55:13 +00001009
Peter Stuge51eafde2010-10-13 06:23:02 +00001010# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1011# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1012# mutually exclusive. One of these options must be selected in the
1013# mainboard Kconfig if the chipset supports enabling and disabling of
1014# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1015# in mainboard/Kconfig to know if the button should be enabled or not.
1016
1017config POWER_BUTTON_DEFAULT_ENABLE
1018 def_bool n
1019 help
1020 Select when the board has a power button which can optionally be
1021 disabled by the user.
1022
1023config POWER_BUTTON_DEFAULT_DISABLE
1024 def_bool n
1025 help
1026 Select when the board has a power button which can optionally be
1027 enabled by the user, e.g. when the board ships with a jumper over
1028 the power switch contacts.
1029
1030config POWER_BUTTON_FORCE_ENABLE
1031 def_bool n
1032 help
1033 Select when the board requires that the power button is always
1034 enabled.
1035
1036config POWER_BUTTON_FORCE_DISABLE
1037 def_bool n
1038 help
1039 Select when the board requires that the power button is always
1040 disabled, e.g. when it has been hardwired to ground.
1041
1042config POWER_BUTTON_IS_OPTIONAL
1043 bool
1044 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1045 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1046 help
1047 Internal option that controls ENABLE_POWER_BUTTON visibility.
Duncan Laurie72748002013-10-31 08:26:23 -07001048
1049config REG_SCRIPT
1050 bool
Duncan Laurie72748002013-10-31 08:26:23 -07001051 default n
1052 help
1053 Internal option that controls whether we compile in register scripts.
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001054
Furquan Shaikh99ac98f2014-04-23 10:18:48 -07001055config MAX_REBOOT_CNT
1056 int
1057 default 3
Timothy Pearson17ada2e2015-03-18 01:31:34 -05001058 help
1059 Internal option that sets the maximum number of bootblock executions allowed
1060 with the normal image enabled before assuming the normal image is defective
Vadim Bendebury9c9c3362014-07-23 09:40:02 -07001061 and switching to the fallback image.
Martin Roth59ff3402016-02-09 09:06:46 -07001062
Lee Leahyfc3741f2016-05-26 17:12:17 -07001063config CREATE_BOARD_CHECKLIST
1064 bool
1065 default n
1066 help
1067 When selected, creates a webpage showing the implementation status for
1068 the board. Routines highlighted in green are complete, yellow are
1069 optional and red are required and must be implemented. A table is
1070 produced for each stage of the boot process except the bootblock. The
1071 red items may be used as an implementation checklist for the board.
1072
1073config MAKE_CHECKLIST_PUBLIC
1074 bool
1075 default n
1076 help
1077 When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
1078 is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
1079 directory.
1080
1081config CHECKLIST_DATA_FILE_LOCATION
1082 string
1083 help
1084 Location of the <stage>_complete.dat and <stage>_optional.dat files
1085 that are consumed during checklist processing. <stage>_complete.dat
1086 contains the symbols that are expected to be in the resulting image.
1087 <stage>_optional.dat is a subset of <stage>_complete.dat and contains
1088 a list of weak symbols which the resulting image may consume. Other
1089 symbols contained only in <stage>_complete.dat will be flagged as
1090 required and not implemented if a weak implementation is found in the
1091 resulting image.
Nico Hubere0ed9022016-10-07 12:58:17 +02001092
Martin Roth8e4aafb2016-12-15 15:25:15 -07001093config UNCOMPRESSED_RAMSTAGE
1094 bool
1095
1096config NO_XIP_EARLY_STAGES
1097 bool
1098 default n if ARCH_X86
1099 default y
1100 help
1101 Identify if early stages are eXecute-In-Place(XIP).
1102
1103config EARLY_CBMEM_INIT
1104 def_bool !LATE_CBMEM_INIT
1105
1106config EARLY_CBMEM_LIST
1107 bool
1108 default n
1109 help
1110 Enable display of CBMEM during romstage and postcar.
1111
1112config RELOCATABLE_MODULES
1113 bool
1114 help
1115 If RELOCATABLE_MODULES is selected then support is enabled for
1116 building relocatable modules in the RAM stage. Those modules can be
1117 loaded anywhere and all the relocations are handled automatically.
1118
1119config NO_STAGE_CACHE
1120 bool
1121 help
1122 Do not save any component in stage cache for resume path. On resume,
1123 all components would be read back from CBFS again.
1124
1125config GENERIC_GPIO_LIB
1126 bool
1127 help
1128 If enabled, compile the generic GPIO library. A "generic" GPIO
1129 implies configurability usually found on SoCs, particularly the
1130 ability to control internal pull resistors.
1131
1132config GENERIC_SPD_BIN
1133 bool
1134 help
1135 If enabled, add support for adding spd.hex files in cbfs as spd.bin
1136 and locating it runtime to load SPD. Additionally provide provision to
1137 fetch SPD over SMBus.
1138
1139config DIMM_MAX
1140 int
1141 default 4
1142 depends on GENERIC_SPD_BIN
1143 help
1144 Total number of memory DIMM slots available on motherboard.
1145 It is multiplication of number of channel to number of DIMMs per
1146 channel
1147
1148config DIMM_SPD_SIZE
1149 int
1150 default 256
Martin Roth8e4aafb2016-12-15 15:25:15 -07001151 help
1152 Total SPD size that will be used for DIMM.
1153 Ex: DDR3 256, DDR4 512.
1154
Kane Chen66f1f382017-10-16 19:40:18 +08001155config SPD_READ_BY_WORD
1156 bool
1157
Martin Roth8e4aafb2016-12-15 15:25:15 -07001158config BOOTBLOCK_CUSTOM
1159 # To be selected by arch, SoC or mainboard if it does not want use the normal
1160 # src/lib/bootblock.c#main() C entry point.
1161 bool
1162
1163config C_ENVIRONMENT_BOOTBLOCK
1164 # To be selected by arch or platform if a C environment is available during the
1165 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
1166 bool
1167
Martin Roth75e5cb72016-12-15 15:05:37 -07001168###############################################################################
1169# Set default values for symbols created before mainboards. This allows the
1170# option to be displayed in the general menu, but the default to be loaded in
1171# the mainboard if desired.
1172config COMPRESS_RAMSTAGE
1173 default y if !UNCOMPRESSED_RAMSTAGE
1174
1175config COMPRESS_PRERAM_STAGES
1176 depends on !ARCH_X86
1177 default y
1178
1179config INCLUDE_CONFIG_FILE
1180 default y
1181
Martin Roth75e5cb72016-12-15 15:05:37 -07001182config BOOTSPLASH_FILE
1183 depends on BOOTSPLASH_IMAGE
1184 default "bootsplash.jpg"
1185
1186config CBFS_SIZE
1187 default ROM_SIZE