Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Arastra, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | * |
| 19 | */ |
| 20 | |
| 21 | #define ASSEMBLY 1 |
| 22 | #include <stdint.h> |
| 23 | #include <stdlib.h> |
| 24 | #include <device/pci_def.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <device/pnp_def.h> |
| 28 | #include <arch/romcc_io.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include "pc80/mc146818rtc_early.c" |
| 31 | #include "pc80/serial.c" |
| 32 | #include "arch/i386/lib/console.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame^] | 33 | #include "lib/ramtest.c" |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 34 | #include "southbridge/intel/i3100/i3100_early_smbus.c" |
| 35 | #include "southbridge/intel/i3100/i3100_early_lpc.c" |
| 36 | #include "northbridge/intel/i3100/raminit.h" |
| 37 | #include "superio/intel/i3100/i3100.h" |
| 38 | #include "cpu/x86/lapic/boot_cpu.c" |
| 39 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 40 | #include "superio/intel/i3100/i3100_early_serial.c" |
| 41 | #include "northbridge/intel/i3100/memory_initialized.c" |
| 42 | #include "cpu/x86/bist.h" |
| 43 | |
| 44 | #define SIO_GPIO_BASE 0x680 |
| 45 | #define SIO_XBUS_BASE 0x4880 |
| 46 | |
| 47 | #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) |
| 48 | #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) |
| 49 | |
| 50 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 51 | { |
| 52 | /* nothing to do */ |
| 53 | } |
| 54 | static inline int spd_read_byte(u16 device, u8 address) |
| 55 | { |
| 56 | return smbus_read_byte(device, address); |
| 57 | } |
| 58 | |
| 59 | #include "northbridge/intel/i3100/raminit.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame^] | 60 | #include "lib/generic_sdram.c" |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 61 | #include "../jarrell/debug.c" |
| 62 | |
| 63 | |
| 64 | static void main(unsigned long bist) |
| 65 | { |
| 66 | msr_t msr; |
| 67 | u16 perf; |
| 68 | static const struct mem_controller mch[] = { |
| 69 | { |
| 70 | .node_id = 0, |
| 71 | .f0 = PCI_DEV(0, 0x00, 0), |
| 72 | .f1 = PCI_DEV(0, 0x00, 1), |
| 73 | .f2 = PCI_DEV(0, 0x00, 2), |
| 74 | .f3 = PCI_DEV(0, 0x00, 3), |
| 75 | .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 }, |
| 76 | .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 }, |
| 77 | } |
| 78 | }; |
| 79 | |
| 80 | if (bist == 0) { |
| 81 | /* Skip this if there was a built in self test failure */ |
| 82 | early_mtrr_init(); |
| 83 | if (memory_initialized()) { |
| 84 | asm volatile ("jmp __cpu_reset"); |
| 85 | } |
| 86 | } |
| 87 | /* Set up the console */ |
| 88 | i3100_enable_superio(); |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 89 | i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE); |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 90 | uart_init(); |
| 91 | console_init(); |
| 92 | |
Ed Swierk | 71f846c | 2008-03-30 11:31:15 +0000 | [diff] [blame] | 93 | /* Prevent the TCO timer from rebooting us */ |
| 94 | i3100_halt_tco_timer(); |
| 95 | |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 96 | /* Halt if there was a built in self test failure */ |
| 97 | report_bist_failure(bist); |
| 98 | |
| 99 | /* print_pci_devices(); */ |
| 100 | enable_smbus(); |
| 101 | /* dump_spd_registers(); */ |
| 102 | |
| 103 | /* Enable SpeedStep and automatic thermal throttling */ |
| 104 | /* FIXME: move to Pentium M init code */ |
| 105 | msr = rdmsr(0x1a0); |
| 106 | msr.lo |= (1 << 3) | (1 << 16); |
| 107 | wrmsr(0x1a0, msr); |
| 108 | msr = rdmsr(0x19d); |
| 109 | msr.lo |= (1 << 16); |
| 110 | wrmsr(0x19d, msr); |
| 111 | |
| 112 | /* Set CPU frequency/voltage to maximum */ |
| 113 | /* FIXME: move to Pentium M init code */ |
| 114 | msr = rdmsr(0x198); |
| 115 | perf = msr.hi & 0xffff; |
| 116 | msr = rdmsr(0x199); |
| 117 | msr.lo &= 0xffff0000; |
| 118 | msr.lo |= perf; |
| 119 | wrmsr(0x199, msr); |
| 120 | |
| 121 | sdram_initialize(ARRAY_SIZE(mch), mch); |
| 122 | /* dump_pci_devices(); */ |
| 123 | /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */ |
| 124 | /* dump_bar14(PCI_DEV(0, 0x00, 0)); */ |
| 125 | |
| 126 | ram_check(0, 1024 * 1024); |
| 127 | } |