Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 2 | |
| 3 | #include <arch/ioapic.h> |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 4 | #include <assert.h> |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <cpu/x86/lapic.h> |
| 7 | #include <device/pci.h> |
| 8 | #include <fsp/api.h> |
Andrey Petrov | 4e48ac0 | 2020-04-30 14:08:19 -0700 | [diff] [blame] | 9 | #include <intelblocks/p2sb.h> |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 10 | #include <post.h> |
Jonathan Zhang | 3172f98 | 2020-05-28 17:53:48 -0700 | [diff] [blame] | 11 | #include <soc/acpi.h> |
Andrey Petrov | 8670e82 | 2020-03-30 12:25:06 -0700 | [diff] [blame] | 12 | #include <soc/cpu.h> |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 13 | #include <soc/ramstage.h> |
| 14 | #include <soc/pm.h> |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 15 | #include <soc/soc_util.h> |
| 16 | #include <stdlib.h> |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 17 | |
| 18 | /* C620 IOAPIC has 120 redirection entries */ |
| 19 | #define C620_IOAPIC_REDIR_ENTRIES 120 |
| 20 | |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 21 | struct pci_resource { |
| 22 | struct device *dev; |
| 23 | struct resource *res; |
| 24 | struct pci_resource *next; |
| 25 | }; |
| 26 | |
| 27 | struct stack_dev_resource { |
| 28 | uint8_t align; |
| 29 | struct pci_resource *children; |
| 30 | struct stack_dev_resource *next; |
| 31 | }; |
| 32 | |
| 33 | typedef enum { |
| 34 | RES_TYPE_IO = 0, |
| 35 | RES_TYPE_NONPREF_MEM, |
| 36 | RES_TYPE_PREF_MEM, |
| 37 | MAX_RES_TYPES |
| 38 | } ResType; |
| 39 | |
| 40 | static ResType get_res_type(uint64_t flags) |
| 41 | { |
| 42 | if (flags & IORESOURCE_IO) |
| 43 | return RES_TYPE_IO; |
| 44 | if (flags & IORESOURCE_MEM) { |
| 45 | if (flags & IORESOURCE_PREFETCH) { |
| 46 | printk(BIOS_DEBUG, "%s:%d flags: 0x%llx\n", __func__, __LINE__, flags); |
| 47 | return RES_TYPE_PREF_MEM; |
| 48 | } |
| 49 | /* both 64-bit and 32-bit use below 4GB address space */ |
| 50 | return RES_TYPE_NONPREF_MEM; |
| 51 | } |
| 52 | printk(BIOS_ERR, "Invalid resource type 0x%llx\n", flags); |
| 53 | die("Invalida resource type"); |
| 54 | } |
| 55 | |
| 56 | static bool need_assignment(uint64_t flags) |
| 57 | { |
| 58 | if (flags & (IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_FIXED | |
| 59 | IORESOURCE_ASSIGNED)) |
| 60 | return false; |
| 61 | else |
| 62 | return true; |
| 63 | } |
| 64 | |
| 65 | static uint64_t get_resource_base(STACK_RES *stack, ResType res_type) |
| 66 | { |
| 67 | if (res_type == RES_TYPE_IO) { |
| 68 | assert(stack->PciResourceIoBase <= stack->PciResourceIoLimit); |
| 69 | return stack->PciResourceIoBase; |
| 70 | } |
| 71 | if (res_type == RES_TYPE_NONPREF_MEM) { |
| 72 | assert(stack->PciResourceMem32Base <= stack->PciResourceMem32Limit); |
| 73 | return stack->PciResourceMem32Base; |
| 74 | } |
| 75 | assert(stack->PciResourceMem64Base <= stack->PciResourceMem64Limit); |
| 76 | return stack->PciResourceMem64Base; |
| 77 | } |
| 78 | |
| 79 | static void set_resource_base(STACK_RES *stack, ResType res_type, uint64_t base) |
| 80 | { |
| 81 | if (res_type == RES_TYPE_IO) { |
| 82 | assert(base <= (stack->PciResourceIoLimit + 1)); |
| 83 | stack->PciResourceIoBase = base; |
| 84 | } else if (res_type == RES_TYPE_NONPREF_MEM) { |
| 85 | assert(base <= (stack->PciResourceMem32Limit + 1)); |
| 86 | stack->PciResourceMem32Base = base; |
| 87 | } else { |
| 88 | assert(base <= (stack->PciResourceMem64Limit + 1)); |
| 89 | stack->PciResourceMem64Base = base; |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | static void assign_stack_resources(struct iiostack_resource *stack_list, |
| 94 | struct device *dev, struct resource *bridge); |
| 95 | |
| 96 | static void xeonsp_cpx_pci_domain_scan_bus(struct device *dev) |
| 97 | { |
| 98 | DEV_FUNC_ENTER(dev); |
| 99 | struct bus *link = dev->link_list; |
| 100 | |
| 101 | printk(BIOS_SPEW, "%s:%s scanning buses under device %s\n", |
| 102 | __FILE__, __func__, dev_path(dev)); |
| 103 | while (link != NULL) { |
| 104 | if (link->secondary == 0) { // scan only PSTACK buses |
| 105 | struct device *d; |
| 106 | for (d = link->children; d; d = d->sibling) |
| 107 | pci_probe_dev(d, link, d->path.pci.devfn); |
| 108 | scan_bridges(link); |
| 109 | } else { |
| 110 | pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); |
| 111 | } |
| 112 | link = link->next; |
| 113 | } |
| 114 | DEV_FUNC_EXIT(dev); |
| 115 | } |
| 116 | |
| 117 | static void xeonsp_pci_dev_iterator(struct bus *bus, |
| 118 | void (*dev_iterator)(struct device *, void *), |
| 119 | void (*res_iterator)(struct device *, struct resource *, void *), |
| 120 | void *data) |
| 121 | { |
| 122 | struct device *curdev; |
| 123 | struct resource *res; |
| 124 | |
| 125 | /* Walk through all devices and find which resources they need. */ |
| 126 | for (curdev = bus->children; curdev; curdev = curdev->sibling) { |
| 127 | struct bus *link; |
| 128 | |
| 129 | if (!curdev->enabled) |
| 130 | continue; |
| 131 | |
| 132 | if (!curdev->ops || !curdev->ops->read_resources) { |
| 133 | if (curdev->path.type != DEVICE_PATH_APIC) |
| 134 | printk(BIOS_ERR, "%s missing read_resources\n", |
| 135 | dev_path(curdev)); |
| 136 | continue; |
| 137 | } |
| 138 | |
| 139 | if (dev_iterator) |
| 140 | dev_iterator(curdev, data); |
| 141 | |
| 142 | if (res_iterator) { |
| 143 | for (res = curdev->resource_list; res; res = res->next) |
| 144 | res_iterator(curdev, res, data); |
| 145 | } |
| 146 | |
| 147 | /* Read in the resources behind the current device's links. */ |
| 148 | for (link = curdev->link_list; link; link = link->next) |
| 149 | xeonsp_pci_dev_iterator(link, dev_iterator, res_iterator, data); |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | static void xeonsp_pci_dev_read_resources(struct device *dev, void *data) |
| 154 | { |
| 155 | post_log_path(dev); |
| 156 | dev->ops->read_resources(dev); |
| 157 | } |
| 158 | |
| 159 | static void xeonsp_pci_dev_dummy_func(struct device *dev) |
| 160 | { |
| 161 | } |
| 162 | |
| 163 | static void xeonsp_reset_pci_op(struct device *dev, void *data) |
| 164 | { |
| 165 | if (dev->ops) |
| 166 | dev->ops->read_resources = xeonsp_pci_dev_dummy_func; |
| 167 | } |
| 168 | |
| 169 | static STACK_RES *find_stack_for_bus(struct iiostack_resource *info, uint8_t bus) |
| 170 | { |
| 171 | for (int i = 0; i < info->no_of_stacks; ++i) { |
| 172 | if (bus >= info->res[i].BusBase && bus <= info->res[i].BusLimit) |
| 173 | return &info->res[i]; |
| 174 | } |
| 175 | return NULL; |
| 176 | } |
| 177 | |
| 178 | static void add_res_to_stack(struct stack_dev_resource **root, |
| 179 | struct device *dev, struct resource *res) |
| 180 | { |
| 181 | struct stack_dev_resource *cur = *root; |
| 182 | while (cur) { |
| 183 | if (cur->align == res->align || cur->next == NULL) /* equal or last record */ |
| 184 | break; |
| 185 | else if (cur->align > res->align) { |
| 186 | if (cur->next->align < res->align) /* need to insert new record here */ |
| 187 | break; |
| 188 | cur = cur->next; |
| 189 | } else { |
| 190 | break; |
| 191 | } |
| 192 | } |
| 193 | |
| 194 | struct stack_dev_resource *nr; |
| 195 | if (!cur || cur->align != res->align) { /* need to add new record */ |
| 196 | nr = malloc(sizeof(struct stack_dev_resource)); |
| 197 | if (nr == 0) |
| 198 | die("assign_resource_to_stack(): out of memory.\n"); |
| 199 | memset(nr, 0, sizeof(struct stack_dev_resource)); |
| 200 | nr->align = res->align; |
| 201 | if (!cur) { |
| 202 | *root = nr; /* head node */ |
| 203 | } else if (cur->align > nr->align) { |
| 204 | if (cur->next == NULL) { |
| 205 | cur->next = nr; |
| 206 | } else { |
| 207 | nr->next = cur->next; |
| 208 | cur->next = nr; |
| 209 | } |
| 210 | } else { /* insert in the beginning */ |
| 211 | nr->next = cur; |
| 212 | *root = nr; |
| 213 | } |
| 214 | } else { |
| 215 | nr = cur; |
| 216 | } |
| 217 | |
| 218 | assert(nr != NULL && nr->align == res->align); |
| 219 | |
| 220 | struct pci_resource *npr = malloc(sizeof(struct pci_resource)); |
| 221 | if (npr == NULL) |
| 222 | die("%s: out of memory.\n", __func__); |
| 223 | npr->res = res; |
| 224 | npr->dev = dev; |
| 225 | npr->next = NULL; |
| 226 | |
| 227 | if (nr->children == NULL) { |
| 228 | nr->children = npr; |
| 229 | } else { |
| 230 | struct pci_resource *pr = nr->children; |
| 231 | while (pr->next != NULL) |
| 232 | pr = pr->next; |
| 233 | pr->next = npr; |
| 234 | } |
| 235 | } |
| 236 | |
| 237 | static void reserve_dev_resources(STACK_RES *stack, ResType res_type, |
| 238 | struct stack_dev_resource *res_root, struct resource *bridge) |
| 239 | { |
| 240 | uint8_t align; |
| 241 | uint64_t orig_base, base; |
| 242 | |
| 243 | orig_base = get_resource_base(stack, res_type); |
| 244 | |
| 245 | align = 0; |
| 246 | base = orig_base; |
| 247 | int first = 1; |
| 248 | while (res_root) { /* loop through all devices grouped by alignment requirements */ |
| 249 | struct pci_resource *pr = res_root->children; |
| 250 | while (pr) { |
| 251 | if (first) { |
| 252 | if (bridge) { /* takes highest alignment */ |
| 253 | if (bridge->align < pr->res->align) |
| 254 | bridge->align = pr->res->align; |
| 255 | orig_base = ALIGN_UP(orig_base, 1 << bridge->align); |
| 256 | } else { |
| 257 | orig_base = ALIGN_UP(orig_base, 1 << pr->res->align); |
| 258 | } |
| 259 | base = orig_base; |
| 260 | |
| 261 | if (bridge) |
| 262 | bridge->base = base; |
| 263 | pr->res->base = base; |
| 264 | first = 0; |
| 265 | } else { |
| 266 | pr->res->base = ALIGN_UP(base, 1 << pr->res->align); |
| 267 | } |
| 268 | pr->res->limit = pr->res->base + pr->res->size - 1; |
| 269 | base = pr->res->limit + 1; |
| 270 | pr->res->flags |= (IORESOURCE_ASSIGNED); |
| 271 | pr = pr->next; |
| 272 | } |
| 273 | res_root = res_root->next; |
| 274 | } |
| 275 | |
| 276 | if (bridge) { |
| 277 | /* this bridge doesn't have any resources, will set it to default window */ |
| 278 | if (first) { |
| 279 | orig_base = ALIGN_UP(orig_base, 1 << bridge->align); |
| 280 | bridge->base = orig_base; |
| 281 | base = orig_base + (1ULL << bridge->gran); |
| 282 | } |
| 283 | |
| 284 | bridge->size = ALIGN_UP(base, 1 << bridge->align) - bridge->base; |
| 285 | |
| 286 | bridge->limit = bridge->base + bridge->size - 1; |
| 287 | bridge->flags |= (IORESOURCE_ASSIGNED); |
| 288 | base = bridge->limit + 1; |
| 289 | } |
| 290 | |
| 291 | set_resource_base(stack, res_type, base); |
| 292 | } |
| 293 | |
| 294 | static void reclaim_resource_mem(struct stack_dev_resource *res_root) |
| 295 | { |
| 296 | while (res_root) { /* loop through all devices grouped by alignment requirements */ |
| 297 | /* free pci_resource */ |
| 298 | struct pci_resource *pr = res_root->children; |
| 299 | while (pr) { |
| 300 | struct pci_resource *dpr = pr; |
| 301 | pr = pr->next; |
| 302 | free(dpr); |
| 303 | } |
| 304 | |
| 305 | /* free stack_dev_resource */ |
| 306 | struct stack_dev_resource *ddr = res_root; |
| 307 | res_root = res_root->next; |
| 308 | free(ddr); |
| 309 | } |
| 310 | } |
| 311 | |
| 312 | static void assign_bridge_resources(struct iiostack_resource *stack_list, |
| 313 | struct device *dev, struct resource *bridge) |
| 314 | { |
| 315 | struct resource *res; |
| 316 | if (!dev->enabled) |
| 317 | return; |
| 318 | |
| 319 | for (res = dev->resource_list; res; res = res->next) { |
| 320 | if (!(res->flags & IORESOURCE_BRIDGE) || |
| 321 | (bridge && (get_res_type(bridge->flags) != get_res_type(res->flags)))) |
| 322 | continue; |
| 323 | |
| 324 | assign_stack_resources(stack_list, dev, res); |
| 325 | |
| 326 | if (!bridge) |
| 327 | continue; |
| 328 | |
| 329 | /* for 1st time update, overlading IORESOURCE_ASSIGNED */ |
| 330 | if (!(bridge->flags & IORESOURCE_ASSIGNED)) { |
| 331 | bridge->base = res->base; |
| 332 | bridge->limit = res->limit; |
| 333 | bridge->flags |= (IORESOURCE_ASSIGNED); |
| 334 | } else { |
| 335 | /* update bridge range from child bridge range */ |
| 336 | if (res->base < bridge->base) |
| 337 | bridge->base = res->base; |
| 338 | if (res->limit > bridge->limit) |
| 339 | bridge->limit = res->limit; |
| 340 | } |
| 341 | bridge->size = (bridge->limit - bridge->base + 1); |
| 342 | } |
| 343 | } |
| 344 | |
| 345 | static void assign_stack_resources(struct iiostack_resource *stack_list, |
| 346 | struct device *dev, struct resource *bridge) |
| 347 | { |
| 348 | struct bus *bus; |
| 349 | |
| 350 | /* Read in the resources behind the current device's links. */ |
| 351 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 352 | struct device *curdev; |
| 353 | STACK_RES *stack; |
| 354 | |
| 355 | /* get IIO stack for this bus */ |
| 356 | stack = find_stack_for_bus(stack_list, bus->secondary); |
| 357 | assert(stack != NULL); |
| 358 | |
| 359 | /* Assign resources to bridge */ |
| 360 | for (curdev = bus->children; curdev; curdev = curdev->sibling) |
| 361 | assign_bridge_resources(stack_list, curdev, bridge); |
| 362 | |
| 363 | /* Pick non-bridged resources for resource allocation for each resource type */ |
| 364 | ResType res_types[MAX_RES_TYPES] = { |
| 365 | RES_TYPE_IO, |
| 366 | RES_TYPE_NONPREF_MEM, |
| 367 | RES_TYPE_PREF_MEM |
| 368 | }; |
| 369 | |
| 370 | uint8_t no_res_types = MAX_RES_TYPES; |
| 371 | |
| 372 | /* if it is a bridge, only process matching brigge resource type */ |
| 373 | if (bridge) { |
| 374 | res_types[0] = get_res_type(bridge->flags); |
| 375 | no_res_types = 1; |
| 376 | } |
| 377 | |
| 378 | printk(BIOS_DEBUG, "%s:%d no_res_types: %d\n", __func__, __LINE__, |
| 379 | no_res_types); |
| 380 | |
| 381 | /* Process each resource type */ |
| 382 | for (int rt = 0; rt < no_res_types; ++rt) { |
| 383 | struct stack_dev_resource *res_root = NULL; |
| 384 | printk(BIOS_DEBUG, "%s:%d rt: %d\n", __func__, __LINE__, rt); |
| 385 | for (curdev = bus->children; curdev; curdev = curdev->sibling) { |
| 386 | struct resource *res; |
| 387 | printk(BIOS_DEBUG, "%s:%d dev: %s\n", |
| 388 | __func__, __LINE__, dev_path(curdev)); |
| 389 | if (!curdev->enabled) |
| 390 | continue; |
| 391 | |
| 392 | for (res = curdev->resource_list; res; res = res->next) { |
| 393 | printk(BIOS_DEBUG, "%s:%d dev: %s, flags: 0x%lx\n", |
| 394 | __func__, __LINE__, |
| 395 | dev_path(curdev), res->flags); |
| 396 | if (res->size == 0 || |
| 397 | get_res_type(res->flags) != res_types[rt] || |
| 398 | (res->flags & IORESOURCE_BRIDGE) || |
| 399 | !need_assignment(res->flags)) |
| 400 | continue; |
| 401 | else |
| 402 | add_res_to_stack(&res_root, curdev, res); |
| 403 | } |
| 404 | } |
| 405 | |
| 406 | /* Allocate resources and update bridge range */ |
| 407 | if (res_root || (bridge && !(bridge->flags & IORESOURCE_ASSIGNED))) { |
| 408 | reserve_dev_resources(stack, res_types[rt], res_root, bridge); |
| 409 | reclaim_resource_mem(res_root); |
| 410 | } |
| 411 | } |
| 412 | } |
| 413 | } |
| 414 | |
| 415 | static void xeonsp_pci_domain_read_resources(struct device *dev) |
| 416 | { |
| 417 | struct bus *link; |
| 418 | |
| 419 | DEV_FUNC_ENTER(dev); |
| 420 | |
| 421 | pci_domain_read_resources(dev); |
| 422 | |
| 423 | /* |
| 424 | * Walk through all devices in this domain and read resources. |
| 425 | * Since there is no callback when read resource operation is |
| 426 | * complete for all devices, domain read resource function initiates |
| 427 | * read resources for all devices and swaps read resource operation |
| 428 | * with dummy function to avoid warning. |
| 429 | */ |
| 430 | for (link = dev->link_list; link; link = link->next) |
| 431 | xeonsp_pci_dev_iterator(link, xeonsp_pci_dev_read_resources, NULL, NULL); |
| 432 | |
| 433 | for (link = dev->link_list; link; link = link->next) |
| 434 | xeonsp_pci_dev_iterator(link, xeonsp_reset_pci_op, NULL, NULL); |
| 435 | |
| 436 | struct iiostack_resource stack_info = {0}; |
| 437 | uint8_t pci64bit_alloc_flag = get_iiostack_info(&stack_info); |
| 438 | if (!pci64bit_alloc_flag) { |
| 439 | /* |
| 440 | * Split 32 bit address space between prefetchable and |
| 441 | * non-prefetchable windows |
| 442 | */ |
| 443 | for (int s = 0; s < stack_info.no_of_stacks; ++s) { |
| 444 | STACK_RES *res = &stack_info.res[s]; |
| 445 | uint64_t length = (res->PciResourceMem32Limit - |
| 446 | res->PciResourceMem32Base + 1)/2; |
| 447 | res->PciResourceMem64Limit = res->PciResourceMem32Limit; |
| 448 | res->PciResourceMem32Limit = (res->PciResourceMem32Base + length - 1); |
| 449 | res->PciResourceMem64Base = res->PciResourceMem32Limit + 1; |
| 450 | } |
| 451 | } |
| 452 | |
| 453 | |
| 454 | /* assign resources */ |
| 455 | assign_stack_resources(&stack_info, dev, NULL); |
| 456 | |
| 457 | DEV_FUNC_EXIT(dev); |
| 458 | } |
| 459 | |
| 460 | static void reset_resource_to_unassigned(struct device *dev, struct resource *res, void *data) |
| 461 | { |
| 462 | if ((res->flags & (IORESOURCE_IO | IORESOURCE_MEM)) && |
| 463 | !(res->flags & (IORESOURCE_FIXED | IORESOURCE_RESERVE))) { |
| 464 | res->flags &= ~IORESOURCE_ASSIGNED; |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | static void xeonsp_cpx_pci_domain_set_resources(struct device *dev) |
| 469 | { |
| 470 | DEV_FUNC_ENTER(dev); |
| 471 | |
| 472 | print_resource_tree(dev, BIOS_SPEW, "Before xeonsp pci domain set resource"); |
| 473 | |
| 474 | /* reset bus 0 dev resource assignment - need to change them to FSP IIOStack window */ |
| 475 | xeonsp_pci_dev_iterator(dev->link_list, NULL, reset_resource_to_unassigned, NULL); |
| 476 | |
| 477 | /* update dev resources based on IIOStack IO/Mem32/Mem64 windows */ |
| 478 | xeonsp_pci_domain_read_resources(dev); |
| 479 | |
| 480 | struct bus *link = dev->link_list; |
| 481 | while (link != NULL) { |
| 482 | assign_resources(link); |
| 483 | link = link->next; |
| 484 | } |
| 485 | |
| 486 | print_resource_tree(dev, BIOS_SPEW, "After xeonsp pci domain set resource"); |
| 487 | |
| 488 | DEV_FUNC_EXIT(dev); |
| 489 | } |
| 490 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 491 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
| 492 | { |
| 493 | /* not implemented yet */ |
| 494 | } |
| 495 | |
| 496 | static struct device_operations pci_domain_ops = { |
| 497 | .read_resources = &pci_domain_read_resources, |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 498 | .set_resources = &xeonsp_cpx_pci_domain_set_resources, |
| 499 | .scan_bus = &xeonsp_cpx_pci_domain_scan_bus, |
Jonathan Zhang | 3172f98 | 2020-05-28 17:53:48 -0700 | [diff] [blame] | 500 | .write_acpi_tables = &northbridge_write_acpi_tables, |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 501 | }; |
| 502 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 503 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 504 | .read_resources = noop_read_resources, |
| 505 | .set_resources = noop_set_resources, |
Andrey Petrov | 8670e82 | 2020-03-30 12:25:06 -0700 | [diff] [blame] | 506 | .init = cpx_init_cpus, |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 507 | }; |
| 508 | |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 509 | /* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ |
| 510 | static void attach_iio_stacks(struct device *dev) |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 511 | { |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 512 | struct bus *iiostack_bus; |
| 513 | struct iiostack_resource stack_info = {0}; |
| 514 | |
| 515 | DEV_FUNC_ENTER(dev); |
| 516 | |
| 517 | get_iiostack_info(&stack_info); |
| 518 | for (int s = 0; s < stack_info.no_of_stacks; ++s) { |
| 519 | /* only non zero bus no. needs to be enumerated */ |
| 520 | if (stack_info.res[s].BusBase == 0) |
| 521 | continue; |
| 522 | |
| 523 | iiostack_bus = malloc(sizeof(struct bus)); |
| 524 | if (iiostack_bus == NULL) |
| 525 | die("%s: out of memory.\n", __func__); |
| 526 | memset(iiostack_bus, 0, sizeof(*iiostack_bus)); |
| 527 | memcpy(iiostack_bus, dev->bus, sizeof(*iiostack_bus)); |
| 528 | iiostack_bus->secondary = stack_info.res[s].BusBase; |
| 529 | iiostack_bus->subordinate = stack_info.res[s].BusBase; |
| 530 | iiostack_bus->dev = NULL; |
| 531 | iiostack_bus->children = NULL; |
| 532 | iiostack_bus->next = NULL; |
| 533 | iiostack_bus->link_num = 1; |
| 534 | |
| 535 | if (dev->link_list == NULL) { |
| 536 | dev->link_list = iiostack_bus; |
| 537 | } else { |
| 538 | struct bus *nlink = dev->link_list; |
| 539 | while (nlink->next != NULL) |
| 540 | nlink = nlink->next; |
| 541 | nlink->next = iiostack_bus; |
| 542 | } |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 543 | } |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 544 | |
| 545 | DEV_FUNC_EXIT(dev); |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 546 | } |
| 547 | |
| 548 | static void pch_enable_ioapic(const struct device *dev) |
| 549 | { |
| 550 | uint32_t reg32; |
| 551 | |
| 552 | set_ioapic_id((void *)IO_APIC_ADDR, 2); |
| 553 | |
| 554 | /* affirm full set of redirection table entries ("write once") */ |
| 555 | reg32 = io_apic_read((void *)IO_APIC_ADDR, 1); |
| 556 | |
| 557 | reg32 &= ~0x00ff0000; |
| 558 | reg32 |= (C620_IOAPIC_REDIR_ENTRIES - 1) << 16; |
| 559 | |
| 560 | io_apic_write((void *)IO_APIC_ADDR, 1, reg32); |
| 561 | |
| 562 | /* |
| 563 | * Select Boot Configuration register (0x03) and |
| 564 | * use Processor System Bus (0x01) to deliver interrupts. |
| 565 | */ |
| 566 | io_apic_write((void *)IO_APIC_ADDR, 3, 1); |
| 567 | } |
| 568 | |
| 569 | struct pci_operations soc_pci_ops = { |
| 570 | .set_subsystem = pci_dev_set_subsystem, |
| 571 | }; |
| 572 | |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 573 | static void chip_enable_dev(struct device *dev) |
| 574 | { |
| 575 | /* Set the operations if it is a special bus type */ |
| 576 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 577 | dev->ops = &pci_domain_ops; |
| 578 | attach_iio_stacks(dev); |
| 579 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 580 | dev->ops = &cpu_bus_ops; |
| 581 | } |
| 582 | } |
| 583 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 584 | static void chip_final(void *data) |
| 585 | { |
Andrey Petrov | 4e48ac0 | 2020-04-30 14:08:19 -0700 | [diff] [blame] | 586 | p2sb_hide(); |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | static void chip_init(void *data) |
| 590 | { |
| 591 | printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); |
| 592 | fsp_silicon_init(false); |
| 593 | pch_enable_ioapic(NULL); |
| 594 | setup_lapic(); |
Andrey Petrov | 4e48ac0 | 2020-04-30 14:08:19 -0700 | [diff] [blame] | 595 | p2sb_unhide(); |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 596 | } |
| 597 | |
| 598 | struct chip_operations soc_intel_xeon_sp_cpx_ops = { |
| 599 | CHIP_NAME("Intel Cooperlake-SP") |
| 600 | .enable_dev = chip_enable_dev, |
| 601 | .init = chip_init, |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 602 | .final = chip_final, |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 603 | }; |