Thomas Jourdan | 1a692d8 | 2009-07-01 17:01:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <string.h> |
| 26 | #include <cpu/cpu.h> |
| 27 | #include <cpu/x86/mtrr.h> |
| 28 | #include <cpu/x86/msr.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <cpu/intel/microcode.h> |
| 31 | #include <cpu/intel/hyperthreading.h> |
| 32 | #include <cpu/x86/cache.h> |
| 33 | #include <cpu/x86/mtrr.h> |
| 34 | |
| 35 | static const uint32_t microcode_updates[] = { |
| 36 | /* Dummy terminator */ |
| 37 | 0x0, 0x0, 0x0, 0x0, |
| 38 | 0x0, 0x0, 0x0, 0x0, |
| 39 | 0x0, 0x0, 0x0, 0x0, |
| 40 | 0x0, 0x0, 0x0, 0x0, |
| 41 | }; |
| 42 | |
| 43 | static inline void strcpy(char *dst, char *src) |
| 44 | { |
| 45 | while (*src) *dst++ = *src++; |
| 46 | } |
| 47 | |
| 48 | static void init_timer(void) |
| 49 | { |
| 50 | /* Set the apic timer to no interrupts and periodic mode */ |
| 51 | lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0)); |
| 52 | |
| 53 | /* Set the divider to 1, no divider */ |
| 54 | lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); |
| 55 | |
| 56 | /* Set the initial counter to 0xffffffff */ |
| 57 | lapic_write(LAPIC_TMICT, 0xffffffff); |
| 58 | } |
| 59 | |
| 60 | static void fill_processor_name(char *processor_name) |
| 61 | { |
| 62 | struct cpuid_result regs; |
| 63 | char temp_processor_name[49]; |
| 64 | char *processor_name_start; |
| 65 | unsigned int *name_as_ints = (unsigned int *)temp_processor_name; |
| 66 | int i; |
| 67 | |
| 68 | for (i=0; i<3; i++) { |
| 69 | regs = cpuid(0x80000002 + i); |
| 70 | name_as_ints[i*4 + 0] = regs.eax; |
| 71 | name_as_ints[i*4 + 1] = regs.ebx; |
| 72 | name_as_ints[i*4 + 2] = regs.ecx; |
| 73 | name_as_ints[i*4 + 3] = regs.edx; |
| 74 | } |
| 75 | |
| 76 | temp_processor_name[48] = 0; |
| 77 | |
| 78 | /* Skip leading spaces */ |
| 79 | processor_name_start = temp_processor_name; |
| 80 | while (*processor_name_start == ' ') |
| 81 | processor_name_start++; |
| 82 | |
| 83 | memset(processor_name, 0, 49); |
| 84 | strcpy(processor_name, processor_name_start); |
| 85 | } |
| 86 | |
| 87 | #define IA32_FEATURE_CONTROL 0x003a |
| 88 | |
| 89 | #define CPUID_VMX (1 << 5) |
| 90 | #define CPUID_SMX (1 << 6) |
| 91 | static void enable_vmx(void) |
| 92 | { |
| 93 | struct cpuid_result regs; |
| 94 | msr_t msr; |
| 95 | |
| 96 | msr = rdmsr(IA32_FEATURE_CONTROL); |
| 97 | |
| 98 | if (msr.lo & (1 << 0)) { |
| 99 | /* VMX locked. If we set it again we get an illegal |
| 100 | * instruction |
| 101 | */ |
| 102 | return; |
| 103 | } |
| 104 | |
| 105 | regs = cpuid(1); |
| 106 | if (regs.ecx & CPUID_VMX) { |
| 107 | msr.lo |= (1 << 2); |
| 108 | if (regs.ecx & CPUID_SMX) |
| 109 | msr.lo |= (1 << 1); |
| 110 | } |
| 111 | |
| 112 | wrmsr(IA32_FEATURE_CONTROL, msr); |
| 113 | |
| 114 | msr.lo |= (1 << 0); /* Set lock bit */ |
| 115 | |
| 116 | wrmsr(IA32_FEATURE_CONTROL, msr); |
| 117 | } |
| 118 | |
| 119 | #define PMG_CST_CONFIG_CONTROL 0xe2 |
| 120 | #define PMG_IO_BASE_ADDR 0xe3 |
| 121 | #define PMG_IO_CAPTURE_ADDR 0xe4 |
| 122 | |
| 123 | #define PMB0_BASE 0x580 |
| 124 | #define PMB1_BASE 0x800 |
| 125 | #define CST_RANGE 2 |
| 126 | static void configure_c_states(void) |
| 127 | { |
| 128 | msr_t msr; |
| 129 | |
| 130 | msr = rdmsr(PMG_CST_CONFIG_CONTROL); |
| 131 | |
| 132 | msr.lo |= (1 << 15); // config lock until next reset |
| 133 | msr.lo |= (1 << 14); // Deeper Sleep |
| 134 | msr.lo |= (1 << 10); // Enable IO MWAIT redirection |
| 135 | msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk |
| 136 | msr.lo |= (1 << 3); // Dynamic L2 |
| 137 | |
| 138 | wrmsr(PMG_CST_CONFIG_CONTROL, msr); |
| 139 | |
| 140 | /* Set Processor MWAIT IO BASE */ |
| 141 | msr.hi = 0; |
| 142 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); |
| 143 | wrmsr(PMG_IO_BASE_ADDR, msr); |
| 144 | |
| 145 | /* Set IO Capture Address */ |
| 146 | msr.hi = 0; |
| 147 | msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16); |
| 148 | wrmsr(PMG_IO_CAPTURE_ADDR, msr); |
| 149 | } |
| 150 | |
| 151 | #define IA32_MISC_ENABLE 0x1a0 |
| 152 | static void configure_misc(void) |
| 153 | { |
| 154 | msr_t msr; |
| 155 | |
| 156 | msr = rdmsr(IA32_MISC_ENABLE); |
| 157 | msr.lo |= (1 << 3); /* TM1 enable */ |
| 158 | msr.lo |= (1 << 13); /* TM2 enable */ |
| 159 | msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ |
| 160 | |
| 161 | msr.lo |= (1 << 10); /* FERR# multiplexing */ |
| 162 | |
| 163 | // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 |
| 164 | msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ |
| 165 | |
| 166 | /* Enable C2E */ |
| 167 | msr.lo |= (1 << 26); |
| 168 | |
| 169 | /* Enable C4E */ |
| 170 | /* TODO This should only be done on mobile CPUs, see cpuid 5 */ |
| 171 | msr.hi |= (1 << (32 - 32)); // C4E |
| 172 | msr.hi |= (1 << (33 - 32)); // Hard C4E |
| 173 | |
| 174 | /* Enable EMTTM. */ |
| 175 | /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */ |
| 176 | msr.hi |= (1 << (36 - 32)); |
| 177 | |
| 178 | wrmsr(IA32_MISC_ENABLE, msr); |
| 179 | |
| 180 | msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ |
| 181 | wrmsr(IA32_MISC_ENABLE, msr); |
| 182 | } |
| 183 | |
| 184 | #define PIC_SENS_CFG 0x1aa |
| 185 | static void configure_pic_thermal_sensors(void) |
| 186 | { |
| 187 | msr_t msr; |
| 188 | |
| 189 | msr = rdmsr(PIC_SENS_CFG); |
| 190 | |
| 191 | msr.lo |= (1 << 21); // inter-core lock TM1 |
| 192 | msr.lo |= (1 << 4); // Enable bypass filter |
| 193 | |
| 194 | wrmsr(PIC_SENS_CFG, msr); |
| 195 | } |
| 196 | |
| 197 | #if CONFIG_USBDEBUG_DIRECT |
| 198 | static unsigned ehci_debug_addr; |
| 199 | #endif |
| 200 | |
| 201 | static void model_1067x_init(device_t cpu) |
| 202 | { |
| 203 | char processor_name[49]; |
| 204 | |
| 205 | /* Turn on caching if we haven't already */ |
| 206 | x86_enable_cache(); |
| 207 | |
| 208 | /* Update the microcode */ |
| 209 | intel_update_microcode(microcode_updates); |
| 210 | |
| 211 | /* Print processor name */ |
| 212 | fill_processor_name(processor_name); |
| 213 | printk_info("CPU: %s.\n", processor_name); |
| 214 | |
| 215 | #if CONFIG_USBDEBUG_DIRECT |
| 216 | // Is this caution really needed? |
| 217 | if(!ehci_debug_addr) |
| 218 | ehci_debug_addr = get_ehci_debug(); |
| 219 | set_ehci_debug(0); |
| 220 | #endif |
| 221 | |
| 222 | /* Setup MTRRs */ |
| 223 | x86_setup_mtrrs(36); |
| 224 | x86_mtrr_check(); |
| 225 | |
| 226 | #if CONFIG_USBDEBUG_DIRECT |
| 227 | set_ehci_debug(ehci_debug_addr); |
| 228 | #endif |
| 229 | |
| 230 | /* Enable the local cpu apics */ |
| 231 | setup_lapic(); |
| 232 | |
| 233 | /* Initialize the APIC timer */ |
| 234 | init_timer(); |
| 235 | |
| 236 | /* Enable virtualization */ |
| 237 | enable_vmx(); |
| 238 | |
| 239 | /* Configure C States */ |
| 240 | configure_c_states(); |
| 241 | |
| 242 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 243 | configure_misc(); |
| 244 | |
| 245 | /* PIC thermal sensor control */ |
| 246 | configure_pic_thermal_sensors(); |
| 247 | |
| 248 | /* Start up my cpu siblings */ |
| 249 | intel_sibling_init(cpu); |
| 250 | } |
| 251 | |
| 252 | static struct device_operations cpu_dev_ops = { |
| 253 | .init = model_1067x_init, |
| 254 | }; |
| 255 | |
| 256 | static struct cpu_device_id cpu_table[] = { |
| 257 | { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */ |
| 258 | { 0, 0 }, |
| 259 | }; |
| 260 | |
| 261 | static const struct cpu_driver driver __cpu_driver = { |
| 262 | .ops = &cpu_dev_ops, |
| 263 | .id_table = cpu_table, |
| 264 | }; |
| 265 | |