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Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -07001config SOC_INTEL_APOLLOLAKE
2 bool
3 help
4 Intel Apollolake support
5
Hannah Williams3ff14a02017-05-05 16:30:22 -07006config SOC_INTEL_GLK
7 bool
8 default n
9 select SOC_INTEL_APOLLOLAKE
Pratik Prajapatidc194e22017-08-29 14:27:07 -070010 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
11 select SOC_INTEL_COMMON_BLOCK_SGX
Ravi Sarawadi3669a062018-02-27 13:23:42 -080012 select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
Aaron Durbin82d0f912018-04-21 00:16:28 -060013 select IDT_IN_EVERY_STAGE
Aaron Durbin5c9df702018-04-18 01:05:25 -060014 select PAGING_IN_CACHE_AS_RAM
Hannah Williams3ff14a02017-05-05 16:30:22 -070015 help
16 Intel GLK support
17
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070018if SOC_INTEL_APOLLOLAKE
19
20config CPU_SPECIFIC_OPTIONS
21 def_bool y
Aaron Durbined35b7c2016-07-13 23:17:38 -050022 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070023 select ARCH_BOOTBLOCK_X86_32
24 select ARCH_RAMSTAGE_X86_32
25 select ARCH_ROMSTAGE_X86_32
26 select ARCH_VERSTAGE_X86_32
Aaron Durbina9e03a32016-09-16 19:25:43 -050027 select BOOTBLOCK_CONSOLE
Aaron Durbin7b2c7812016-08-11 23:51:42 -050028 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
Aaron Durbine8e118d2016-08-12 15:00:10 -050029 select BOOT_DEVICE_SUPPORTS_WRITES
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070030 # CPU specific options
31 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
32 select IOAPIC
Subrata Banikccd87002017-03-08 17:55:26 +053033 select PCR_COMMON_IOSF_1_0
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070034 select SMP
35 select SSE2
36 select SUPPORT_CPU_UCODE_IN_CBFS
Saurabh Satija734aa872016-06-21 14:22:16 -070037 # Audio options
38 select ACPI_NHLT
39 select SOC_INTEL_COMMON_NHLT
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070040 # Misc options
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -070041 select C_ENVIRONMENT_BOOTBLOCK
Aaron Durbin934f4332017-12-15 12:59:18 -070042 select CACHE_MRC_SETTINGS
Brandon Breitenstein135eae92016-09-30 13:57:12 -070043 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070044 select COLLECT_TIMESTAMPS
Aaron Durbinc3ee3f62016-05-11 10:35:49 -050045 select COMMON_FADT
Ravi Sarawadia3d13fbd62017-04-25 19:30:58 -070046 select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
Duncan Lauried25dd992016-06-29 10:47:48 -070047 select GENERIC_GPIO_LIB
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070048 select HAVE_INTEL_FIRMWARE
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070049 select HAVE_SMI_HANDLER
Furquan Shaikhffb3a2d2016-10-24 15:28:23 -070050 select MRC_SETTINGS_PROTECT
Aaron Durbin934f4332017-12-15 12:59:18 -070051 select MRC_SETTINGS_VARIABLE_DATA
Aaron Durbinf5ff8542016-05-05 10:38:03 -050052 select NO_FIXED_XIP_ROM_SIZE
Furquan Shaikh94b18a12016-05-04 23:25:16 -070053 select NO_XIP_EARLY_STAGES
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070054 select PARALLEL_MP
Andrey Petrova697c192016-12-07 10:47:46 -080055 select PARALLEL_MP_AP_WORK
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070056 select PCIEXP_ASPM
57 select PCIEXP_COMMON_CLOCK
58 select PCIEXP_CLK_PM
59 select PCIEXP_L1_SUB_STATE
Subrata Banik7952e282017-03-14 18:26:27 +053060 select PCIEX_LENGTH_256MB
Aaron Durbin79587ed2016-09-16 16:30:09 -050061 select POSTCAR_CONSOLE
Aaron Durbineebe0e02016-03-18 11:19:38 -050062 select POSTCAR_STAGE
Hannah Williams1177bf52017-12-13 12:44:26 -080063 select PMC_INVALID_READ_AFTER_WRITE
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070064 select REG_SCRIPT
65 select RELOCATABLE_RAMSTAGE # Build fails if this is not selected
Aaron Durbin16246ea2016-08-05 21:23:37 -050066 select RTC
Hannah Williamsd9c84ca2016-05-13 00:47:14 -070067 select SMM_TSEG
Subrata Banik208587e2017-05-19 18:38:24 +053068 select SA_ENABLE_IMR
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070069 select SOC_INTEL_COMMON
Shaunak Saha60b46182016-08-02 17:25:13 -070070 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
Subrata Banikfc4c7d82017-03-03 18:23:59 +053071 select SOC_INTEL_COMMON_BLOCK
Shaunak Sahabd427802017-07-18 00:19:33 -070072 select SOC_INTEL_COMMON_BLOCK_ACPI
Barnali Sarkar66fe0c42017-05-23 18:17:14 +053073 select SOC_INTEL_COMMON_BLOCK_CPU
Lijian Zhao44e2abf2017-10-30 14:27:52 -070074 select SOC_INTEL_COMMON_BLOCK_DSP
Barnali Sarkare70142c2017-03-28 16:32:33 +053075 select SOC_INTEL_COMMON_BLOCK_FAST_SPI
Hannah Williams12bed182017-05-26 20:31:15 -070076 select SOC_INTEL_COMMON_BLOCK_GPIO
Aaron Durbinaa2504a2017-07-14 16:53:49 -060077 select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES
Hannah Williams12bed182017-05-26 20:31:15 -070078 select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
79 select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
Subrata Banikb7b56662017-11-28 17:54:15 +053080 select SOC_INTEL_COMMON_BLOCK_GRAPHICS
Bora Guvendik33117ec2017-04-10 15:49:02 -070081 select SOC_INTEL_COMMON_BLOCK_ITSS
Rizwan Qureshiae6a4b62017-04-26 21:06:35 +053082 select SOC_INTEL_COMMON_BLOCK_I2C
Ravi Sarawadiefa606b2017-08-04 16:26:09 -070083 select SOC_INTEL_COMMON_BLOCK_LPC
Aamir Bohra138b2a02017-04-06 20:21:58 +053084 select SOC_INTEL_COMMON_BLOCK_LPSS
Subrata Banikccd87002017-03-08 17:55:26 +053085 select SOC_INTEL_COMMON_BLOCK_PCR
Lijian Zhao8aba24d2017-10-26 12:16:53 -070086 select SOC_INTEL_COMMON_BLOCK_P2SB
Shaunak Saha93cdc8b2017-04-18 15:42:09 -070087 select SOC_INTEL_COMMON_BLOCK_PMC
V Sowmya45a21382017-11-27 12:39:10 +053088 select SOC_INTEL_COMMON_BLOCK_SRAM
Subrata Banik8bf69d32017-03-09 13:43:54 +053089 select SOC_INTEL_COMMON_BLOCK_RTC
Aamir Bohrabf6dfae2017-04-07 21:10:27 +053090 select SOC_INTEL_COMMON_BLOCK_SA
Bora Guvendik65623b72017-05-08 16:29:17 -070091 select SOC_INTEL_COMMON_BLOCK_SCS
Aamir Bohra4c9cf302017-05-25 14:38:37 +053092 select SOC_INTEL_COMMON_BLOCK_TIMER
Aamir Bohrabf6dfae2017-04-07 21:10:27 +053093 select SOC_INTEL_COMMON_BLOCK_UART
Subrata Banik4aaa7e32017-04-24 11:54:34 +053094 select SOC_INTEL_COMMON_BLOCK_XDCI
Subrata Banik73b17972017-04-24 10:25:56 +053095 select SOC_INTEL_COMMON_BLOCK_XHCI
Brandon Breitensteina86d1b82017-06-08 17:32:02 -070096 select SOC_INTEL_COMMON_BLOCK_SMM
Subrata Banik15129b42017-11-07 17:50:48 +053097 select SOC_INTEL_COMMON_BLOCK_SPI
Marshall Dawson0cc28d72017-12-12 12:24:19 -070098 select SOC_INTEL_COMMON_BLOCK_CSE
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -070099 select UDELAY_TSC
Andrey Petrov87fb1a62016-02-10 17:47:03 -0800100 select TSC_CONSTANT_RATE
Hannah Williamsb13d4542016-03-14 17:38:51 -0700101 select TSC_MONOTONIC_TIMER
102 select HAVE_MONOTONIC_TIMER
Andrey Petrov0d187912016-02-25 18:39:38 -0800103 select PLATFORM_USES_FSP2_0
Subrata Banik74558812018-01-25 11:41:04 +0530104 select UDK_2015_BINDING if !SOC_INTEL_GLK
105 select UDK_2017_BINDING if SOC_INTEL_GLK
Zhao, Lijiand8d42c22016-03-14 14:19:22 -0700106 select HAVE_HARD_RESET
Patrick Rudolph4c170982017-07-17 19:53:56 +0200107 select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
Nico Huber2e7f6cc2017-05-22 15:58:03 +0200108 select HAVE_FSP_GOP
Ravi Sarawadi92b487d2017-11-29 16:11:32 -0800109 select NO_UART_ON_SUPERIO
Patrick Rudolphc7edf182017-09-26 19:34:35 +0200110 select INTEL_GMA_ACPI
111 select INTEL_GMA_SWSMISCI
Zhao, Lijiand8d42c22016-03-14 14:19:22 -0700112
Furquan Shaikh87b1bcc2016-07-22 12:57:51 -0700113config CHROMEOS
114 select CHROMEOS_RAMOOPS_DYNAMIC
Julius Werner58c39382017-02-13 17:53:29 -0800115
116config VBOOT
117 select VBOOT_SEPARATE_VERSTAGE
Furquan Shaikh87b1bcc2016-07-22 12:57:51 -0700118 select VBOOT_OPROM_MATTERS
Furquan Shaikh7c7b2912016-07-22 09:02:35 -0700119 select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
Furquan Shaikh87b1bcc2016-07-22 12:57:51 -0700120 select VBOOT_STARTS_IN_BOOTBLOCK
Furquan Shaikh2a12e2e2016-07-25 11:48:03 -0700121 select VBOOT_VBNV_CMOS
122 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Furquan Shaikh87b1bcc2016-07-22 12:57:51 -0700123
Aaron Durbin80a3df22016-04-27 23:05:52 -0500124config TPM_ON_FAST_SPI
125 bool
126 default n
127 select LPC_TPM
128 help
129 TPM part is conntected on Fast SPI interface, but the LPC MMIO
130 TPM transactions are decoded and serialized over the SPI interface.
131
Zhao, Lijiand8d42c22016-03-14 14:19:22 -0700132config SOC_INTEL_COMMON_RESET
133 bool
Andrey Petrov9c0e1802016-06-23 08:26:00 -0700134 default y
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -0700135
Subrata Banikccd87002017-03-08 17:55:26 +0530136config PCR_BASE_ADDRESS
137 hex
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -0700138 default 0xd0000000
Subrata Banikccd87002017-03-08 17:55:26 +0530139 help
140 This option allows you to select MMIO Base Address of sideband bus.
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -0700141
142config DCACHE_RAM_BASE
Arthur Heymans3038b482017-06-13 14:05:09 +0200143 hex
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -0700144 default 0xfef00000
145
146config DCACHE_RAM_SIZE
Arthur Heymans3038b482017-06-13 14:05:09 +0200147 hex
Aaron Durbinfa529bb2018-04-12 14:00:45 -0600148 default 0x100000 if SOC_INTEL_GLK
Andrey Petrov0dde2912016-06-27 15:21:26 -0700149 default 0xc0000
Alexandru Gagniucdfc2b312015-10-06 17:16:41 -0700150 help
151 The size of the cache-as-ram region required during bootblock
152 and/or romstage.
153
154config DCACHE_BSP_STACK_SIZE
155 hex
156 default 0x4000
157 help
158 The amount of anticipated stack usage in CAR by bootblock and
159 other stages.
160
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -0700161config CPU_ADDR_BITS
162 int
Hannah Williams57d8ccb2018-04-14 23:04:34 -0700163 default 39
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -0700164
Aaron Durbin551e4be2018-04-10 09:24:54 -0600165config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
Duncan Laurieff8bce02016-06-27 10:57:13 -0700166 int
Aaron Durbin24de5972018-04-10 09:28:42 -0600167 default 100
Duncan Laurieff8bce02016-06-27 10:57:13 -0700168
Chris Chingb8dc63b2017-12-06 14:26:15 -0700169config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
170 int
Aaron Durbin24de5972018-04-10 09:28:42 -0600171 default 133
Chris Chingb8dc63b2017-12-06 14:26:15 -0700172
Andrey Petrov87fb1a62016-02-10 17:47:03 -0800173config CONSOLE_UART_BASE_ADDRESS
174 depends on CONSOLE_SERIAL
Arthur Heymans3038b482017-06-13 14:05:09 +0200175 hex
Andrey Petrov87fb1a62016-02-10 17:47:03 -0800176 default 0xde000000
177
Aaron Durbin61810302016-02-24 18:49:07 -0600178config SOC_UART_DEBUG
179 bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
180 default n
181 select CONSOLE_SERIAL
Aaron Durbin61810302016-02-24 18:49:07 -0600182 select DRIVERS_UART
183 select DRIVERS_UART_8250MEM_32
184 select NO_UART_ON_SUPERIO
185
Aaron Durbinada13ed2016-02-11 14:47:33 -0600186# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB.
187config C_ENV_BOOTBLOCK_SIZE
188 hex
189 default 0x8000
190
Andrey Petrov5672dcd2016-02-12 15:12:43 -0800191# This SoC does not map SPI flash like many previous SoC. Therefore we provide
192# a custom media driver that facilitates mapping
193config X86_TOP4G_BOOTMEDIA_MAP
194 bool
195 default n
Andrey Petrovb4831462016-02-25 17:42:25 -0800196
197config ROMSTAGE_ADDR
198 hex
Andrey Petrov7f72c9b2016-06-24 18:15:09 -0700199 default 0xfef20000
Andrey Petrovb4831462016-02-25 17:42:25 -0800200 help
201 The base address (in CAR) where romstage should be linked
202
Aaron Durbinbef75e72016-05-26 11:00:44 -0500203config VERSTAGE_ADDR
204 hex
Andrey Petrov7f72c9b2016-06-24 18:15:09 -0700205 default 0xfef40000
Aaron Durbinbef75e72016-05-26 11:00:44 -0500206 help
207 The base address (in CAR) where verstage should be linked
208
Andrey Petrov79091db72016-05-17 00:03:27 -0700209config FSP_M_ADDR
210 hex
Andrey Petrov7f72c9b2016-06-24 18:15:09 -0700211 default 0xfef40000
Andrey Petrov79091db72016-05-17 00:03:27 -0700212 help
213 The address FSP-M will be relocated to during build time
214
Aaron Durbin9f444c32016-05-20 10:48:44 -0500215config NEED_LBP2
216 bool "Write contents for logical boot partition 2."
217 default n
218 help
219 Write the contents from a file into the logical boot partition 2
220 region defined by LBP2_FMAP_NAME.
221
222config LBP2_FMAP_NAME
223 string "Name of FMAP region to put logical boot partition 2"
224 depends on NEED_LBP2
225 default "SIGN_CSE"
226 help
227 Name of FMAP region to write logical boot partition 2 data.
228
229config LBP2_FILE_NAME
230 string "Path of file to write to logical boot partition 2 region"
231 depends on NEED_LBP2
232 default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin"
233 help
234 Name of file to store in the logical boot partition 2 region.
235
Furquan Shaikh7043bf32016-05-28 12:57:05 -0700236config NEED_IFWI
237 bool "Write content into IFWI region"
238 default n
239 help
240 Write the content from a file into IFWI region defined by
241 IFWI_FMAP_NAME.
242
243config IFWI_FMAP_NAME
244 string "Name of FMAP region to pull IFWI into"
245 depends on NEED_IFWI
246 default "IFWI"
247 help
248 Name of FMAP region to write IFWI.
249
250config IFWI_FILE_NAME
251 string "Path of file to write to IFWI region"
252 depends on NEED_IFWI
253 default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin"
254 help
255 Name of file to store in the IFWI region.
256
Sathyanarayana Nujellac4467042016-10-26 17:38:49 -0700257config HEAP_SIZE
258 hex
259 default 0x8000
260
Sathyanarayana Nujella3e0a3fb2016-10-26 17:31:36 -0700261config NHLT_DMIC_1CH_16B
262 bool
263 depends on ACPI_NHLT
264 default n
265 help
266 Include DSP firmware settings for 1 channel 16B DMIC array.
267
Saurabh Satija734aa872016-06-21 14:22:16 -0700268config NHLT_DMIC_2CH_16B
269 bool
270 depends on ACPI_NHLT
271 default n
272 help
273 Include DSP firmware settings for 2 channel 16B DMIC array.
274
Sathyanarayana Nujella3e0a3fb2016-10-26 17:31:36 -0700275config NHLT_DMIC_4CH_16B
276 bool
277 depends on ACPI_NHLT
278 default n
279 help
280 Include DSP firmware settings for 4 channel 16B DMIC array.
281
Saurabh Satija734aa872016-06-21 14:22:16 -0700282config NHLT_MAX98357
283 bool
284 depends on ACPI_NHLT
285 default n
286 help
287 Include DSP firmware settings for headset codec.
288
289config NHLT_DA7219
290 bool
291 depends on ACPI_NHLT
292 default n
293 help
294 Include DSP firmware settings for headset codec.
Subrata Banikfc4c7d82017-03-03 18:23:59 +0530295
Andrey Petrov3f4aece2016-06-27 13:39:34 -0700296choice
297 prompt "Cache-as-ram implementation"
Hannah Williams3ff14a02017-05-05 16:30:22 -0700298 default CAR_CQOS if !SOC_INTEL_GLK
299 default CAR_NEM
Andrey Petrov3f4aece2016-06-27 13:39:34 -0700300 help
301 This option allows you to select how cache-as-ram (CAR) is set up.
302
303config CAR_NEM
304 bool "Non-evict mode"
Subrata Banikfc4c7d82017-03-03 18:23:59 +0530305 select SOC_INTEL_COMMON_BLOCK_CAR
306 select INTEL_CAR_NEM
Andrey Petrov3f4aece2016-06-27 13:39:34 -0700307 help
308 Traditionally, CAR is set up by using Non-Evict mode. This method
309 does not allow CAR and cache to co-exist, because cache fills are
310 block in NEM mode.
311
312config CAR_CQOS
313 bool "Cache Quality of Service"
Subrata Banikfc4c7d82017-03-03 18:23:59 +0530314 select SOC_INTEL_COMMON_BLOCK_CAR
315 select INTEL_CAR_CQOS
Andrey Petrov3f4aece2016-06-27 13:39:34 -0700316 help
317 Cache Quality of Service allows more fine-grained control of cache
318 usage. As result, it is possible to set up portion of L2 cache for
319 CAR and use remainder for actual caching.
320
Subrata Banikfc4c7d82017-03-03 18:23:59 +0530321config USE_APOLLOLAKE_FSP_CAR
322 bool "Use FSP CAR"
323 select FSP_CAR
324 help
Subrata Banik7952e282017-03-14 18:26:27 +0530325 Use FSP APIs to initialize & tear down the Cache-As-Ram.
Subrata Banikfc4c7d82017-03-03 18:23:59 +0530326
Andrey Petrov3f4aece2016-06-27 13:39:34 -0700327endchoice
Saurabh Satija734aa872016-06-21 14:22:16 -0700328
Subrata Banik8e1c12f2017-03-10 13:51:11 +0530329#
330# Each bit in QOS mask controls this many bytes. This is calculated as:
331# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
332#
333
334config CACHE_QOS_SIZE_PER_BIT
335 hex
336 default 0x20000 # 128 KB
337
338config L2_CACHE_SIZE
339 hex
Aaron Durbinfa529bb2018-04-12 14:00:45 -0600340 default 0x400000 if SOC_INTEL_GLK
Subrata Banik8e1c12f2017-03-10 13:51:11 +0530341 default 0x100000
342
Aaron Durbinbdb6cc92016-08-11 09:48:52 -0500343config SPI_FLASH_INCLUDE_ALL_DRIVERS
344 bool
345 default n
346
Brandon Breitenstein135eae92016-09-30 13:57:12 -0700347config SMM_RESERVED_SIZE
348 hex
349 default 0x100000
350
Andrey Petrov4c5b31e2016-11-06 23:43:57 -0800351config IFD_CHIPSET
352 string
Furquan Shaikhc0257dd2018-05-02 23:29:04 -0700353 default "glk" if SOC_INTEL_GLK
Andrey Petrov4c5b31e2016-11-06 23:43:57 -0800354 default "aplk"
355
Aamir Bohra22b2c792017-06-02 19:07:56 +0530356config CPU_BCLK_MHZ
357 int
358 default 100
359
Mario Scheithauer38b61002017-07-25 10:52:41 +0200360config APL_SKIP_SET_POWER_LIMITS
361 bool
362 default n
363 help
364 Some Apollo Lake mainboards do not need the Running Average Power
365 Limits (RAPL) algorithm for a constant power management.
366 Set this config option to skip the RAPL configuration.
367
Furquan Shaikh3406dd62017-08-04 15:58:26 -0700368# M and N divisor values for clock frequency configuration.
369# These values get us a 1.836 MHz clock (ideally we want 1.843 MHz)
370config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
371 hex
372 default 0x25a
373
374config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
375 hex
376 default 0x7fff
377
Bora Guvendik94aed8d2017-11-03 12:40:25 -0700378config SOC_ESPI
379 bool
380 default n
381 help
382 Use eSPI bus instead of LPC
383
Ravi Sarawadi3669a062018-02-27 13:23:42 -0800384config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
385 int
386 default 3
387
Aaron Durbin5c9df702018-04-18 01:05:25 -0600388# Don't include the early page tables in RW_A or RW_B cbfs regions
389config RO_REGION_ONLY
390 string
391 default "pdpt pt"
392
Alexandru Gagniuc7e86cd42015-10-06 10:33:49 -0700393endif