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Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +03001#
2# This file is part of the coreboot project.
3#
Marc Jonesaa31f992016-09-20 20:30:17 -06004# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +03005#
6# This program is free software; you can redistribute it and/or modify
7# it under the terms of the GNU General Public License as published by
8# the Free Software Foundation; version 2 of the License.
9#
10# This program is distributed in the hope that it will be useful,
11# but WITHOUT ANY WARRANTY; without even the implied warranty of
12# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13# GNU General Public License for more details.
14#
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030015
16config NORTHBRIDGE_AMD_PI
Martin Roth595e7772015-04-26 18:53:26 -060017 bool
Marc Jones21cde8b2017-05-07 16:47:36 -060018 default y if CPU_AMD_PI
Marc Jones21cde8b2017-05-07 16:47:36 -060019 default n
Kyösti Mälkki6e37b0a2017-04-17 06:45:56 +030020 select CBMEM_TOP_BACKUP
Kyösti Mälkkie95b6b22017-04-17 06:45:56 +030021 select RELOCATABLE_RAMSTAGE
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030022
23if NORTHBRIDGE_AMD_PI
24
Ricardo Ribalda Delgadoa1328922016-12-28 15:16:22 +010025config BOTTOMIO_POSITION
26 hex "Bottom of 32-bit IO space"
27 default 0xD0000000
28 help
29 If PCI peripherals with big BARs are connected to the system
30 the bottom of the IO must be decreased to allocate such
31 devices.
32
33 Declare the beginning of the 128MB-aligned MMIO region. This
34 option is useful when PCI peripherals requesting large address
35 ranges are present.
36
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030037config CONSOLE_VGA_MULTI
38 bool
39 default n
40
41config S3_VGA_ROM_RUN
42 bool
43 default n
44
Bruce Griffith006364e2014-10-22 03:33:49 -060045source src/northbridge/amd/pi/00630F01/Kconfig
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030046source src/northbridge/amd/pi/00730F01/Kconfig
WANG Siyuan05639412015-05-20 14:44:32 +080047source src/northbridge/amd/pi/00660F01/Kconfig
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030048
WANG Siyuan2dcd0fc2015-06-02 16:25:58 +080049config HW_MEM_HOLE_SIZEK
50 hex
51 default 0x200000
52
53config HW_MEM_HOLE_SIZE_AUTO_INC
54 bool
55 default n
56
57config RAMTOP
58 hex
59 default 0x1000000
60
61config HEAP_SIZE
62 hex
63 default 0xc0000
64
65config RAMBASE
66 hex
67 default 0x200000
68
Kyösti Mälkkie4c17ce2014-10-21 18:22:32 +030069endif # NORTHBRIDGE_AMD_PI