blob: d88e4692918a8b2269329ddccd0220afea40aa66 [file] [log] [blame]
Lee Leahyeef40eb2017-03-23 10:54:57 -07001/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Copyright 2013 Google Inc. All rights reserved.
6 * Copyright 2017 Intel Corporation
7 *
8 * MultiMediaCard (MMC) and eMMC specific support code
9 * This code is controller independent
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */
21
Lee Leahy48dbc662017-05-08 16:56:03 -070022#include <commonlib/storage.h>
Lee Leahy927f06a2017-06-19 10:53:18 -070023#include <delay.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070024#include "sd_mmc.h"
25#include "mmc.h"
26#include "sd_mmc.h"
27#include "storage.h"
28#include <string.h>
Lee Leahy927f06a2017-06-19 10:53:18 -070029#include <timer.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070030
31/* We pass in the cmd since otherwise the init seems to fail */
32static int mmc_send_op_cond_iter(struct storage_media *media,
33 struct mmc_command *cmd, int use_arg)
34{
35 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
36
37 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
38 cmd->resp_type = CARD_RSP_R3;
39
40 /* Set the controller's operating conditions */
41 if (use_arg) {
42 uint32_t mask = media->op_cond_response &
43 (OCR_VOLTAGE_MASK | OCR_ACCESS_MODE);
44 cmd->cmdarg = ctrlr->voltages & mask;
45
46 /* Always request high capacity if supported by the
47 * controller
48 */
49 if (ctrlr->caps & DRVR_CAP_HC)
50 cmd->cmdarg |= OCR_HCS;
51 }
52 cmd->flags = 0;
53 int err = ctrlr->send_cmd(ctrlr, cmd, NULL);
54 if (err)
55 return err;
56
57 media->op_cond_response = cmd->response[0];
58 return 0;
59}
60
61int mmc_send_op_cond(struct storage_media *media)
62{
63 struct mmc_command cmd;
64 int max_iters = 2;
65
66 /* Ask the card for its operating conditions */
67 cmd.cmdarg = 0;
68 for (int i = 0; i < max_iters; i++) {
69 int err = mmc_send_op_cond_iter(media, &cmd, i != 0);
70 if (err)
71 return err;
72
73 // OCR_BUSY is active low, this bit set means
74 // "initialization complete".
75 if (media->op_cond_response & OCR_BUSY)
76 return 0;
77 }
78 return CARD_IN_PROGRESS;
79}
80
81int mmc_complete_op_cond(struct storage_media *media)
82{
83 struct mmc_command cmd;
84 struct stopwatch sw;
85
86 stopwatch_init_msecs_expire(&sw, MMC_INIT_TIMEOUT_US_MS);
87 while (1) {
88 // CMD1 queries whether initialization is done.
89 int err = mmc_send_op_cond_iter(media, &cmd, 1);
90 if (err)
91 return err;
92
93 // OCR_BUSY means "initialization complete".
94 if (media->op_cond_response & OCR_BUSY)
95 break;
96
97 // Check if init timeout has expired.
98 if (stopwatch_expired(&sw))
99 return CARD_UNUSABLE_ERR;
100
101 udelay(100);
102 }
103
104 media->version = MMC_VERSION_UNKNOWN;
105 media->ocr = cmd.response[0];
106
107 media->high_capacity = ((media->ocr & OCR_HCS) == OCR_HCS);
108 media->rca = 0;
109 return 0;
110}
111
112int mmc_send_ext_csd(struct sd_mmc_ctrlr *ctrlr, unsigned char *ext_csd)
113{
114 struct mmc_command cmd;
115 struct mmc_data data;
116 int rv;
117
118 /* Get the Card Status Register */
119 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
120 cmd.resp_type = CARD_RSP_R1;
121 cmd.cmdarg = 0;
122 cmd.flags = 0;
123
124 data.dest = (char *)ext_csd;
125 data.blocks = 1;
126 data.blocksize = 512;
127 data.flags = DATA_FLAG_READ;
128
129 rv = ctrlr->send_cmd(ctrlr, &cmd, &data);
130
131 if (!rv && IS_ENABLED(CONFIG_SD_MMC_TRACE)) {
132 int i, size;
133
134 size = data.blocks * data.blocksize;
135 sd_mmc_trace("\t%p ext_csd:", ctrlr);
136 for (i = 0; i < size; i++) {
137 if (!(i % 32))
138 sd_mmc_trace("\n");
139 sd_mmc_trace(" %2.2x", ext_csd[i]);
140 }
141 sd_mmc_trace("\n");
142 }
143 return rv;
144}
145
146static int mmc_switch(struct storage_media *media, uint8_t index, uint8_t value)
147{
148 struct mmc_command cmd;
149 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
150
151 cmd.cmdidx = MMC_CMD_SWITCH;
152 cmd.resp_type = CARD_RSP_R1b;
153 cmd.cmdarg = ((MMC_SWITCH_MODE_WRITE_BYTE << 24) |
154 (index << 16) | (value << 8));
155 cmd.flags = 0;
156
157 int ret = ctrlr->send_cmd(ctrlr, &cmd, NULL);
158
159 /* Waiting for the ready status */
160 sd_mmc_send_status(media, SD_MMC_IO_RETRIES);
161 return ret;
162
163}
164
165static void mmc_recalculate_clock(struct storage_media *media)
166{
167 uint32_t clock;
168
169 clock = CLOCK_26MHZ;
170 if (media->caps & DRVR_CAP_HS) {
171 if ((media->caps & DRVR_CAP_HS200) ||
172 (media->caps & DRVR_CAP_HS400))
173 clock = CLOCK_200MHZ;
174 else if (media->caps & DRVR_CAP_HS52)
175 clock = CLOCK_52MHZ;
176 }
177 SET_CLOCK(media->ctrlr, clock);
178}
179
180static int mmc_select_hs(struct storage_media *media)
181{
182 int ret;
183
184 /* Switch the MMC device into high speed mode */
185 ret = mmc_switch(media, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS);
186 if (ret) {
187 sd_mmc_error("Timing switch to high speed failed\n");
188 return ret;
189 }
190 sdhc_debug("SDHCI switched MMC to high speed\n");
191
192 /* Increase the controller clock speed */
193 SET_TIMING(media->ctrlr, BUS_TIMING_MMC_HS);
194 media->caps |= DRVR_CAP_HS52 | DRVR_CAP_HS;
195 mmc_recalculate_clock(media);
196 ret = sd_mmc_send_status(media, SD_MMC_IO_RETRIES);
197 return ret;
198}
199
200static int mmc_send_tunning_seq(struct sd_mmc_ctrlr *ctrlr, char *buffer)
201{
202 struct mmc_command cmd;
203 struct mmc_data data;
204
205 /* Request the device send the tuning sequence to the host */
206 cmd.cmdidx = MMC_CMD_AUTO_TUNING_SEQUENCE;
207 cmd.resp_type = CARD_RSP_R1;
208 cmd.cmdarg = 0;
209 cmd.flags = CMD_FLAG_IGNORE_INHIBIT;
210
211 data.dest = buffer;
212 data.blocks = 1;
213 data.blocksize = (ctrlr->bus_width == 8) ? 128 : 64;
214 data.flags = DATA_FLAG_READ;
215 return ctrlr->send_cmd(ctrlr, &cmd, &data);
216}
217
218static int mmc_bus_tuning(struct storage_media *media)
219{
220 ALLOC_CACHE_ALIGN_BUFFER(char, buffer, 128);
221 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
222 int index;
223 int successful;
224
225 /* Request the device send the tuning sequence up to 40 times */
226 ctrlr->tuning_start(ctrlr, 0);
227 for (index = 0; index < 40; index++) {
228 mmc_send_tunning_seq(ctrlr, buffer);
229 if (ctrlr->is_tuning_complete(ctrlr, &successful)) {
230 if (successful)
231 return 0;
232 break;
233 }
234 }
235 sd_mmc_error("Bus tuning failed!\n");
236 return -1;
237}
238
239static int mmc_select_hs400(struct storage_media *media)
240{
241 uint8_t bus_width;
242 uint32_t caps;
243 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
244 int ret;
245 uint32_t timing;
246
247 /* Switch the MMC device into high speed mode */
248 ret = mmc_select_hs(media);
249 if (ret)
250 return ret;
251
252 /* Switch MMC device to 8-bit DDR with strobe */
253 bus_width = EXT_CSD_DDR_BUS_WIDTH_8;
254 caps = DRVR_CAP_HS400 | DRVR_CAP_HS52 | DRVR_CAP_HS;
255 timing = BUS_TIMING_MMC_HS400;
256 if ((ctrlr->caps & DRVR_CAP_ENHANCED_STROBE)
257 && (media->caps & DRVR_CAP_ENHANCED_STROBE)) {
258 bus_width |= EXT_CSD_BUS_WIDTH_STROBE;
259 caps |= DRVR_CAP_ENHANCED_STROBE;
260 timing = BUS_TIMING_MMC_HS400ES;
261 }
262 ret = mmc_switch(media, EXT_CSD_BUS_WIDTH, bus_width);
263 if (ret) {
264 sd_mmc_error("Switching bus width for HS400 failed\n");
265 return ret;
266 }
267 sdhc_debug("SDHCI switched MMC to 8-bit DDR\n");
268
269 /* Set controller to 8-bit mode */
270 SET_BUS_WIDTH(ctrlr, 8);
271 media->caps |= EXT_CSD_BUS_WIDTH_8;
272
273 /* Switch MMC device to HS400 */
274 ret = mmc_switch(media, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400);
275 if (ret) {
276 sd_mmc_error("Switch to HS400 timing failed\n");
277 return ret;
278 }
279
280 /* Set controller to 200 MHz and use receive strobe */
281 SET_TIMING(ctrlr, timing);
282 media->caps |= caps;
283 mmc_recalculate_clock(media);
284 ret = sd_mmc_send_status(media, SD_MMC_IO_RETRIES);
285 return ret;
286}
287
288static int mmc_select_hs200(struct storage_media *media)
289{
290 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
291 int ret;
292
293 /* Switch the MMC device to 8-bit SDR */
294 ret = mmc_switch(media, EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8);
295 if (ret) {
296 sd_mmc_error("Switching bus width for HS200 failed\n");
297 return ret;
298 }
299
300 /* Set controller to 8-bit mode */
301 SET_BUS_WIDTH(ctrlr, 8);
302 media->caps |= EXT_CSD_BUS_WIDTH_8;
303
304 /* Switch to HS200 */
305 ret = mmc_switch(media, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS200);
306
307 if (ret) {
308 sd_mmc_error("Switch to HS200 failed\n");
309 return ret;
310 }
311 sdhc_debug("SDHCI switched MMC to 8-bit SDR\n");
312
313 /* Set controller to 200 MHz */
314 SET_TIMING(ctrlr, BUS_TIMING_MMC_HS200);
315 media->caps |= DRVR_CAP_HS200 | DRVR_CAP_HS52 | DRVR_CAP_HS;
316 mmc_recalculate_clock(media);
317
318 /* Tune the receive sampling point for the bus */
319 if ((!ret) && (ctrlr->caps & DRVR_CAP_HS200_TUNING))
320 ret = mmc_bus_tuning(media);
321 return ret;
322}
323
324int mmc_change_freq(struct storage_media *media)
325{
326 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
327 int err;
328 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ext_csd, 512);
329
330 media->caps = 0;
331
332 /* Only version 4 supports high-speed */
333 if (media->version < MMC_VERSION_4)
334 return 0;
335
336 err = mmc_send_ext_csd(ctrlr, ext_csd);
337 if (err)
338 return err;
339
Barnali Sarkare9628402017-12-27 13:51:18 +0530340 /* Determine if the device supports enhanced strobe */
341 media->caps |= ext_csd[EXT_CSD_STROBE_SUPPORT]
342 ? DRVR_CAP_ENHANCED_STROBE : 0;
343
Lee Leahyeef40eb2017-03-23 10:54:57 -0700344 if ((ctrlr->caps & DRVR_CAP_HS400) &&
345 (ext_csd[EXT_CSD_CARD_TYPE] & MMC_HS400))
346 err = mmc_select_hs400(media);
347 else if ((ctrlr->caps & DRVR_CAP_HS200) &&
348 (ext_csd[EXT_CSD_CARD_TYPE] & MMC_HS_200MHZ))
349 err = mmc_select_hs200(media);
350 else
351 err = mmc_select_hs(media);
352
353 return err;
354}
355
356int mmc_set_bus_width(struct storage_media *media)
357{
358 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
359 int err;
360 int width;
361
362 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ext_csd, EXT_CSD_SIZE);
363 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, test_csd, EXT_CSD_SIZE);
364
365 /* Set the bus width */
366 err = 0;
367 for (width = EXT_CSD_BUS_WIDTH_8; width >= 0; width--) {
368 /* If HS200 is switched, Bus Width has been 8-bit */
369 if ((media->caps & DRVR_CAP_HS200) ||
370 (media->caps & DRVR_CAP_HS400))
371 break;
372
373 /* Set the card to use 4 bit*/
374 err = mmc_switch(media, EXT_CSD_BUS_WIDTH, width);
375 if (err)
376 continue;
377
378 if (!width) {
379 SET_BUS_WIDTH(ctrlr, 1);
380 break;
381 }
382 SET_BUS_WIDTH(ctrlr, 4 * width);
383
384 err = mmc_send_ext_csd(ctrlr, test_csd);
385 if (!err &&
386 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] ==
387 test_csd[EXT_CSD_PARTITIONING_SUPPORT]) &&
388 (ext_csd[EXT_CSD_ERASE_GROUP_DEF] ==
389 test_csd[EXT_CSD_ERASE_GROUP_DEF]) &&
390 (ext_csd[EXT_CSD_REV] ==
391 test_csd[EXT_CSD_REV]) &&
392 (ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] ==
393 test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]) &&
394 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
395 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
396 media->caps |= width;
397 break;
398 }
399 }
400 return err;
401}
402
403int mmc_update_capacity(struct storage_media *media)
404{
405 uint64_t capacity;
406 struct sd_mmc_ctrlr *ctrlr = media->ctrlr;
407 int err;
408 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, ext_csd, EXT_CSD_SIZE);
409 uint32_t erase_size;
410 uint32_t hc_erase_size;
411 uint64_t hc_wp_size;
412 int index;
413
414 if (media->version < MMC_VERSION_4)
415 return 0;
416
417 /* check ext_csd version and capacity */
418 err = mmc_send_ext_csd(ctrlr, ext_csd);
419 if (err)
420 return err;
421
422 if (ext_csd[EXT_CSD_REV] < 2)
423 return 0;
424
Lee Leahyeef40eb2017-03-23 10:54:57 -0700425 /* Determine the eMMC device information */
426 media->partition_config = ext_csd[EXT_CSD_PART_CONF]
427 & EXT_CSD_PART_ACCESS_MASK;
428
429 /* Determine the user partition size
430 *
431 * According to the JEDEC Standard, the value of
432 * ext_csd's capacity is valid if the value is
433 * more than 2GB
434 */
Lee Leahyf968a4c2017-06-27 09:28:35 -0700435 capacity = (uint32_t)(ext_csd[EXT_CSD_SEC_CNT + 0] << 0 |
Lee Leahyeef40eb2017-03-23 10:54:57 -0700436 ext_csd[EXT_CSD_SEC_CNT + 1] << 8 |
437 ext_csd[EXT_CSD_SEC_CNT + 2] << 16 |
438 ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
439 capacity *= 512;
440 if ((capacity >> 20) > 2 * 1024)
441 media->capacity[MMC_PARTITION_USER] = capacity;
442
443 /* Determine the boot parition sizes */
444 hc_erase_size = ext_csd[224] * 512 * KiB;
445 capacity = ext_csd[EXT_CSD_BOOT_SIZE_MULT] * 128 * KiB;
446 media->capacity[MMC_PARTITION_BOOT_1] = capacity;
447 media->capacity[MMC_PARTITION_BOOT_2] = capacity;
448
449 /* Determine the RPMB size */
450 hc_wp_size = ext_csd[EXT_CSD_HC_WP_GRP_SIZE] * hc_erase_size;
451 capacity = 128 * KiB * ext_csd[EXT_CSD_RPMB_SIZE_MULT];
452 media->capacity[MMC_PARTITION_RPMB] = capacity;
453
454 /* Determine the general partition sizes */
455 capacity = (ext_csd[EXT_CSD_GP_SIZE_MULT_GP0 + 2] << 16)
456 | (ext_csd[EXT_CSD_GP_SIZE_MULT_GP0 + 1] << 8)
457 | ext_csd[EXT_CSD_GP_SIZE_MULT_GP0];
458 capacity *= hc_wp_size;
459 media->capacity[MMC_PARTITION_GP1] = capacity;
460
461 capacity = (ext_csd[EXT_CSD_GP_SIZE_MULT_GP1 + 2] << 16)
462 | (ext_csd[EXT_CSD_GP_SIZE_MULT_GP1 + 1] << 8)
463 | ext_csd[EXT_CSD_GP_SIZE_MULT_GP1];
464 capacity *= hc_wp_size;
465 media->capacity[MMC_PARTITION_GP2] = capacity;
466
467 capacity = (ext_csd[EXT_CSD_GP_SIZE_MULT_GP2 + 2] << 16)
468 | (ext_csd[EXT_CSD_GP_SIZE_MULT_GP2 + 1] << 8)
469 | ext_csd[EXT_CSD_GP_SIZE_MULT_GP2];
470 capacity *= hc_wp_size;
471 media->capacity[MMC_PARTITION_GP3] = capacity;
472
473 capacity = (ext_csd[EXT_CSD_GP_SIZE_MULT_GP3 + 2] << 16)
474 | (ext_csd[EXT_CSD_GP_SIZE_MULT_GP3 + 1] << 8)
475 | ext_csd[EXT_CSD_GP_SIZE_MULT_GP3];
476 capacity *= hc_wp_size;
477 media->capacity[MMC_PARTITION_GP4] = capacity;
478
479 /* Determine the erase size */
480 erase_size = (sd_mmc_extract_uint32_bits(media->csd,
481 81, 5) + 1) *
482 (sd_mmc_extract_uint32_bits(media->csd, 86, 5)
483 + 1);
484 for (index = MMC_PARTITION_BOOT_1; index <= MMC_PARTITION_GP4;
485 index++) {
486 if (media->capacity[index] != 0) {
487 /* Enable the partitions */
488 err = mmc_switch(media, EXT_CSD_ERASE_GROUP_DEF,
489 EXT_CSD_PARTITION_ENABLE);
490 if (err) {
491 sdhc_error("Failed to enable partition access\n");
492 return err;
493 }
494
495 /* Use HC erase group size */
496 erase_size = hc_erase_size / media->write_bl_len;
497 break;
498 }
499 }
500 media->erase_blocks = erase_size;
501 media->trim_mult = ext_csd[EXT_CSD_TRIM_MULT];
502
503 return 0;
504}
505
506int mmc_set_partition(struct storage_media *media,
507 unsigned int partition_number)
508{
509 uint8_t partition_config;
510
511 /* Validate the partition number */
512 if ((partition_number > MMC_PARTITION_GP4)
513 || (!media->capacity[partition_number]))
514 return -1;
515
516 /* Update the partition register */
517 partition_config = media->partition_config;
518 partition_config &= ~EXT_CSD_PART_ACCESS_MASK;
519 partition_config |= partition_number;
520
521 /* Select the new partition */
522 int ret = mmc_switch(media, EXT_CSD_PART_CONF, partition_config);
523 if (!ret)
524 media->partition_config = partition_config;
525
526 return ret;
527}
528
529const char *mmc_partition_name(struct storage_media *media,
530 unsigned int partition_number)
531{
532 static const char * const partition_name[8] = {
533 "User", /* 0 */
534 "Boot 1", /* 1 */
535 "Boot 2", /* 2 */
536 "RPMB", /* 3 */
537 "GP 1", /* 4 */
538 "GP 2", /* 5 */
539 "GP 3", /* 6 */
540 "GP 4" /* 7 */
541 };
542
543 if (partition_number >= ARRAY_SIZE(partition_name))
544 return "";
545 return partition_name[partition_number];
546}