blob: 544436f449c164a27b67a0385c2eb0b36d9d787e [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2009 coresystems GmbH
5 * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
20 * MA 02110-1301 USA
21 */
22
23#include <types.h>
24#include <console/console.h>
25#include <arch/acpi.h>
26#include <arch/acpigen.h>
27#include <arch/cpu.h>
28#include <cpu/x86/msr.h>
29#include <cpu/intel/speedstep.h>
30#include <cpu/intel/turbo.h>
31#include <device/device.h>
Aaron Durbin76c37002012-10-30 09:03:43 -050032#include "haswell.h"
33#include "chip.h"
34
Duncan Laurie1ad55642013-03-07 14:08:04 -080035#include <southbridge/intel/lynxpoint/pch.h>
36
Aaron Durbin76c37002012-10-30 09:03:43 -050037static int get_cores_per_package(void)
38{
39 struct cpuinfo_x86 c;
40 struct cpuid_result result;
41 int cores = 1;
42
43 get_fms(&c, cpuid_eax(1));
44 if (c.x86 != 6)
45 return 1;
46
47 result = cpuid_ext(0xb, 1);
48 cores = result.ebx & 0xff;
49
50 return cores;
51}
52
53static int generate_cstate_entries(acpi_cstate_t *cstates,
54 int c1, int c2, int c3)
55{
56 int length, cstate_count = 0;
57
58 /* Count number of active C-states */
59 if (c1 > 0)
60 ++cstate_count;
61 if (c2 > 0)
62 ++cstate_count;
63 if (c3 > 0)
64 ++cstate_count;
65 if (!cstate_count)
66 return 0;
67
68 length = acpigen_write_package(cstate_count + 1);
69 length += acpigen_write_byte(cstate_count);
70
71 /* Add an entry if the level is enabled */
72 if (c1 > 0) {
73 cstates[c1].ctype = 1;
74 length += acpigen_write_CST_package_entry(&cstates[c1]);
75 }
76 if (c2 > 0) {
77 cstates[c2].ctype = 2;
78 length += acpigen_write_CST_package_entry(&cstates[c2]);
79 }
80 if (c3 > 0) {
81 cstates[c3].ctype = 3;
82 length += acpigen_write_CST_package_entry(&cstates[c3]);
83 }
84
85 acpigen_patch_len(length - 1);
86 return length;
87}
88
89static int generate_C_state_entries(void)
90{
91 struct cpu_info *info;
92 struct cpu_driver *cpu;
93 int len, lenif;
Edward O'Callaghan2c9d2cf2014-10-27 23:29:29 +110094 struct device *lapic;
Aaron Durbin76c37002012-10-30 09:03:43 -050095 struct cpu_intel_haswell_config *conf = NULL;
96
97 /* Find the SpeedStep CPU in the device tree using magic APIC ID */
98 lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
99 if (!lapic)
100 return 0;
101 conf = lapic->chip_info;
102 if (!conf)
103 return 0;
104
105 /* Find CPU map of supported C-states */
106 info = cpu_info();
107 if (!info)
108 return 0;
109 cpu = find_cpu_driver(info->cpu);
110 if (!cpu || !cpu->cstates)
111 return 0;
112
113 len = acpigen_emit_byte(0x14); /* MethodOp */
114 len += acpigen_write_len_f(); /* PkgLength */
115 len += acpigen_emit_namestring("_CST");
116 len += acpigen_emit_byte(0x00); /* No Arguments */
117
118 /* If running on AC power */
119 len += acpigen_emit_byte(0xa0); /* IfOp */
120 lenif = acpigen_write_len_f(); /* PkgLength */
121 lenif += acpigen_emit_namestring("PWRS");
122 lenif += acpigen_emit_byte(0xa4); /* ReturnOp */
123 lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
124 conf->c2_acpower, conf->c3_acpower);
125 acpigen_patch_len(lenif - 1);
126 len += lenif;
127
128 /* Else on battery power */
129 len += acpigen_emit_byte(0xa4); /* ReturnOp */
130 len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
131 conf->c2_battery, conf->c3_battery);
132 acpigen_patch_len(len - 1);
133 return len;
134}
135
136static acpi_tstate_t tss_table_fine[] = {
137 { 100, 1000, 0, 0x00, 0 },
138 { 94, 940, 0, 0x1f, 0 },
139 { 88, 880, 0, 0x1e, 0 },
140 { 82, 820, 0, 0x1d, 0 },
141 { 75, 760, 0, 0x1c, 0 },
142 { 69, 700, 0, 0x1b, 0 },
143 { 63, 640, 0, 0x1a, 0 },
144 { 57, 580, 0, 0x19, 0 },
145 { 50, 520, 0, 0x18, 0 },
146 { 44, 460, 0, 0x17, 0 },
147 { 38, 400, 0, 0x16, 0 },
148 { 32, 340, 0, 0x15, 0 },
149 { 25, 280, 0, 0x14, 0 },
150 { 19, 220, 0, 0x13, 0 },
151 { 13, 160, 0, 0x12, 0 },
152};
153
154static acpi_tstate_t tss_table_coarse[] = {
155 { 100, 1000, 0, 0x00, 0 },
156 { 88, 875, 0, 0x1f, 0 },
157 { 75, 750, 0, 0x1e, 0 },
158 { 63, 625, 0, 0x1d, 0 },
159 { 50, 500, 0, 0x1c, 0 },
160 { 38, 375, 0, 0x1b, 0 },
161 { 25, 250, 0, 0x1a, 0 },
162 { 13, 125, 0, 0x19, 0 },
163};
164
165static int generate_T_state_entries(int core, int cores_per_package)
166{
167 int len;
168
169 /* Indicate SW_ALL coordination for T-states */
170 len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
171
172 /* Indicate FFixedHW so OS will use MSR */
173 len += acpigen_write_empty_PTC();
174
175 /* Set a T-state limit that can be modified in NVS */
176 len += acpigen_write_TPC("\\TLVL");
177
178 /*
179 * CPUID.(EAX=6):EAX[5] indicates support
180 * for extended throttle levels.
181 */
182 if (cpuid_eax(6) & (1 << 5))
183 len += acpigen_write_TSS_package(
184 ARRAY_SIZE(tss_table_fine), tss_table_fine);
185 else
186 len += acpigen_write_TSS_package(
187 ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
188
189 return len;
190}
191
192static int calculate_power(int tdp, int p1_ratio, int ratio)
193{
194 u32 m;
195 u32 power;
196
197 /*
198 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
199 *
200 * Power = (ratio / p1_ratio) * m * tdp
201 */
202
203 m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
204 m = (m * m) / 1000;
205
206 power = ((ratio * 100000 / p1_ratio) / 100);
207 power *= (m / 100) * (tdp / 1000);
208 power /= 1000;
209
210 return (int)power;
211}
212
213static int generate_P_state_entries(int core, int cores_per_package)
214{
215 int len, len_pss;
216 int ratio_min, ratio_max, ratio_turbo, ratio_step;
217 int coord_type, power_max, power_unit, num_entries;
218 int ratio, power, clock, clock_max;
219 msr_t msr;
220
221 /* Determine P-state coordination type from MISC_PWR_MGMT[0] */
222 msr = rdmsr(MSR_MISC_PWR_MGMT);
223 if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
224 coord_type = SW_ANY;
225 else
226 coord_type = HW_ALL;
227
228 /* Get bus ratio limits and calculate clock speeds */
229 msr = rdmsr(MSR_PLATFORM_INFO);
230 ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
231
232 /* Determine if this CPU has configurable TDP */
233 if (cpu_config_tdp_levels()) {
234 /* Set max ratio to nominal TDP ratio */
235 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
236 ratio_max = msr.lo & 0xff;
237 } else {
238 /* Max Non-Turbo Ratio */
239 ratio_max = (msr.lo >> 8) & 0xff;
240 }
241 clock_max = ratio_max * HASWELL_BCLK;
242
243 /* Calculate CPU TDP in mW */
244 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
245 power_unit = 2 << ((msr.lo & 0xf) - 1);
246 msr = rdmsr(MSR_PKG_POWER_SKU);
247 power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
248
249 /* Write _PCT indicating use of FFixedHW */
250 len = acpigen_write_empty_PCT();
251
252 /* Write _PPC with no limit on supported P-state */
253 len += acpigen_write_PPC_NVS();
254
255 /* Write PSD indicating configured coordination type */
Duncan Laurie25b8b7b2013-04-19 10:02:23 -0700256 len += acpigen_write_PSD_package(core, 1, coord_type);
Aaron Durbin76c37002012-10-30 09:03:43 -0500257
258 /* Add P-state entries in _PSS table */
259 len += acpigen_write_name("_PSS");
260
261 /* Determine ratio points */
262 ratio_step = PSS_RATIO_STEP;
263 num_entries = (ratio_max - ratio_min) / ratio_step;
264 while (num_entries > PSS_MAX_ENTRIES-1) {
265 ratio_step <<= 1;
266 num_entries >>= 1;
267 }
268
269 /* P[T] is Turbo state if enabled */
270 if (get_turbo_state() == TURBO_ENABLED) {
271 /* _PSS package count including Turbo */
272 len_pss = acpigen_write_package(num_entries + 2);
273
274 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
275 ratio_turbo = msr.lo & 0xff;
276
277 /* Add entry for Turbo ratio */
278 len_pss += acpigen_write_PSS_package(
279 clock_max + 1, /*MHz*/
280 power_max, /*mW*/
281 PSS_LATENCY_TRANSITION, /*lat1*/
282 PSS_LATENCY_BUSMASTER, /*lat2*/
283 ratio_turbo << 8, /*control*/
284 ratio_turbo << 8); /*status*/
285 } else {
286 /* _PSS package count without Turbo */
287 len_pss = acpigen_write_package(num_entries + 1);
288 }
289
290 /* First regular entry is max non-turbo ratio */
291 len_pss += acpigen_write_PSS_package(
292 clock_max, /*MHz*/
293 power_max, /*mW*/
294 PSS_LATENCY_TRANSITION, /*lat1*/
295 PSS_LATENCY_BUSMASTER, /*lat2*/
296 ratio_max << 8, /*control*/
297 ratio_max << 8); /*status*/
298
299 /* Generate the remaining entries */
300 for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
301 ratio >= ratio_min; ratio -= ratio_step) {
302
303 /* Calculate power at this ratio */
304 power = calculate_power(power_max, ratio_max, ratio);
305 clock = ratio * HASWELL_BCLK;
306
307 len_pss += acpigen_write_PSS_package(
308 clock, /*MHz*/
309 power, /*mW*/
310 PSS_LATENCY_TRANSITION, /*lat1*/
311 PSS_LATENCY_BUSMASTER, /*lat2*/
312 ratio << 8, /*control*/
313 ratio << 8); /*status*/
314 }
315
316 /* Fix package length */
317 len_pss--;
318 acpigen_patch_len(len_pss);
319
320 return len + len_pss;
321}
322
323void generate_cpu_entries(void)
324{
325 int len_pr;
Duncan Laurie1ad55642013-03-07 14:08:04 -0800326 int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
Aaron Durbin76c37002012-10-30 09:03:43 -0500327 int totalcores = dev_count_cpu();
328 int cores_per_package = get_cores_per_package();
329 int numcpus = totalcores/cores_per_package;
330
331 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
332 numcpus, cores_per_package);
333
Martin Roth9944b282014-08-11 11:24:55 -0600334 for (cpuID = 1; cpuID <= numcpus; cpuID++) {
Aaron Durbin76c37002012-10-30 09:03:43 -0500335 for (coreID=1; coreID<=cores_per_package; coreID++) {
336 if (coreID>1) {
337 pcontrol_blk = 0;
338 plen = 0;
339 }
340
341 /* Generate processor \_PR.CPUx */
342 len_pr = acpigen_write_processor(
343 (cpuID-1)*cores_per_package+coreID-1,
344 pcontrol_blk, plen);
345
346 /* Generate P-state tables */
347 len_pr += generate_P_state_entries(
Duncan Laurie25b8b7b2013-04-19 10:02:23 -0700348 coreID-1, cores_per_package);
Aaron Durbin76c37002012-10-30 09:03:43 -0500349
350 /* Generate C-state tables */
351 len_pr += generate_C_state_entries();
352
353 /* Generate T-state tables */
354 len_pr += generate_T_state_entries(
355 cpuID-1, cores_per_package);
356
357 len_pr--;
358 acpigen_patch_len(len_pr);
359 }
360 }
361}
362
363struct chip_operations cpu_intel_haswell_ops = {
364 CHIP_NAME("Intel Haswell CPU")
365};