Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <device/pci_ops.h> |
| 25 | #include <device/smbus.h> |
| 26 | #include <pc80/mc146818rtc.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <cpu/x86/lapic.h> |
| 29 | #include <arch/ioapic.h> |
| 30 | #include <stdlib.h> |
| 31 | #include "hudson.h" |
| 32 | #include "smbus.c" |
| 33 | |
| 34 | #define NMI_OFF 0 |
| 35 | |
| 36 | #define MAINBOARD_POWER_OFF 0 |
| 37 | #define MAINBOARD_POWER_ON 1 |
| 38 | |
| 39 | #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 40 | #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON |
| 41 | #endif |
| 42 | |
| 43 | #define BIT0 (1 << 0) |
| 44 | #define BIT1 (1 << 1) |
| 45 | #define BIT2 (1 << 2) |
| 46 | #define BIT3 (1 << 3) |
| 47 | #define BIT4 (1 << 4) |
| 48 | #define BIT5 (1 << 5) |
| 49 | #define BIT6 (1 << 6) |
| 50 | #define BIT7 (1 << 7) |
| 51 | |
| 52 | #define BIT8 (1 << 8 ) |
| 53 | #define BIT9 (1 << 9 ) |
| 54 | #define BIT10 (1 << 10) |
| 55 | #define BIT11 (1 << 11) |
| 56 | #define BIT12 (1 << 12) |
| 57 | #define BIT13 (1 << 13) |
| 58 | #define BIT14 (1 << 14) |
| 59 | #define BIT15 (1 << 15) |
| 60 | |
| 61 | #define BIT16 (1 << 16) |
| 62 | #define BIT17 (1 << 17) |
| 63 | #define BIT18 (1 << 18) |
| 64 | #define BIT19 (1 << 19) |
| 65 | #define BIT20 (1 << 20) |
| 66 | #define BIT21 (1 << 21) |
| 67 | #define BIT22 (1 << 22) |
| 68 | #define BIT23 (1 << 23) |
| 69 | #define BIT24 (1 << 24) |
| 70 | #define BIT25 (1 << 25) |
| 71 | #define BIT26 (1 << 26) |
| 72 | #define BIT27 (1 << 27) |
| 73 | #define BIT28 (1 << 28) |
| 74 | #define BIT29 (1 << 29) |
| 75 | #define BIT30 (1 << 30) |
| 76 | #define BIT31 (1 << 31) |
| 77 | |
| 78 | /* |
| 79 | * HUDSON enables all USB controllers by default in SMBUS Control. |
| 80 | * HUDSON enables SATA by default in SMBUS Control. |
| 81 | */ |
| 82 | |
| 83 | static void sm_init(device_t dev) |
| 84 | { |
| 85 | setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS); |
| 86 | } |
| 87 | |
| 88 | static int lsmbus_recv_byte(device_t dev) |
| 89 | { |
| 90 | u32 device; |
| 91 | struct resource *res; |
| 92 | struct bus *pbus; |
| 93 | |
| 94 | device = dev->path.i2c.device; |
| 95 | pbus = get_pbus_smbus(dev); |
| 96 | |
| 97 | res = find_resource(pbus->dev, 0x90); |
| 98 | |
| 99 | return do_smbus_recv_byte(res->base, device); |
| 100 | } |
| 101 | |
| 102 | static int lsmbus_send_byte(device_t dev, u8 val) |
| 103 | { |
| 104 | u32 device; |
| 105 | struct resource *res; |
| 106 | struct bus *pbus; |
| 107 | |
| 108 | device = dev->path.i2c.device; |
| 109 | pbus = get_pbus_smbus(dev); |
| 110 | |
| 111 | res = find_resource(pbus->dev, 0x90); |
| 112 | |
| 113 | return do_smbus_send_byte(res->base, device, val); |
| 114 | } |
| 115 | |
| 116 | static int lsmbus_read_byte(device_t dev, u8 address) |
| 117 | { |
| 118 | u32 device; |
| 119 | struct resource *res; |
| 120 | struct bus *pbus; |
| 121 | |
| 122 | device = dev->path.i2c.device; |
| 123 | pbus = get_pbus_smbus(dev); |
| 124 | |
| 125 | res = find_resource(pbus->dev, 0x90); |
| 126 | |
| 127 | return do_smbus_read_byte(res->base, device, address); |
| 128 | } |
| 129 | |
| 130 | static int lsmbus_write_byte(device_t dev, u8 address, u8 val) |
| 131 | { |
| 132 | u32 device; |
| 133 | struct resource *res; |
| 134 | struct bus *pbus; |
| 135 | |
| 136 | device = dev->path.i2c.device; |
| 137 | pbus = get_pbus_smbus(dev); |
| 138 | |
| 139 | res = find_resource(pbus->dev, 0x90); |
| 140 | |
| 141 | return do_smbus_write_byte(res->base, device, address, val); |
| 142 | } |
| 143 | static struct smbus_bus_operations lops_smbus_bus = { |
| 144 | .recv_byte = lsmbus_recv_byte, |
| 145 | .send_byte = lsmbus_send_byte, |
| 146 | .read_byte = lsmbus_read_byte, |
| 147 | .write_byte = lsmbus_write_byte, |
| 148 | }; |
| 149 | |
| 150 | static void hudson_sm_read_resources(device_t dev) |
| 151 | { |
| 152 | } |
| 153 | |
| 154 | static void hudson_sm_set_resources(struct device *dev) |
| 155 | { |
| 156 | } |
| 157 | |
| 158 | static struct pci_operations lops_pci = { |
| 159 | .set_subsystem = pci_dev_set_subsystem, |
| 160 | }; |
| 161 | static struct device_operations smbus_ops = { |
| 162 | .read_resources = hudson_sm_read_resources, |
| 163 | .set_resources = hudson_sm_set_resources, |
| 164 | .enable_resources = pci_dev_enable_resources, |
| 165 | .init = sm_init, |
| 166 | .scan_bus = scan_static_bus, |
| 167 | .ops_pci = &lops_pci, |
| 168 | .ops_smbus_bus = &lops_smbus_bus, |
| 169 | }; |
| 170 | static const struct pci_driver smbus_driver __pci_driver = { |
| 171 | .ops = &smbus_ops, |
| 172 | .vendor = PCI_VENDOR_ID_AMD, |
| 173 | .device = PCI_DEVICE_ID_ATI_SB900_SM, |
| 174 | }; |