Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <delay.h> |
| 27 | #include <broadwell/iobp.h> |
| 28 | #include <broadwell/ramstage.h> |
| 29 | #include <broadwell/rcba.h> |
| 30 | #include <broadwell/sata.h> |
| 31 | #include <chip.h> |
| 32 | |
| 33 | static inline u32 sir_read(struct device *dev, int idx) |
| 34 | { |
| 35 | pci_write_config32(dev, SATA_SIRI, idx); |
| 36 | return pci_read_config32(dev, SATA_SIRD); |
| 37 | } |
| 38 | |
| 39 | static inline void sir_write(struct device *dev, int idx, u32 value) |
| 40 | { |
| 41 | pci_write_config32(dev, SATA_SIRI, idx); |
| 42 | pci_write_config32(dev, SATA_SIRD, value); |
| 43 | } |
| 44 | |
| 45 | static void sata_init(struct device *dev) |
| 46 | { |
| 47 | config_t *config = dev->chip_info; |
| 48 | u32 reg32, abar; |
| 49 | u16 reg16; |
| 50 | |
| 51 | printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n"); |
| 52 | |
| 53 | /* Enable BARs */ |
| 54 | pci_write_config16(dev, PCI_COMMAND, 0x0007); |
| 55 | |
| 56 | /* Set Interrupt Line */ |
| 57 | /* Interrupt Pin is set by D31IP.PIP */ |
| 58 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0x0a); |
| 59 | |
| 60 | /* Set timings */ |
| 61 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 62 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 63 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 64 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 65 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 66 | |
| 67 | /* Sync DMA */ |
| 68 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); |
| 69 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); |
| 70 | |
| 71 | /* Set IDE I/O Configuration */ |
| 72 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
| 73 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 74 | |
| 75 | /* for AHCI, Port Enable is managed in memory mapped space */ |
| 76 | reg16 = pci_read_config16(dev, 0x92); |
| 77 | reg16 &= ~0x3f; |
| 78 | reg16 |= 0x8000 | config->sata_port_map; |
| 79 | pci_write_config16(dev, 0x92, reg16); |
| 80 | udelay(2); |
| 81 | |
| 82 | /* Setup register 98h */ |
| 83 | reg32 = pci_read_config16(dev, 0x98); |
| 84 | reg32 |= 1 << 19; /* BWG step 6 */ |
| 85 | reg32 |= 1 << 22; /* BWG step 5 */ |
| 86 | reg32 &= ~(0x3f << 7); |
| 87 | reg32 |= 0x04 << 7; /* BWG step 7 */ |
| 88 | reg32 |= 1 << 20; /* BWG step 8 */ |
| 89 | reg32 &= ~(0x03 << 5); |
| 90 | reg32 |= 1 << 5; /* BWG step 9 */ |
| 91 | reg32 |= 1 << 18; /* BWG step 10 */ |
| 92 | reg32 |= 1 << 29; /* BWG step 11 */ |
| 93 | reg32 &= ~((1 << 31) | (1 << 30)); |
| 94 | reg32 |= 1 << 23; |
| 95 | reg32 |= 1 << 24; /* Disable listen mode (hotplug) */ |
| 96 | pci_write_config32(dev, 0x98, reg32); |
| 97 | |
| 98 | /* Setup register 9Ch */ |
| 99 | reg16 = 0; /* Disable alternate ID */ |
| 100 | reg16 = 1 << 5; /* BWG step 12 */ |
| 101 | pci_write_config16(dev, 0x9c, reg16); |
| 102 | |
| 103 | /* SATA Initialization register */ |
| 104 | reg32 = 0x183; |
| 105 | reg32 |= (config->sata_port_map ^ 0x3f) << 24; |
| 106 | reg32 |= (config->sata_devslp_mux & 1) << 15; |
| 107 | pci_write_config32(dev, 0x94, reg32); |
| 108 | |
| 109 | /* Initialize AHCI memory-mapped space */ |
| 110 | abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 111 | printk(BIOS_DEBUG, "ABAR: %08X\n", abar); |
| 112 | |
| 113 | /* CAP (HBA Capabilities) : enable power management */ |
| 114 | reg32 = read32(abar + 0x00); |
| 115 | reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS |
| 116 | reg32 &= ~0x00020060; // clear SXS+EMS+PMS |
| 117 | reg32 |= (1 << 18); // SAM: SATA AHCI MODE ONLY |
| 118 | write32(abar + 0x00, reg32); |
| 119 | |
| 120 | /* PI (Ports implemented) */ |
| 121 | write32(abar + 0x0c, config->sata_port_map); |
| 122 | (void) read32(abar + 0x0c); /* Read back 1 */ |
| 123 | (void) read32(abar + 0x0c); /* Read back 2 */ |
| 124 | |
| 125 | /* CAP2 (HBA Capabilities Extended)*/ |
| 126 | reg32 = read32(abar + 0x24); |
| 127 | |
| 128 | /* |
| 129 | * Static Power Gating for unused ports |
| 130 | */ |
| 131 | reg32 = RCBA32(0x3a84); |
| 132 | /* Port 3 and 2 disabled */ |
| 133 | if ((config->sata_port_map & ((1 << 3)|(1 << 2))) == 0) |
| 134 | reg32 |= (1 << 24) | (1 << 26); |
| 135 | /* Port 1 and 0 disabled */ |
| 136 | if ((config->sata_port_map & ((1 << 1)|(1 << 0))) == 0) |
| 137 | reg32 |= (1 << 20) | (1 << 18); |
| 138 | RCBA32(0x3a84) = reg32; |
| 139 | |
| 140 | /* Enable DEVSLP */ |
| 141 | if (config->sata_devslp_disable) |
| 142 | reg32 &= ~(1 << 3); |
| 143 | else |
| 144 | reg32 |= (1 << 5)|(1 << 4)|(1 << 3)|(1 << 2); |
| 145 | write32(abar + 0x24, reg32); |
| 146 | |
| 147 | /* Set Gen3 Transmitter settings if needed */ |
| 148 | if (config->sata_port0_gen3_tx) |
| 149 | pch_iobp_update(SATA_IOBP_SP0G3IR, 0, |
| 150 | config->sata_port0_gen3_tx); |
| 151 | |
| 152 | if (config->sata_port1_gen3_tx) |
| 153 | pch_iobp_update(SATA_IOBP_SP1G3IR, 0, |
| 154 | config->sata_port1_gen3_tx); |
| 155 | |
| 156 | /* Set Gen3 DTLE DATA / EDGE registers if needed */ |
| 157 | if (config->sata_port0_gen3_dtle) { |
| 158 | pch_iobp_update(SATA_IOBP_SP0DTLE_DATA, |
| 159 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 160 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 161 | << SATA_DTLE_DATA_SHIFT); |
| 162 | |
| 163 | pch_iobp_update(SATA_IOBP_SP0DTLE_EDGE, |
| 164 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 165 | (config->sata_port0_gen3_dtle & SATA_DTLE_MASK) |
| 166 | << SATA_DTLE_EDGE_SHIFT); |
| 167 | } |
| 168 | |
| 169 | if (config->sata_port1_gen3_dtle) { |
| 170 | pch_iobp_update(SATA_IOBP_SP1DTLE_DATA, |
| 171 | ~(SATA_DTLE_MASK << SATA_DTLE_DATA_SHIFT), |
| 172 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 173 | << SATA_DTLE_DATA_SHIFT); |
| 174 | |
| 175 | pch_iobp_update(SATA_IOBP_SP1DTLE_EDGE, |
| 176 | ~(SATA_DTLE_MASK << SATA_DTLE_EDGE_SHIFT), |
| 177 | (config->sata_port1_gen3_dtle & SATA_DTLE_MASK) |
| 178 | << SATA_DTLE_EDGE_SHIFT); |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * Additional Programming Requirements for Power Optimizer |
| 183 | */ |
| 184 | |
| 185 | /* Step 1 */ |
| 186 | sir_write(dev, 0x64, 0x883c9003); |
| 187 | |
| 188 | /* Step 2: SIR 68h[15:0] = 880Ah */ |
| 189 | reg32 = sir_read(dev, 0x68); |
| 190 | reg32 &= 0xffff0000; |
| 191 | reg32 |= 0x880a; |
| 192 | sir_write(dev, 0x68, reg32); |
| 193 | |
| 194 | /* Step 3: SIR 60h[3] = 1 */ |
| 195 | reg32 = sir_read(dev, 0x60); |
| 196 | reg32 |= (1 << 3); |
| 197 | sir_write(dev, 0x60, reg32); |
| 198 | |
| 199 | /* Step 4: SIR 60h[0] = 1 */ |
| 200 | reg32 = sir_read(dev, 0x60); |
| 201 | reg32 |= (1 << 0); |
| 202 | sir_write(dev, 0x60, reg32); |
| 203 | |
| 204 | /* Step 5: SIR 60h[1] = 1 */ |
| 205 | reg32 = sir_read(dev, 0x60); |
| 206 | reg32 |= (1 << 1); |
| 207 | sir_write(dev, 0x60, reg32); |
| 208 | |
| 209 | /* Clock Gating */ |
| 210 | sir_write(dev, 0x70, 0x3f00bf1f); |
| 211 | sir_write(dev, 0x54, 0xcf000f0f); |
| 212 | sir_write(dev, 0x58, 0x00190000); |
| 213 | |
| 214 | reg32 = pci_read_config32(dev, 0x300); |
| 215 | reg32 |= (1 << 17) | (1 << 16); |
| 216 | reg32 |= (1 << 31) | (1 << 30) | (1 << 29); |
| 217 | pci_write_config32(dev, 0x300, reg32); |
| 218 | } |
| 219 | |
| 220 | /* |
| 221 | * Set SATA controller mode early so the resource allocator can |
| 222 | * properly assign IO/Memory resources for the controller. |
| 223 | */ |
| 224 | static void sata_enable(device_t dev) |
| 225 | { |
| 226 | /* Get the chip configuration */ |
| 227 | config_t *config = dev->chip_info; |
| 228 | u16 map = 0x0060; |
| 229 | |
| 230 | map |= (config->sata_port_map ^ 0x3f) << 8; |
| 231 | |
| 232 | pci_write_config16(dev, 0x90, map); |
| 233 | } |
| 234 | |
| 235 | static struct device_operations sata_ops = { |
| 236 | .read_resources = &pci_dev_read_resources, |
| 237 | .set_resources = &pci_dev_set_resources, |
| 238 | .enable_resources = &pci_dev_enable_resources, |
| 239 | .init = &sata_init, |
| 240 | .enable = &sata_enable, |
| 241 | .ops_pci = &broadwell_pci_ops, |
| 242 | }; |
| 243 | |
| 244 | static const unsigned short pci_device_ids[] = { |
| 245 | 0x9c03, 0x9c05, 0x9c07, 0x9c0f, /* LynxPoint-LP */ |
| 246 | 0x9c83, 0x9c85, 0x282a, 0x9c87, 0x282a, 0x9c8f, /* WildcatPoint */ |
| 247 | 0 |
| 248 | }; |
| 249 | |
| 250 | static const struct pci_driver pch_sata __pci_driver = { |
| 251 | .ops = &sata_ops, |
| 252 | .vendor = PCI_VENDOR_ID_INTEL, |
| 253 | .devices = pci_device_ids, |
| 254 | }; |