Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <stdlib.h> |
| 23 | #include <console/console.h> |
| 24 | #include <arch/io.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 25 | #include <device/pci_def.h> |
| 26 | #include <elog.h> |
| 27 | #include "haswell.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 28 | |
| 29 | static void haswell_setup_bars(void) |
| 30 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 32 | /* Set up all hardcoded northbridge BARs */ |
| 33 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 34 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); |
| 35 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); |
| 36 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); |
| 38 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32); |
| 39 | |
| 40 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 41 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); |
| 42 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); |
| 43 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); |
| 44 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); |
| 45 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); |
| 46 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); |
| 47 | pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); |
| 48 | |
| 49 | printk(BIOS_DEBUG, " done.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 50 | } |
| 51 | |
| 52 | static void haswell_setup_graphics(void) |
| 53 | { |
| 54 | u32 reg32; |
| 55 | u16 reg16; |
| 56 | u8 reg8; |
| 57 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | printk(BIOS_DEBUG, "Initializing Graphics...\n"); |
| 59 | |
| 60 | /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ |
| 61 | reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC); |
| 62 | reg16 &= ~0x00f8; |
| 63 | reg16 |= 1 << 3; |
| 64 | /* Program GTT memory by setting GGC[9:8] = 2MB */ |
| 65 | reg16 &= ~0x0300; |
| 66 | reg16 |= 2 << 8; |
| 67 | /* Enable VGA decode */ |
| 68 | reg16 &= ~0x0002; |
| 69 | pci_write_config16(PCI_DEV(0,0,0), GGC, reg16); |
| 70 | |
| 71 | /* Enable 256MB aperture */ |
| 72 | reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC); |
| 73 | reg8 &= ~0x06; |
| 74 | reg8 |= 0x02; |
| 75 | pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); |
| 76 | |
| 77 | /* Erratum workarounds */ |
| 78 | reg32 = MCHBAR32(0x5f00); |
| 79 | reg32 |= (1 << 9)|(1 << 10); |
| 80 | MCHBAR32(0x5f00) = reg32; |
| 81 | |
| 82 | /* Enable SA Clock Gating */ |
| 83 | reg32 = MCHBAR32(0x5f00); |
| 84 | MCHBAR32(0x5f00) = reg32 | 1; |
| 85 | |
| 86 | /* GPU RC6 workaround for sighting 366252 */ |
| 87 | reg32 = MCHBAR32(0x5d14); |
| 88 | reg32 |= (1 << 31); |
| 89 | MCHBAR32(0x5d14) = reg32; |
| 90 | |
| 91 | /* VLW */ |
| 92 | reg32 = MCHBAR32(0x6120); |
| 93 | reg32 &= ~(1 << 0); |
| 94 | MCHBAR32(0x6120) = reg32; |
| 95 | |
| 96 | reg32 = MCHBAR32(0x5418); |
| 97 | reg32 |= (1 << 4) | (1 << 5); |
| 98 | MCHBAR32(0x5418) = reg32; |
| 99 | } |
| 100 | |
| 101 | void haswell_early_initialization(int chipset_type) |
| 102 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 103 | /* Setup all BARs required for early PCIe and raminit */ |
| 104 | haswell_setup_bars(); |
| 105 | |
Duncan Laurie | 0a7c49e | 2013-06-20 12:40:55 -0700 | [diff] [blame] | 106 | /* Device Enable: IGD and Mini-HD Audio */ |
| 107 | pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, |
| 108 | DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 109 | |
| 110 | haswell_setup_graphics(); |
| 111 | } |