Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <console/console.h> |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | |
| 26 | static void pci_init(struct device *dev) |
| 27 | { |
| 28 | u16 reg16; |
| 29 | |
| 30 | #if 0 |
| 31 | /* Commented out for now because it will break on some machines. */ |
| 32 | /* Set latency timer to 32. */ |
| 33 | pci_write_config16(dev, 0x1b, 0x20); |
| 34 | #endif |
| 35 | |
| 36 | /* disable parity error response */ |
| 37 | reg16 = pci_read_config16(dev, 0x3e); |
| 38 | reg16 &= ~(1 << 0); |
| 39 | pci_write_config16(dev, 0x3e, reg16); |
| 40 | |
| 41 | /* Clear errors in status registers */ |
| 42 | reg16 = pci_read_config16(dev, 0x06); |
| 43 | reg16 |= 0xf900; |
| 44 | pci_write_config16(dev, 0x06, reg16); |
| 45 | |
| 46 | reg16 = pci_read_config16(dev, 0x1e); |
| 47 | reg16 |= 0xf900; |
| 48 | pci_write_config16(dev, 0x1e, reg16); |
| 49 | } |
| 50 | |
| 51 | static void ich_pci_dev_enable_resources(struct device *dev) |
| 52 | { |
| 53 | const struct pci_operations *ops; |
| 54 | uint16_t command; |
| 55 | |
| 56 | /* Set the subsystem vendor and device id for mainboard devices */ |
| 57 | ops = ops_pci(dev); |
| 58 | if (dev->on_mainboard && ops && ops->set_subsystem) { |
| 59 | printk_debug("%s subsystem <- %02x/%02x\n", |
| 60 | dev_path(dev), |
| 61 | MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, |
| 62 | MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); |
| 63 | ops->set_subsystem(dev, |
| 64 | MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID, |
| 65 | MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID); |
| 66 | } |
| 67 | |
| 68 | #if 0 |
| 69 | /* If we write to PCI_COMMAND, on some systems |
| 70 | * this will cause the ROM and APICs not being visible |
| 71 | * anymore. |
| 72 | */ |
| 73 | command = pci_read_config16(dev, PCI_COMMAND); |
| 74 | command |= dev->command; |
| 75 | printk_debug("%s cmd <- %02x\n", dev_path(dev), command); |
| 76 | pci_write_config16(dev, PCI_COMMAND, command); |
| 77 | #endif |
| 78 | } |
| 79 | |
| 80 | static void ich_pci_bus_enable_resources(struct device *dev) |
| 81 | { |
| 82 | uint16_t ctrl; |
| 83 | /* enable IO in command register if there is VGA card |
| 84 | * connected with (even it does not claim IO resource) |
| 85 | */ |
| 86 | if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 87 | dev->command |= PCI_COMMAND_IO; |
| 88 | ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); |
| 89 | ctrl |= dev->link[0].bridge_ctrl; |
| 90 | ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */ |
| 91 | printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); |
| 92 | pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); |
| 93 | |
| 94 | /* This is the reason we need our own pci_bus_enable_resources */ |
| 95 | ich_pci_dev_enable_resources(dev); |
| 96 | |
| 97 | enable_childrens_resources(dev); |
| 98 | } |
| 99 | |
| 100 | static void set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 101 | { |
| 102 | #if 0 |
| 103 | /* Currently disabled because it causes a "BAR 9" memory resource |
| 104 | * conflict: |
| 105 | */ |
| 106 | u32 pci_id; |
| 107 | |
| 108 | printk_debug("Setting PCI bridge subsystem ID\n"); |
| 109 | pci_id = pci_read_config32(dev, 0); |
| 110 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_id ); |
| 111 | #endif |
| 112 | } |
| 113 | |
| 114 | static struct pci_operations pci_ops = { |
| 115 | .set_subsystem = set_subsystem, |
| 116 | }; |
| 117 | |
| 118 | static struct device_operations device_ops = { |
| 119 | .read_resources = pci_bus_read_resources, |
| 120 | .set_resources = pci_dev_set_resources, |
| 121 | .enable_resources = ich_pci_bus_enable_resources, |
| 122 | .init = pci_init, |
| 123 | .scan_bus = pci_scan_bridge, |
| 124 | .ops_pci = &pci_ops, |
| 125 | }; |
| 126 | |
| 127 | |
| 128 | /* Desktop */ |
| 129 | static const struct pci_driver i82801g_pci __pci_driver = { |
| 130 | .ops = &device_ops, |
| 131 | .vendor = 0x8086, |
| 132 | .device = 0x244e, |
| 133 | }; |
| 134 | |
| 135 | /* Mobile / Ultra Mobile */ |
| 136 | static const struct pci_driver i82801gmu_pci __pci_driver = { |
| 137 | .ops = &device_ops, |
| 138 | .vendor = 0x8086, |
| 139 | .device = 0x2448, |
| 140 | }; |
| 141 | |