| Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2014 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <stdint.h> |
| 23 | #include <string.h> |
| 24 | #include <console/console.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <lib.h> |
| 27 | #include <cpu/x86/lapic.h> |
| 28 | #include <timestamp.h> |
| 29 | #include "sandybridge.h" |
| 30 | #include <cpu/x86/bist.h> |
| 31 | #include <cpu/intel/romstage.h> |
| 32 | #include "raminit_native.h" |
| 33 | #include "southbridge/intel/bd82x6x/pch.h" |
| 34 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 35 | |
| 36 | void main(unsigned long bist) |
| 37 | { |
| 38 | int s3resume = 0; |
| 39 | spd_raw_data spd[4]; |
| 40 | |
| 41 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 42 | outb(0x6, 0xcf9); |
| 43 | hlt (); |
| 44 | } |
| 45 | |
| 46 | timestamp_init(get_initial_timestamp()); |
| 47 | timestamp_add_now(TS_START_ROMSTAGE); |
| 48 | |
| 49 | if (bist == 0) |
| 50 | enable_lapic(); |
| 51 | |
| 52 | pch_enable_lpc(); |
| 53 | |
| 54 | /* Enable GPIOs */ |
| 55 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 56 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 57 | |
| 58 | setup_pch_gpios(&mainboard_gpio_map); |
| 59 | |
| 60 | early_usb_init(mainboard_usb_ports); |
| 61 | |
| 62 | /* Initialize console device(s) */ |
| 63 | console_init(); |
| 64 | |
| 65 | /* Halt if there was a built in self test failure */ |
| 66 | report_bist_failure(bist); |
| 67 | |
| 68 | /* Perform some early chipset initialization required |
| 69 | * before RAM initialization can work |
| 70 | */ |
| 71 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 72 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 73 | |
| 74 | s3resume = southbridge_detect_s3_resume(); |
| 75 | |
| 76 | post_code(0x38); |
| 77 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 78 | enable_smbus(); |
| 79 | |
| 80 | post_code(0x39); |
| 81 | |
| 82 | post_code(0x3a); |
| 83 | |
| 84 | memset (spd, 0, sizeof (spd)); |
| 85 | mainboard_get_spd(spd); |
| 86 | |
| 87 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 88 | |
| 89 | init_dram_ddr3(spd, 1, TCK_800MHZ, s3resume); |
| 90 | |
| 91 | timestamp_add_now(TS_AFTER_INITRAM); |
| 92 | post_code(0x3c); |
| 93 | |
| Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 94 | southbridge_configure_default_intmap(); |
| Vladimir Serbinenko | fa1d688 | 2014-10-19 02:50:45 +0200 | [diff] [blame] | 95 | rcba_config(); |
| 96 | post_code(0x3d); |
| 97 | |
| 98 | northbridge_romstage_finalize(s3resume); |
| 99 | |
| 100 | post_code(0x3f); |
| 101 | timestamp_add_now(TS_END_ROMSTAGE); |
| 102 | } |