Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 22 | #define RAMINIT_SYSINFO 1 |
| 23 | |
| 24 | #define K8_ALLOCATE_IO_RANGE 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 25 | |
| 26 | #define QRANK_DIMM_SUPPORT 1 |
| 27 | |
| 28 | #if CONFIG_LOGICAL_CPUS==1 |
| 29 | #define SET_NB_CFG_54 1 |
| 30 | #endif |
| 31 | |
| 32 | //used by init_cpus and fidvid |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 33 | #define SET_FIDVID 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 34 | //if we want to wait for core1 done before DQS training, set it to 0 |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 35 | #define SET_FIDVID_CORE0_ONLY 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 36 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 37 | #if CONFIG_K8_REV_F_SUPPORT == 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 38 | #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 |
| 39 | #endif |
| 40 | |
| 41 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 42 | #include <string.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 43 | #include <device/pci_def.h> |
| 44 | #include <device/pci_ids.h> |
| 45 | #include <arch/io.h> |
| 46 | #include <device/pnp_def.h> |
| 47 | #include <arch/romcc_io.h> |
| 48 | #include <cpu/x86/lapic.h> |
| 49 | #include "option_table.h" |
| 50 | #include "pc80/mc146818rtc_early.c" |
| 51 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 52 | #include "pc80/serial.c" |
Stefan Reinauer | 5a1f597 | 2010-03-31 14:34:40 +0000 | [diff] [blame] | 53 | #include "console/console.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 54 | #include "lib/ramtest.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 55 | |
| 56 | #include <cpu/amd/model_fxx_rev.h> |
| 57 | |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame^] | 58 | // for enable the FAN |
| 59 | #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 60 | #include "northbridge/amd/amdk8/raminit.h" |
| 61 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 62 | #include "lib/delay.c" |
| 63 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 64 | #include "cpu/x86/lapic/boot_cpu.c" |
| 65 | #include "northbridge/amd/amdk8/reset_test.c" |
| 66 | #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| 67 | #include "superio/winbond/w83627hf/w83627hf_early_init.c" |
| 68 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 69 | #include "cpu/x86/bist.h" |
| 70 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 71 | #include "northbridge/amd/amdk8/debug.c" |
| 72 | |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 73 | #include "cpu/x86/mtrr/earlymtrr.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 74 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 75 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 76 | |
| 77 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 78 | |
| 79 | #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" |
| 80 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 81 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 82 | { |
| 83 | } |
| 84 | |
| 85 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 86 | { |
| 87 | /* nothing to do */ |
| 88 | } |
| 89 | |
| 90 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 91 | { |
| 92 | return smbus_read_byte(device, address); |
| 93 | } |
| 94 | |
| 95 | #include "northbridge/amd/amdk8/amdk8_f.h" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 96 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 97 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 98 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 99 | #include "lib/generic_sdram.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 100 | |
| 101 | #include "resourcemap.c" |
| 102 | |
| 103 | #include "cpu/amd/dualcore/dualcore.c" |
| 104 | |
| 105 | #define MCP55_NUM 1 |
| 106 | #define MCP55_USE_NIC 1 |
| 107 | #define MCP55_USE_AZA 1 |
| 108 | |
| 109 | #define MCP55_PCI_E_X_0 4 |
| 110 | |
| 111 | #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" |
| 112 | #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" |
| 113 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 114 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 115 | |
| 116 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 117 | |
| 118 | #include "cpu/amd/model_fxx/fidvid.c" |
| 119 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 120 | #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" |
| 121 | #include "northbridge/amd/amdk8/early_ht.c" |
| 122 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 123 | static void sio_setup(void) |
| 124 | { |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 125 | uint32_t dword; |
| 126 | uint8_t byte; |
| 127 | enable_smbus(); |
| 128 | // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ |
| 129 | smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ |
| 130 | |
| 131 | byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); |
| 132 | byte |= 0x20; |
| 133 | pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); |
| 134 | |
| 135 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); |
| 136 | dword |= (1<<0); |
| 137 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); |
| 138 | |
| 139 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); |
| 140 | dword |= (1<<16); |
| 141 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 142 | } |
| 143 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 144 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 145 | { |
| 146 | static const uint16_t spd_addr [] = { |
Stefan Reinauer | 523ebd9 | 2010-04-14 18:59:42 +0000 | [diff] [blame] | 147 | // Node 0 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 148 | (0xa<<3)|0, (0xa<<3)|2, 0, 0, |
| 149 | (0xa<<3)|1, (0xa<<3)|3, 0, 0, |
Stefan Reinauer | 523ebd9 | 2010-04-14 18:59:42 +0000 | [diff] [blame] | 150 | // Node 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 151 | (0xa<<3)|4, (0xa<<3)|6, 0, 0, |
| 152 | (0xa<<3)|5, (0xa<<3)|7, 0, 0, |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 153 | }; |
| 154 | |
Stefan Reinauer | 523ebd9 | 2010-04-14 18:59:42 +0000 | [diff] [blame] | 155 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE |
| 156 | + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 157 | |
| 158 | int needs_reset = 0; |
| 159 | unsigned bsp_apicid = 0; |
| 160 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 161 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 162 | /* Nothing special needs to be done to find bus 0 */ |
| 163 | /* Allow the HT devices to be found */ |
| 164 | |
| 165 | enumerate_ht_chain(); |
| 166 | |
| 167 | sio_setup(); |
| 168 | |
| 169 | /* Setup the mcp55 */ |
| 170 | mcp55_enable_rom(); |
| 171 | } |
| 172 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 173 | if (bist == 0) { |
| 174 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 175 | } |
| 176 | |
| 177 | pnp_enter_ext_func_mode(SERIAL_DEV); |
| 178 | pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 179 | w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 180 | pnp_exit_ext_func_mode(SERIAL_DEV); |
| 181 | |
| 182 | uart_init(); |
| 183 | console_init(); |
| 184 | |
| 185 | /* Halt if there was a built in self test failure */ |
| 186 | report_bist_failure(bist); |
| 187 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 188 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 189 | |
| 190 | setup_mb_resource_map(); |
| 191 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 192 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 193 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 194 | #if CONFIG_MEM_TRAIN_SEQ == 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 195 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
| 196 | #endif |
| 197 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 198 | |
| 199 | wait_all_core0_started(); |
| 200 | #if CONFIG_LOGICAL_CPUS==1 |
| 201 | // It is said that we should start core1 after all core0 launched |
| 202 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 203 | * So here need to make sure last core0 is started, esp for two way system, |
| 204 | * (there may be apic id conflicts in that case) |
| 205 | */ |
| 206 | start_other_cores(); |
| 207 | wait_all_other_cores_started(bsp_apicid); |
| 208 | #endif |
| 209 | |
| 210 | /* it will set up chains and store link pair for optimization later */ |
| 211 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 212 | |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 213 | #if SET_FIDVID == 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 214 | { |
| 215 | msr_t msr; |
| 216 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame^] | 217 | printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | enable_fid_change(); |
| 221 | |
| 222 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 223 | |
| 224 | init_fidvid_bsp(bsp_apicid); |
| 225 | |
| 226 | // show final fid and vid |
| 227 | { |
| 228 | msr_t msr; |
| 229 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame^] | 230 | printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 231 | } |
| 232 | #endif |
| 233 | |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame^] | 234 | init_timer(); // Need to use TMICT to synconize FID/VID |
| 235 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 236 | needs_reset |= optimize_link_coherent_ht(); |
| 237 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 238 | needs_reset |= mcp55_early_setup_x(); |
| 239 | |
| 240 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 241 | if (needs_reset) { |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 242 | print_info("ht reset -\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 243 | soft_reset(); |
| 244 | } |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame^] | 245 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 246 | allow_all_aps_stop(bsp_apicid); |
| 247 | |
| 248 | //It's the time to set ctrl in sysinfo now; |
| 249 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 250 | |
| 251 | // enable_smbus(); /* enable in sio_setup */ |
| 252 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 253 | /* all ap stopped? */ |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 254 | |
| 255 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 256 | |
| 257 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 258 | } |