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huang linc14b54d2016-03-02 18:38:40 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2016 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
huang linc14b54d2016-03-02 18:38:40 +080014 */
15
Kyösti Mälkki13f66502019-03-03 08:01:05 +020016#include <device/mmio.h>
huang linc14b54d2016-03-02 18:38:40 +080017#include <bootblock_common.h>
Shunqian Zheng5dae9302016-04-13 22:43:35 +080018#include <soc/grf.h>
Lin Huangfe7aa202016-03-19 22:44:39 +080019#include <soc/mmu_operations.h>
Lin Huanga1f82a32016-03-09 18:08:20 +080020#include <soc/clock.h>
huang linc14b54d2016-03-02 18:38:40 +080021
22void bootblock_soc_init(void)
23{
Lin Huanga1f82a32016-03-09 18:08:20 +080024 rkclk_init();
Shunqian Zheng5dae9302016-04-13 22:43:35 +080025
26 /* all ddr range non-secure */
27 write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);
28
29 /* tzma_rosize = 0, all sram non-secure */
30 write32(&rk3399_pmusgrf->soc_con4, 0x3ff << 16 | 0);
31
32 /* emmc master secure */
33 write32(&rk3399_pmusgrf->soc_con7, 1 << 23 | 1 << 24 | 0 << 8 | 0 << 7);
34
35 /* glb_slv_secure_bypass */
36 write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1);
huang linc14b54d2016-03-02 18:38:40 +080037}