blob: 6310bac8a6c63f61db00e78f1fe2793ecbccf5c7 [file] [log] [blame]
Jonathan Zhang8f895492020-01-16 11:16:45 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2019 - 2020 Intel Corporation
5 * Copyright (C) 2019 - 2020 Facebook Inc
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <assert.h>
19#include <commonlib/sort.h>
20#include <console/console.h>
21#include <cpu/cpu.h>
22#include <cpu/x86/msr.h>
23#include <delay.h>
24#include <device/pci.h>
25#include <hob_iiouds.h>
26#include <intelblocks/cpulib.h>
27#include <intelblocks/pcr.h>
28#include <soc/iomap.h>
29#include <soc/cpu.h>
30#include <soc/msr.h>
31#include <soc/pci_devs.h>
32#include <soc/pcr_ids.h>
33#include <soc/soc_util.h>
34#include <stdlib.h>
35#include <timer.h>
36
37/*
38 * Get TOLM CSR B0:D5:F0:Offset_d0h
39 */
40uintptr_t get_tolm(uint32_t bus)
41{
42 uint32_t w = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC),
43 VTD_TOLM_CSR);
44 uintptr_t addr = w & 0xfc000000;
45 printk(BIOS_DEBUG, "VTD_TOLM_CSR 0x%x, addr: 0x%lx\n", w, addr);
46 return addr;
47}
48
49void get_tseg_base_lim(uint32_t bus, uint32_t *base, uint32_t *limit)
50{
51 uint32_t w1 = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC),
52 VTD_TSEG_BASE_CSR);
53 uint32_t wh = pci_io_read_config32(PCI_DEV(bus, VTD_DEV, VTD_FUNC),
54 VTD_TSEG_LIMIT_CSR);
55 *base = w1 & 0xfff00000;
56 *limit = wh & 0xfff00000;
57}
58
59/*
60 * Get MMCFG CSR B1:D29:F1:Offset_C0h
61 */
62uintptr_t get_cha_mmcfg_base(uint32_t bus)
63{
64 uint32_t wl = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV,
65 CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR);
66 uint32_t wh = pci_io_read_config32(PCI_DEV(bus, CHA_UTIL_ALL_DEV,
67 CHA_UTIL_ALL_FUNC), CHA_UTIL_ALL_MMCFG_CSR + 4);
68 uintptr_t addr = ((((wh & 0x3fff) << 6) | ((wl >> 26) & 0x3f)) << 26);
69 printk(BIOS_DEBUG, "CHA_UTIL_ALL_MMCFG_CSR wl: 0x%x, wh: 0x%x, addr: 0x%lx\n",
70 wl, wh, addr);
71 return addr;
72}
73
74/*
75 * Get Socket 0 CPUBUSNO(0), CPUBUSNO(1) PCI bus numbers UBOX (B0:D8:F2:Offset_CCh)
76 * TODO: D0h
77 */
78void get_cpubusnos(uint32_t *bus0, uint32_t *bus1, uint32_t *bus2, uint32_t *bus3)
79{
80 uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV,
81 UBOX_DECS_FUNC), UBOX_DECS_CPUBUSNO_CSR);
82 if (bus0)
83 *bus0 = (bus & 0xff);
84 if (bus1)
85 *bus1 = (bus >> 8) & 0xff;
86 if (bus2)
87 *bus2 = (bus >> 16) & 0xff;
88 if (bus3)
89 *bus3 = (bus >> 24) & 0xff;
90}
91
92uint32_t top_of_32bit_ram(void)
93{
94 uintptr_t mmcfg, tolm;
95 uint32_t bus0 = 0, bus1 = 0;
96 uint32_t base = 0, limit = 0;
97
98 get_cpubusnos(&bus0, &bus1, NULL, NULL);
99
100 mmcfg = get_cha_mmcfg_base(bus1);
101 tolm = get_tolm(bus0);
102 printk(BIOS_DEBUG, "bus0: 0x%x, bus1: 0x%x, mmcfg: 0x%lx, tolm: 0x%lx\n",
103 bus0, bus1, mmcfg, tolm);
104 get_tseg_base_lim(bus0, &base, &limit);
105 printk(BIOS_DEBUG, "tseg base: 0x%x, limit: 0x%x\n", base, limit);
106
107 /* We will use TSEG base as the top of DRAM */
108 return base;
109}
110
111/*
112 * +-------------------------+ TOLM
113 * | System Management Mode |
114 * | code and data |
115 * | (TSEG) |
116 * +-------------------------+ SMM base (aligned)
117 * | |
118 * | Chipset Reserved Memory |
119 * | |
120 * +-------------------------+ top_of_ram (aligned)
121 * | |
122 * | CBMEM Root |
123 * | |
124 * +-------------------------+
125 * | |
126 * | FSP Reserved Memory |
127 * | |
128 * +-------------------------+
129 * | |
130 * | Various CBMEM Entries |
131 * | |
132 * +-------------------------+ top_of_stack (8 byte aligned)
133 * | |
134 * | stack (CBMEM Entry) |
135 * | |
136 * +-------------------------+
137 */
138
139uint32_t pci_read_mmio_reg(int bus, uint32_t dev, uint32_t func, int offset)
140{
141 return pci_mmio_read_config32(PCI_DEV(bus, dev, func), offset);
142}
143
144uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack)
145{
146 size_t hob_size;
147 const IIO_UDS *hob;
148 const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
149
150 assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK);
151
152 hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size);
153 assert(hob != NULL && hob_size != 0);
154
155 return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack];
156}
157
158/* bus needs to be of size 6 (MAX_IIO_STACK) */
159void get_stack_busnos(uint32_t *bus)
160{
161 uint32_t reg1, reg2;
162
163 reg1 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
164 0xcc);
165 reg2 = pci_mmio_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC),
166 0xd0);
167
168 for (int i = 0; i < 4; ++i)
169 bus[i] = ((reg1 >> (i * 8)) & 0xff);
170 for (int i = 0; i < 2; ++i)
171 bus[4+i] = ((reg2 >> (i * 8)) & 0xff);
172}
173
174void unlock_pam_regions(void)
175{
176 uint32_t bus1 = 0;
177 uint32_t pam0123_unlock_dram = 0x33333330;
178 uint32_t pam456_unlock_dram = 0x00333333;
179
180 get_cpubusnos(NULL, &bus1, NULL, NULL);
181 pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
182 SAD_ALL_PAM0123_CSR, pam0123_unlock_dram);
183 pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC),
184 SAD_ALL_PAM456_CSR, pam456_unlock_dram);
185
186 uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
187 SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR);
188 uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV,
189 SAD_ALL_FUNC), SAD_ALL_PAM456_CSR);
190 printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n",
191 __FILE__, __func__, reg1, reg2);
192}
193
194/* return 1 if command timed out else 0 */
195static uint32_t wait_for_bios_cmd_cpl(pci_devfn_t dev, uint32_t reg, uint32_t mask,
196 uint32_t target)
197{
198 uint32_t max_delay = 5000; /* 5 seconds max */
199 uint32_t step_delay = 50; /* 50 us */
200 struct stopwatch sw;
201
202 stopwatch_init_msecs_expire(&sw, max_delay);
203 while ((pci_mmio_read_config32(dev, reg) & mask) != target) {
204 udelay(step_delay);
205 if (stopwatch_expired(&sw)) {
206 printk(BIOS_ERR, "%s timed out for dev: 0x%x, reg: 0x%x, "
207 "mask: 0x%x, target: 0x%x\n", __func__, dev, reg, mask, target);
208 return 1; /* timedout */
209 }
210 }
211 return 0; /* successful */
212}
213
214/* return 1 if command timed out else 0 */
215static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask,
216 uint32_t pcode_init_mask, uint32_t val)
217{
218 uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
219 pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
220
221 uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG);
222 reg &= (uint32_t) ~rst_cpl_mask;
223 reg |= rst_cpl_mask;
224 reg |= val;
225
226 /* update BIOS RESET completion bit */
227 pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg);
228
229 /* wait for PCU ack */
230 return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask,
231 pcode_init_mask);
232}
233
234/* return 1 if command timed out else 0 */
235static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data)
236{
237 /* verify bios is not in busy state */
238 if (wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG, BIOS_MB_RUN_BUSY_MASK, 0))
239 return 1; /* timed out */
240
241 /* write data to data register */
242 printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
243 PCU_CR1_BIOS_MB_DATA_REG, data);
244 pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_DATA_REG, data);
245
246 /* write the command */
247 printk(BIOS_SPEW, "%s - pci_mmio_write_config32 reg: 0x%x, data: 0x%x\n", __func__,
248 PCU_CR1_BIOS_MB_INTERFACE_REG,
249 (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK));
250 pci_mmio_write_config32(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
251 (uint32_t) (command | BIOS_MB_RUN_BUSY_MASK));
252
253 /* wait for completion or time out*/
254 return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_MB_INTERFACE_REG,
255 BIOS_MB_RUN_BUSY_MASK, 0);
256}
257
258void config_reset_cpl3_csrs(void)
259{
260 uint32_t data, plat_info, max_min_turbo_limit_ratio;
261
262 for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
263 uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
264
265 /* configure PCU_CR0_FUN csrs */
266 pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN);
267 data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS);
268 data |= P_STATE_LIMITS_LOCK;
269 pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data);
270
271 plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO);
272 dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO);
273 max_min_turbo_limit_ratio =
274 (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >>
275 MAX_NON_TURBO_LIM_RATIO_SHIFT;
276 printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n",
277 plat_info, max_min_turbo_limit_ratio);
278
279 /* configure PCU_CR1_FUN csrs */
280 pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
281
282 data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL);
283 /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */
284 data &= 0x0fffffff;
285 data |= SAPMCTL_LOCK_MASK;
286 pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data);
287
288 /* configure PCU_CR1_FUN csrs */
289 pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN);
290
291 data = PCIE_IN_PKGCSTATE_L1_MASK;
292 pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data);
293
294 data = KTI_IN_PKGCSTATE_L1_MASK;
295 pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data);
296
297 data = PROCHOT_RATIO;
298 printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data);
299 pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data);
300 dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG);
301
302 data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL);
303 data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT;
304 pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data);
305 }
306}
307
308static void set_bios_init_completion_for_package(uint32_t socket)
309{
310 uint32_t data;
311 uint32_t timedout;
312 uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK);
313 pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN);
314
315 /* read pcu config */
316 timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
317 if (timedout) {
318 /* 2nd try */
319 timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0);
320 if (timedout)
321 die("BIOS PCU Misc Config Read timed out.\n");
322
323 data = pci_mmio_read_config32(dev, PCU_CR1_BIOS_MB_DATA_REG);
324 printk(BIOS_SPEW, "%s - pci_mmio_read_config32 reg: 0x%x, data: 0x%x\n",
325 __func__, PCU_CR1_BIOS_MB_DATA_REG, data);
326
327 /* write PCU config */
328 timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_WRITE_PCU_MISC_CFG, data);
329 if (timedout)
330 die("BIOS PCU Misc Config Write timed out.\n");
331 }
332
333 /* update RST_CPL3, PCODE_INIT_DONE3 */
334 timedout = set_bios_reset_cpl_for_package(socket, RST_CPL3_MASK,
335 PCODE_INIT_DONE3_MASK, RST_CPL3_MASK);
336 if (timedout)
337 die("BIOS RESET CPL3 timed out.\n");
338
339 /* update RST_CPL4, PCODE_INIT_DONE4 */
340 timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK,
341 PCODE_INIT_DONE4_MASK, RST_CPL4_MASK);
342 if (timedout)
343 die("BIOS RESET CPL4 timed out.\n");
344 /* set CSR_DESIRED_CORES_CFG2 lock bit */
345 data = pci_mmio_read_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG);
346 data |= PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK;
347 printk(BIOS_SPEW, "%s - pci_mmio_write_config32 PCU_CR1_DESIRED_CORES_CFG2_REG 0x%x, data: 0x%x\n",
348 __func__, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
349 pci_mmio_write_config32(dev, PCU_CR1_DESIRED_CORES_CFG2_REG, data);
350}
351
352void set_bios_init_completion(void)
353{
354 uint32_t sbsp_socket_id = 0; /* TODO - this needs to be configurable */
355
356 for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) {
357 if (socket == sbsp_socket_id)
358 continue;
359 set_bios_init_completion_for_package(socket);
360 }
361 set_bios_init_completion_for_package(sbsp_socket_id);
362}
363
364void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits)
365{
366 register int ecx;
367 struct cpuid_result cpuid_regs;
368
369 /* get max index of CPUID */
370 cpuid_regs = cpuid(0);
371 assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */
372
373 *thread_bits = *core_bits = 0;
374 ecx = 0;
375 while (1) {
376 cpuid_regs = cpuid_ext(0xb, ecx);
377 if (ecx == 0) {
378 *thread_bits = (cpuid_regs.eax & 0x1f);
379 } else {
380 *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits;
381 break;
382 }
383 ecx++;
384 }
385}
386
387void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits,
388 uint8_t *package, uint8_t *core, uint8_t *thread)
389{
390 if (package != NULL)
391 *package = (apicid >> (thread_bits + core_bits));
392 if (core != NULL)
393 *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits));
394 if (thread != NULL)
395 *thread = (uint32_t)(apicid & ~((~0) << thread_bits));
396}
397
398int get_cpu_count(void)
399{
400 size_t hob_size;
401 const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
402 const IIO_UDS *hob;
403
404 /* these fields are incorrect - need debugging */
405 hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size);
406 assert(hob != NULL && hob_size != 0);
407 return hob->SystemStatus.numCpus;
408}
409
410int get_threads_per_package(void)
411{
412 unsigned int core_count, thread_count;
413 cpu_read_topology(&core_count, &thread_count);
414 return thread_count;
415}
416
417int get_platform_thread_count(void)
418{
419 return get_cpu_count() * get_threads_per_package();
420}
421
422void get_iiostack_info(struct iiostack_resource *info)
423{
424 size_t hob_size;
425 const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
426 const IIO_UDS *hob;
427
428 hob = fsp_find_extension_hob_by_guid(
429 fsp_hob_iio_universal_data_guid, &hob_size);
430 assert(hob != NULL && hob_size != 0);
431
432 // copy IIO Stack info from FSP HOB
433 info->no_of_stacks = 0;
434 for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
435 for (int x = 0; x < MAX_IIO_STACK; ++x) {
436 const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
437 // TODO: do we have situation with only bux 0 and one stack?
438 if (ri->BusBase >= ri->BusLimit)
439 continue;
440 assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK));
441 memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES));
442 }
443 }
444}
445
446#if ENV_RAMSTAGE
447
448void xeonsp_init_cpu_config(void)
449{
450 struct device *dev;
451 int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0};
452 int num_apics = 0;
453 uint32_t core_bits, thread_bits;
454 unsigned int core_count, thread_count;
455 unsigned int num_cpus;
456
457 /* sort APIC ids in asending order to identify apicid ranges for
458 each numa domain
459 */
460 for (dev = all_devices; dev; dev = dev->next) {
461 if ((dev->path.type != DEVICE_PATH_APIC) ||
462 (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
463 continue;
464 }
465 if (!dev->enabled)
466 continue;
467 if (num_apics >= ARRAY_SIZE(apic_ids))
468 break;
469 apic_ids[num_apics++] = dev->path.apic.apic_id;
470 }
471 if (num_apics > 1)
472 bubblesort(apic_ids, num_apics, NUM_ASCENDING);
473
474 num_cpus = get_cpu_count();
475 cpu_read_topology(&core_count, &thread_count);
476 assert(num_apics == (num_cpus * thread_count));
477
478 /* sort them by thread i.e., all cores with thread 0 and then thread 1 */
479 int index = 0;
480 for (int id = 0; id < num_apics; ++id) {
481 int apic_id = apic_ids[id];
482 if (apic_id & 0x1) { /* 2nd thread */
483 apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id;
484 } else { /* 1st thread */
485 apic_ids_by_thread[index++] = apic_id;
486 }
487 }
488
489
490 /* update apic_id, node_id in sorted order */
491 num_apics = 0;
492 get_core_thread_bits(&core_bits, &thread_bits);
493 for (dev = all_devices; dev; dev = dev->next) {
494 uint8_t package;
495
496 if ((dev->path.type != DEVICE_PATH_APIC) ||
497 (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
498 continue;
499 }
500 if (!dev->enabled)
501 continue;
502 if (num_apics >= ARRAY_SIZE(apic_ids))
503 break;
504 dev->path.apic.apic_id = apic_ids_by_thread[num_apics];
505 get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits,
506 &package, NULL, NULL);
507 dev->path.apic.node_id = package;
508 printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n",
509 num_apics, dev->path.apic.apic_id,
510 dev->path.apic.apic_id, dev->path.apic.node_id);
511
512 ++num_apics;
513 }
514}
515
516unsigned int get_srat_memory_entries(acpi_srat_mem_t *srat_mem)
517{
518 const struct SystemMemoryMapHob *memory_map;
519 size_t hob_size;
520 const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
521 unsigned int mmap_index;
522
523 memory_map = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size);
524 assert(memory_map != NULL && hob_size != 0);
525 printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size);
526
527 mmap_index = 0;
528 for (int e = 0; e < memory_map->numberEntries; ++e) {
529 const struct SystemMemoryMapElement *mem_element = &memory_map->Element[e];
530 uint64_t addr =
531 (uint64_t) ((uint64_t)mem_element->BaseAddress <<
532 MEM_ADDR_64MB_SHIFT_BITS);
533 uint64_t size =
534 (uint64_t) ((uint64_t)mem_element->ElementSize <<
535 MEM_ADDR_64MB_SHIFT_BITS);
536
537 printk(BIOS_DEBUG, "memory_map %d addr: 0x%llx, BaseAddress: 0x%x, size: 0x%llx, "
538 "ElementSize: 0x%x, reserved: %d\n",
539 e, addr, mem_element->BaseAddress, size,
540 mem_element->ElementSize, (mem_element->Type & MEM_TYPE_RESERVED));
541
542 assert(mmap_index < MAX_ACPI_MEMORY_AFFINITY_COUNT);
543
544 /* skip reserved memory region */
545 if (mem_element->Type & MEM_TYPE_RESERVED)
546 continue;
547
548 /* skip if this address is already added */
549 bool skip = false;
550 for (int idx = 0; idx < mmap_index; ++idx) {
551 uint64_t base_addr = ((uint64_t)srat_mem[idx].base_address_high << 32) +
552 srat_mem[idx].base_address_low;
553 if (addr == base_addr) {
554 skip = true;
555 break;
556 }
557 }
558 if (skip)
559 continue;
560
561 srat_mem[mmap_index].type = 1; /* Memory affinity structure */
562 srat_mem[mmap_index].length = sizeof(acpi_srat_mem_t);
563 srat_mem[mmap_index].base_address_low = (uint32_t) (addr & 0xffffffff);
564 srat_mem[mmap_index].base_address_high = (uint32_t) (addr >> 32);
565 srat_mem[mmap_index].length_low = (uint32_t) (size & 0xffffffff);
566 srat_mem[mmap_index].length_high = (uint32_t) (size >> 32);
567 srat_mem[mmap_index].proximity_domain = mem_element->SocketId;
568 srat_mem[mmap_index].flags = SRAT_ACPI_MEMORY_ENABLED;
569 if ((mem_element->Type & MEMTYPE_VOLATILE_MASK) == 0)
570 srat_mem[mmap_index].flags |= SRAT_ACPI_MEMORY_NONVOLATILE;
571 ++mmap_index;
572 }
573
574 return mmap_index;
575}
576
577#endif