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Jonathan Zhang8f895492020-01-16 11:16:45 -08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2019 - 2020 Intel Corporation
5 * Copyright (C) 2019 - 2020 Facebook Inc
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18
19#ifndef _SOC_CHIP_H_
20#define _SOC_CHIP_H_
21
22#include <stdint.h>
23#include <intelblocks/cfg.h>
24#include <soc/irq.h>
25
26struct soc_intel_xeon_sp_config {
27 /* Common struct containing soc config data required by common code */
28 struct soc_intel_common_config common_soc_config;
29
30 /**
31 * Interrupt Routing configuration
32 * If bit7 is 1, the interrupt is disabled.
33 */
34 uint8_t pirqa_routing;
35 uint8_t pirqb_routing;
36 uint8_t pirqc_routing;
37 uint8_t pirqd_routing;
38 uint8_t pirqe_routing;
39 uint8_t pirqf_routing;
40 uint8_t pirqg_routing;
41 uint8_t pirqh_routing;
42
43 /**
44 * Device Interrupt Routing configuration
45 * Interrupt Pin x Route.
46 * 0h = PIRQA#
47 * 1h = PIRQB#
48 * 2h = PIRQC#
49 * 3h = PIRQD#
50 * 4h = PIRQE#
51 * 5h = PIRQF#
52 * 6h = PIRQG#
53 * 7h = PIRQH#
54 */
55 uint16_t ir00_routing;
56 uint16_t ir01_routing;
57 uint16_t ir02_routing;
58 uint16_t ir03_routing;
59 uint16_t ir04_routing;
60
61 /**
62 * Device Interrupt Polarity Control
63 * ipc0 - IRQ-00-31 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
64 * ipc1 - IRQ-32-63 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
65 * ipc2 - IRQ-64-95 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
66 * ipc3 - IRQ-96-119 - 1: Active low to IOAPIC, 0: Active high to IOAPIC
67 */
68 uint32_t ipc0;
69 uint32_t ipc1;
70 uint32_t ipc2;
71 uint32_t ipc3;
72
73 uint64_t turbo_ratio_limit;
74 uint64_t turbo_ratio_limit_cores;
75
76 uint32_t pstate_req_ratio;
77
78 uint32_t vtd_support;
79 uint32_t coherency_support;
80 uint32_t ats_support;
81};
82
83extern struct chip_operations soc_intel_xeon_sp_ops;
84
85typedef struct soc_intel_xeon_sp_config config_t;
86
87#endif