blob: c745b8cc0968308931eb61fcdfc76d39dbd8e603 [file] [log] [blame]
Lee Leahyeef40eb2017-03-23 10:54:57 -07001/*
Martin Roth0443ac22019-08-30 21:29:41 -06002 * This file is part of the coreboot project.
Lee Leahyeef40eb2017-03-23 10:54:57 -07003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
Lee Leahy48dbc662017-05-08 16:56:03 -070014#ifndef __COMMONLIB_STORAGE_SDHCI_H__
15#define __COMMONLIB_STORAGE_SDHCI_H__
Lee Leahyeef40eb2017-03-23 10:54:57 -070016
Kyösti Mälkki13f66502019-03-03 08:01:05 +020017#include <device/mmio.h>
Lee Leahy48dbc662017-05-08 16:56:03 -070018#include <commonlib/sd_mmc_ctrlr.h>
Lee Leahyeef40eb2017-03-23 10:54:57 -070019
20/*
21 * Controller registers
22 */
23
24#define SDHCI_DMA_ADDRESS 0x00
25
26#define SDHCI_BLOCK_SIZE 0x04
27#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
28
29#define SDHCI_BLOCK_COUNT 0x06
30
31#define SDHCI_ARGUMENT 0x08
32
33#define SDHCI_TRANSFER_MODE 0x0C
34#define SDHCI_TRNS_DMA 0x01
35#define SDHCI_TRNS_BLK_CNT_EN 0x02
36#define SDHCI_TRNS_ACMD12 0x04
37#define SDHCI_TRNS_READ 0x10
38#define SDHCI_TRNS_MULTI 0x20
39
40#define SDHCI_COMMAND 0x0E
41#define SDHCI_CMD_RESP_MASK 0x03
42#define SDHCI_CMD_CRC 0x08
43#define SDHCI_CMD_INDEX 0x10
44#define SDHCI_CMD_DATA 0x20
45#define SDHCI_CMD_ABORTCMD 0xC0
46
47#define SDHCI_CMD_RESP_NONE 0x00
48#define SDHCI_CMD_RESP_LONG 0x01
49#define SDHCI_CMD_RESP_SHORT 0x02
50#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
51
52#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
53#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
54
55#define SDHCI_RESPONSE 0x10
56
57#define SDHCI_BUFFER 0x20
58
59#define SDHCI_PRESENT_STATE 0x24
60#define SDHCI_CMD_INHIBIT 0x00000001
61#define SDHCI_DATA_INHIBIT 0x00000002
62#define SDHCI_DOING_WRITE 0x00000100
63#define SDHCI_DOING_READ 0x00000200
64#define SDHCI_SPACE_AVAILABLE 0x00000400
65#define SDHCI_DATA_AVAILABLE 0x00000800
66#define SDHCI_CARD_PRESENT 0x00010000
67#define SDHCI_CARD_STATE_STABLE 0x00020000
68#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
69#define SDHCI_WRITE_PROTECT 0x00080000
70
71#define SDHCI_HOST_CONTROL 0x28
72#define SDHCI_CTRL_LED 0x01
73#define SDHCI_CTRL_4BITBUS 0x02
74#define SDHCI_CTRL_HISPD 0x04
75#define SDHCI_CTRL_DMA_MASK 0x18
76#define SDHCI_CTRL_SDMA 0x00
77#define SDHCI_CTRL_ADMA1 0x08
78#define SDHCI_CTRL_ADMA32 0x10
79#define SDHCI_CTRL_ADMA64 0x18
80#define SDHCI_CTRL_8BITBUS 0x20
81#define SDHCI_CTRL_CD_TEST_INS 0x40
82#define SDHCI_CTRL_CD_TEST 0x80
83
84#define SDHCI_POWER_CONTROL 0x29
85#define SDHCI_POWER_ON 0x01
86#define SDHCI_POWER_180 0x0A
87#define SDHCI_POWER_300 0x0C
88#define SDHCI_POWER_330 0x0E
89
90#define SDHCI_BLOCK_GAP_CONTROL 0x2A
91
92#define SDHCI_WAKE_UP_CONTROL 0x2B
93#define SDHCI_WAKE_ON_INT 0x01
94#define SDHCI_WAKE_ON_INSERT 0x02
95#define SDHCI_WAKE_ON_REMOVE 0x04
96
97#define SDHCI_CLOCK_CONTROL 0x2C
98#define SDHCI_DIVIDER_SHIFT 8
99#define SDHCI_DIVIDER_HI_SHIFT 6
100#define SDHCI_DIV_MASK 0xFF
101#define SDHCI_DIV_MASK_LEN 8
102#define SDHCI_DIV_HI_MASK 0x300
103#define SDHCI_CLOCK_CARD_EN 0x0004
104#define SDHCI_CLOCK_INT_STABLE 0x0002
105#define SDHCI_CLOCK_INT_EN 0x0001
106
107#define SDHCI_TIMEOUT_CONTROL 0x2E
108
109#define SDHCI_SOFTWARE_RESET 0x2F
110#define SDHCI_RESET_ALL 0x01
111#define SDHCI_RESET_CMD 0x02
112#define SDHCI_RESET_DATA 0x04
113
114#define SDHCI_INT_STATUS 0x30
115#define SDHCI_INT_ENABLE 0x34
116#define SDHCI_SIGNAL_ENABLE 0x38
117#define SDHCI_INT_RESPONSE 0x00000001
118#define SDHCI_INT_DATA_END 0x00000002
119#define SDHCI_INT_DMA_END 0x00000008
120#define SDHCI_INT_SPACE_AVAIL 0x00000010
121#define SDHCI_INT_DATA_AVAIL 0x00000020
122#define SDHCI_INT_CARD_INSERT 0x00000040
123#define SDHCI_INT_CARD_REMOVE 0x00000080
124#define SDHCI_INT_CARD_INT 0x00000100
125#define SDHCI_INT_ERROR 0x00008000
126#define SDHCI_INT_TIMEOUT 0x00010000
127#define SDHCI_INT_CRC 0x00020000
128#define SDHCI_INT_END_BIT 0x00040000
129#define SDHCI_INT_INDEX 0x00080000
130#define SDHCI_INT_DATA_TIMEOUT 0x00100000
131#define SDHCI_INT_DATA_CRC 0x00200000
132#define SDHCI_INT_DATA_END_BIT 0x00400000
133#define SDHCI_INT_BUS_POWER 0x00800000
134#define SDHCI_INT_ACMD12ERR 0x01000000
135#define SDHCI_INT_ADMA_ERROR 0x02000000
136
137#define SDHCI_INT_NORMAL_MASK 0x00007FFF
138#define SDHCI_INT_ERROR_MASK 0xFFFF8000
139
140#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT \
141 | SDHCI_INT_CRC | SDHCI_INT_END_BIT \
142 | SDHCI_INT_INDEX)
143#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END \
144 | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL \
145 | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC \
146 | SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
147#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
148
149#define SDHCI_ACMD12_ERR 0x3C
150
151#define SDHCI_HOST_CONTROL2 0x3E
152#define SDHCI_CTRL_UHS_MASK 0x0007
153#define SDHCI_CTRL_UHS_SDR12 0x0000
154#define SDHCI_CTRL_UHS_SDR25 0x0001
155#define SDHCI_CTRL_UHS_SDR50 0x0002
156#define SDHCI_CTRL_UHS_SDR104 0x0003
157#define SDHCI_CTRL_UHS_DDR50 0x0004
158#define SDHCI_CTRL_HS400 0x0005 /* reserved value in SDIO spec */
159#define SDHCI_CTRL_VDD_180 0x0008
160#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
161#define SDHCI_CTRL_DRV_TYPE_B 0x0000
162#define SDHCI_CTRL_DRV_TYPE_A 0x0010
163#define SDHCI_CTRL_DRV_TYPE_C 0x0020
164#define SDHCI_CTRL_DRV_TYPE_D 0x0030
165#define SDHCI_CTRL_EXEC_TUNING 0x0040
166#define SDHCI_CTRL_TUNED_CLK 0x0080
167#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
168
169#define SDHCI_CAPABILITIES 0x40
170#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
171#define SDHCI_TIMEOUT_CLK_SHIFT 0
172#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
173#define SDHCI_CLOCK_BASE_MASK 0x00003F00
174#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
175#define SDHCI_CLOCK_BASE_SHIFT 8
176#define SDHCI_MAX_BLOCK_MASK 0x00030000
177#define SDHCI_MAX_BLOCK_SHIFT 16
178#define SDHCI_CAN_DO_8BIT 0x00040000
179#define SDHCI_CAN_DO_ADMA2 0x00080000
180#define SDHCI_CAN_DO_ADMA1 0x00100000
181#define SDHCI_CAN_DO_HISPD 0x00200000
182#define SDHCI_CAN_DO_SDMA 0x00400000
183#define SDHCI_CAN_VDD_330 0x01000000
184#define SDHCI_CAN_VDD_300 0x02000000
185#define SDHCI_CAN_VDD_180 0x04000000
186#define SDHCI_CAN_64BIT 0x10000000
187
188#define SDHCI_CAPABILITIES_1 0x44
189#define SDHCI_SUPPORT_HS400 0x80000000
190
191#define SDHCI_MAX_CURRENT 0x48
192
193/* 4C-4F reserved for more max current */
194
195#define SDHCI_SET_ACMD12_ERROR 0x50
196#define SDHCI_SET_INT_ERROR 0x52
197
198#define SDHCI_ADMA_ERROR 0x54
199
200/* 55-57 reserved */
201
202#define SDHCI_ADMA_ADDRESS 0x58
203
204/* 60-FB reserved */
205
206#define SDHCI_SLOT_INT_STATUS 0xFC
207
208#define SDHCI_HOST_VERSION 0xFE
209#define SDHCI_VENDOR_VER_MASK 0xFF00
210#define SDHCI_VENDOR_VER_SHIFT 8
211#define SDHCI_SPEC_VER_MASK 0x00FF
212#define SDHCI_SPEC_VER_SHIFT 0
213#define SDHCI_SPEC_100 0
214#define SDHCI_SPEC_200 1
215#define SDHCI_SPEC_300 2
216
217/*
218 * End of controller registers.
219 */
220
221#define SDHCI_MAX_DIV_SPEC_200 256
222#define SDHCI_MAX_DIV_SPEC_300 2046
223
224/*
225 * Controller SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
226 */
227#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
228#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
229
230#define SDHCI_MAX_PER_DESCRIPTOR 0x10000
231
232/* ADMA descriptor attributes */
233#define SDHCI_ADMA_VALID (1 << 0)
234#define SDHCI_ADMA_END (1 << 1)
235#define SDHCI_ADMA_INT (1 << 2)
236#define SDHCI_ACT_NOP (0 << 4)
237#define SDHCI_ACT_TRAN (2 << 4)
238#define SDHCI_ACT_LINK (3 << 4)
239
240static inline void sdhci_writel(struct sdhci_ctrlr *sdhci_ctrlr, u32 val,
241 int reg)
242{
243 write32(sdhci_ctrlr->ioaddr + reg, val);
244}
245
246static inline void sdhci_writew(struct sdhci_ctrlr *sdhci_ctrlr, u16 val,
247 int reg)
248{
249 write16(sdhci_ctrlr->ioaddr + reg, val);
250}
251
252static inline void sdhci_writeb(struct sdhci_ctrlr *sdhci_ctrlr, u8 val,
253 int reg)
254{
255 write8(sdhci_ctrlr->ioaddr + reg, val);
256}
257static inline u32 sdhci_readl(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
258{
259 return read32(sdhci_ctrlr->ioaddr + reg);
260}
261
262static inline u16 sdhci_readw(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
263{
264 return read16(sdhci_ctrlr->ioaddr + reg);
265}
266
267static inline u8 sdhci_readb(struct sdhci_ctrlr *sdhci_ctrlr, int reg)
268{
269 return read8(sdhci_ctrlr->ioaddr + reg);
270}
271
272void sdhci_reset(struct sdhci_ctrlr *sdhci_ctrlr, u8 mask);
273void sdhci_cmd_done(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_command *cmd);
274int sdhci_setup_adma(struct sdhci_ctrlr *sdhci_ctrlr, struct mmc_data *data);
275int sdhci_complete_adma(struct sdhci_ctrlr *sdhci_ctrlr,
276 struct mmc_command *cmd);
277
Lee Leahy48dbc662017-05-08 16:56:03 -0700278#endif /* __COMMONLIB_STORAGE_SDHCI_H__ */