Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc. |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 5 | * Copyright (C) 2012 ChromeOS Authors |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #define __SIMPLE_DEVICE__ |
| 18 | |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 20 | #include <arch/io.h> |
| 21 | #include <cbmem.h> |
Kyösti Mälkki | 140087f | 2016-12-06 14:00:05 +0200 | [diff] [blame] | 22 | #include <cpu/cpu.h> |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 23 | #include <cpu/intel/romstage.h> |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 24 | #include <cpu/x86/mtrr.h> |
| 25 | #include <program_loading.h> |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 26 | #include "sandybridge.h" |
| 27 | |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 28 | #if (CONFIG_SMM_TSEG_SIZE < 0x800000) |
| 29 | # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" |
| 30 | #endif |
| 31 | #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) |
| 32 | # error "CONFIG_SMM_TSEG_SIZE is not a power of 2" |
| 33 | #endif |
| 34 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 35 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 36 | { |
| 37 | /* Base of TSEG is top of usable DRAM */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 38 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 39 | return tom; |
| 40 | } |
| 41 | |
| 42 | void *cbmem_top(void) |
| 43 | { |
| 44 | return (void *) smm_region_start(); |
Kyösti Mälkki | cb08e16 | 2013-10-15 17:19:41 +0300 | [diff] [blame] | 45 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 46 | |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 47 | static inline u32 *stack_push(u32 *stack, u32 value) |
| 48 | { |
| 49 | stack = &stack[-1]; |
| 50 | *stack = value; |
| 51 | return stack; |
| 52 | } |
| 53 | |
| 54 | /* setup_stack_and_mtrrs() determines the stack to use after |
| 55 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 56 | void *setup_stack_and_mtrrs(void) |
| 57 | { |
Kyösti Mälkki | bfca670 | 2016-07-22 22:48:35 +0300 | [diff] [blame] | 58 | int num_mtrrs; |
| 59 | u32 *slot; |
| 60 | u32 mtrr_mask_upper; |
| 61 | u32 top_of_ram; |
| 62 | |
| 63 | /* Top of stack needs to be aligned to a 4-byte boundary. */ |
| 64 | slot = (void *)romstage_ram_stack_top(); |
| 65 | num_mtrrs = 0; |
| 66 | |
| 67 | /* The upper bits of the MTRR mask need to set according to the number |
| 68 | * of physical address bits. */ |
| 69 | mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1; |
| 70 | |
| 71 | /* The order for each MTRR is value then base with upper 32-bits of |
| 72 | * each value coming before the lower 32-bits. The reasoning for |
| 73 | * this ordering is to create a stack layout like the following: |
| 74 | * +0: Number of MTRRs |
| 75 | * +4: MTRR base 0 31:0 |
| 76 | * +8: MTRR base 0 63:32 |
| 77 | * +12: MTRR mask 0 31:0 |
| 78 | * +16: MTRR mask 0 63:32 |
| 79 | * +20: MTRR base 1 31:0 |
| 80 | * +24: MTRR base 1 63:32 |
| 81 | * +28: MTRR mask 1 31:0 |
| 82 | * +32: MTRR mask 1 63:32 |
| 83 | */ |
| 84 | |
| 85 | /* Cache the ROM as WP just below 4GiB. */ |
| 86 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 87 | slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); |
| 88 | slot = stack_push(slot, 0); /* upper base */ |
| 89 | slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); |
| 90 | num_mtrrs++; |
| 91 | |
| 92 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 93 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 94 | slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); |
| 95 | slot = stack_push(slot, 0); /* upper base */ |
| 96 | slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); |
| 97 | num_mtrrs++; |
| 98 | |
| 99 | top_of_ram = (uint32_t)cbmem_top(); |
| 100 | /* Cache 8MiB below the top of ram. On sandybridge systems the top of |
| 101 | * ram under 4GiB is the start of the TSEG region. It is required to |
| 102 | * be 8MiB aligned. Set this area as cacheable so it can be used later |
| 103 | * for ramstage before setting up the entire RAM as cacheable. */ |
| 104 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 105 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); |
| 106 | slot = stack_push(slot, 0); /* upper base */ |
| 107 | slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); |
| 108 | num_mtrrs++; |
| 109 | |
| 110 | /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems |
| 111 | * is where the TSEG region resides. However, it is not restricted |
| 112 | * to SMM mode until SMM has been relocated. By setting the region |
| 113 | * to cacheable it provides faster access when relocating the SMM |
| 114 | * handler as well as using the TSEG region for other purposes. */ |
| 115 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 116 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); |
| 117 | slot = stack_push(slot, 0); /* upper base */ |
| 118 | slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); |
| 119 | num_mtrrs++; |
| 120 | |
| 121 | /* Save the number of MTRRs to setup. Return the stack location |
| 122 | * pointing to the number of MTRRs. */ |
| 123 | slot = stack_push(slot, num_mtrrs); |
| 124 | |
| 125 | return slot; |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 126 | } |