Angel Pons | fabfe9d | 2020-04-05 15:47:07 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | #include <arch/cpu.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <console/console.h> |
| 6 | #include <cpu/x86/msr.h> |
Usha P | a5f9a4a | 2020-07-15 14:25:14 +0530 | [diff] [blame] | 7 | #include <cpu/x86/name.h> |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 8 | #include <device/pci.h> |
| 9 | #include <device/pci_ids.h> |
| 10 | #include <intelblocks/mp_init.h> |
| 11 | #include <soc/bootblock.h> |
| 12 | #include <soc/pch.h> |
| 13 | #include <soc/pci_devs.h> |
| 14 | #include <string.h> |
| 15 | |
| 16 | #define BIOS_SIGN_ID 0x8B |
| 17 | |
| 18 | static struct { |
| 19 | u32 cpuid; |
| 20 | const char *name; |
| 21 | } cpu_table[] = { |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 22 | { CPUID_JASPERLAKE_A0, "Jasperlake A0" }, |
| 23 | }; |
| 24 | |
| 25 | static struct { |
| 26 | u16 mchid; |
| 27 | const char *name; |
| 28 | } mch_table[] = { |
Maulik V Vaghela | 8745a27 | 2020-04-22 12:13:40 +0530 | [diff] [blame] | 29 | { PCI_DEVICE_ID_INTEL_JSL_ID_1, "Jasperlake SKU4-1" }, |
| 30 | { PCI_DEVICE_ID_INTEL_JSL_ID_2, "Jasperlake SKU4-2" }, |
| 31 | { PCI_DEVICE_ID_INTEL_JSL_ID_3, "Jasperlake SKU2-1" }, |
| 32 | { PCI_DEVICE_ID_INTEL_JSL_ID_4, "Jasperlake SKU2-2" }, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 33 | }; |
| 34 | |
| 35 | static struct { |
| 36 | u16 espiid; |
| 37 | const char *name; |
| 38 | } pch_table[] = { |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 39 | { PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI, "Jasperlake Super" }, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | static struct { |
| 43 | u16 igdid; |
| 44 | const char *name; |
| 45 | } igd_table[] = { |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 46 | { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, |
| 47 | { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 48 | }; |
| 49 | |
| 50 | static inline uint8_t get_dev_revision(pci_devfn_t dev) |
| 51 | { |
| 52 | return pci_read_config8(dev, PCI_REVISION_ID); |
| 53 | } |
| 54 | |
| 55 | static inline uint16_t get_dev_id(pci_devfn_t dev) |
| 56 | { |
| 57 | return pci_read_config16(dev, PCI_DEVICE_ID); |
| 58 | } |
| 59 | |
| 60 | static void report_cpu_info(void) |
| 61 | { |
Usha P | a5f9a4a | 2020-07-15 14:25:14 +0530 | [diff] [blame] | 62 | u32 i, cpu_id, cpu_feature_flag; |
| 63 | char cpu_name[49]; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 64 | int vt, txt, aes; |
| 65 | msr_t microcode_ver; |
| 66 | static const char *const mode[] = {"NOT ", ""}; |
| 67 | const char *cpu_type = "Unknown"; |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 68 | |
Usha P | a5f9a4a | 2020-07-15 14:25:14 +0530 | [diff] [blame] | 69 | fill_processor_name(cpu_name); |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 70 | |
| 71 | microcode_ver.lo = 0; |
| 72 | microcode_ver.hi = 0; |
| 73 | wrmsr(BIOS_SIGN_ID, microcode_ver); |
| 74 | cpu_id = cpu_get_cpuid(); |
| 75 | microcode_ver = rdmsr(BIOS_SIGN_ID); |
| 76 | |
| 77 | /* Look for string to match the name */ |
| 78 | for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { |
| 79 | if (cpu_table[i].cpuid == cpu_id) { |
| 80 | cpu_type = cpu_table[i].name; |
| 81 | break; |
| 82 | } |
| 83 | } |
| 84 | |
| 85 | printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); |
| 86 | printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", |
| 87 | cpu_id, cpu_type, microcode_ver.hi); |
| 88 | |
| 89 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 90 | aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; |
| 91 | txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; |
| 92 | vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; |
| 93 | printk(BIOS_DEBUG, |
| 94 | "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", |
| 95 | mode[aes], mode[txt], mode[vt]); |
| 96 | } |
| 97 | |
| 98 | static void report_mch_info(void) |
| 99 | { |
| 100 | int i; |
| 101 | pci_devfn_t dev = SA_DEV_ROOT; |
| 102 | uint16_t mchid = get_dev_id(dev); |
| 103 | uint8_t mch_revision = get_dev_revision(dev); |
| 104 | const char *mch_type = "Unknown"; |
| 105 | |
| 106 | for (i = 0; i < ARRAY_SIZE(mch_table); i++) { |
| 107 | if (mch_table[i].mchid == mchid) { |
| 108 | mch_type = mch_table[i].name; |
| 109 | break; |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", |
| 114 | mchid, mch_revision, mch_type); |
| 115 | } |
| 116 | |
| 117 | static void report_pch_info(void) |
| 118 | { |
| 119 | int i; |
| 120 | pci_devfn_t dev = PCH_DEV_ESPI; |
| 121 | uint16_t espiid = get_dev_id(dev); |
| 122 | const char *pch_type = "Unknown"; |
| 123 | |
| 124 | for (i = 0; i < ARRAY_SIZE(pch_table); i++) { |
| 125 | if (pch_table[i].espiid == espiid) { |
| 126 | pch_type = pch_table[i].name; |
| 127 | break; |
| 128 | } |
| 129 | } |
| 130 | printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", |
| 131 | espiid, get_dev_revision(dev), pch_type); |
| 132 | } |
| 133 | |
| 134 | static void report_igd_info(void) |
| 135 | { |
| 136 | int i; |
| 137 | pci_devfn_t dev = SA_DEV_IGD; |
| 138 | uint16_t igdid = get_dev_id(dev); |
| 139 | const char *igd_type = "Unknown"; |
| 140 | |
| 141 | for (i = 0; i < ARRAY_SIZE(igd_table); i++) { |
| 142 | if (igd_table[i].igdid == igdid) { |
| 143 | igd_type = igd_table[i].name; |
| 144 | break; |
| 145 | } |
| 146 | } |
| 147 | printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", |
| 148 | igdid, get_dev_revision(dev), igd_type); |
| 149 | } |
| 150 | |
| 151 | void report_platform_info(void) |
| 152 | { |
| 153 | report_cpu_info(); |
| 154 | report_mch_info(); |
| 155 | report_pch_info(); |
| 156 | report_igd_info(); |
| 157 | } |