Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 1 | // See LICENSE for license details. |
| 2 | |
| 3 | #ifndef RISCV_CSR_ENCODING_H |
| 4 | #define RISCV_CSR_ENCODING_H |
| 5 | |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 6 | #define MSTATUS_IE 0x00000001 |
| 7 | #define MSTATUS_PRV 0x00000006 |
| 8 | #define MSTATUS_IE1 0x00000008 |
| 9 | #define MSTATUS_PRV1 0x00000030 |
| 10 | #define MSTATUS_IE2 0x00000040 |
| 11 | #define MSTATUS_PRV2 0x00000180 |
| 12 | #define MSTATUS_IE3 0x00000200 |
| 13 | #define MSTATUS_PRV3 0x00000C00 |
| 14 | #define MSTATUS_FS 0x00003000 |
| 15 | #define MSTATUS_XS 0x0000C000 |
| 16 | #define MSTATUS_MPRV 0x00010000 |
| 17 | #define MSTATUS_VM 0x003E0000 |
| 18 | #define MSTATUS32_SD 0x80000000 |
| 19 | #define MSTATUS64_SD 0x8000000000000000 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 20 | |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 21 | #define SSTATUS_IE 0x00000001 |
| 22 | #define SSTATUS_PIE 0x00000008 |
| 23 | #define SSTATUS_PS 0x00000010 |
| 24 | #define SSTATUS_FS 0x00003000 |
| 25 | #define SSTATUS_XS 0x0000C000 |
| 26 | #define SSTATUS_MPRV 0x00010000 |
| 27 | #define SSTATUS_TIE 0x01000000 |
| 28 | #define SSTATUS32_SD 0x80000000 |
| 29 | #define SSTATUS64_SD 0x8000000000000000 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 30 | |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 31 | #define MIP_SSIP 0x00000002 |
| 32 | #define MIP_HSIP 0x00000004 |
| 33 | #define MIP_MSIP 0x00000008 |
| 34 | #define MIP_STIP 0x00000020 |
| 35 | #define MIP_HTIP 0x00000040 |
| 36 | #define MIP_MTIP 0x00000080 |
| 37 | |
| 38 | #define SIP_SSIP MIP_SSIP |
| 39 | #define SIP_STIP MIP_STIP |
| 40 | |
| 41 | #define PRV_U 0 |
| 42 | #define PRV_S 1 |
| 43 | #define PRV_H 2 |
| 44 | #define PRV_M 3 |
| 45 | |
| 46 | #define VM_MBARE 0 |
| 47 | #define VM_MBB 1 |
| 48 | #define VM_MBBID 2 |
| 49 | #define VM_SV32 8 |
| 50 | #define VM_SV39 9 |
| 51 | #define VM_SV48 10 |
| 52 | |
| 53 | #define UA_RV32 0 |
| 54 | #define UA_RV64 4 |
| 55 | #define UA_RV128 8 |
| 56 | |
| 57 | #define IRQ_SOFT 0 |
| 58 | #define IRQ_TIMER 1 |
| 59 | #define IRQ_HOST 2 |
| 60 | #define IRQ_COP 3 |
| 61 | |
| 62 | #define IMPL_ROCKET 1 |
| 63 | |
| 64 | #define DEFAULT_MTVEC 0x100 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 65 | |
| 66 | // page table entry (PTE) fields |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 67 | #define PTE_V 0x001 // Valid |
| 68 | #define PTE_TYPE 0x01E // Type |
| 69 | #define PTE_R 0x020 // Referenced |
| 70 | #define PTE_D 0x040 // Dirty |
| 71 | #define PTE_SOFT 0x380 // Reserved for Software |
| 72 | |
| 73 | #define PTE_TYPE_TABLE 0x00 |
| 74 | #define PTE_TYPE_TABLE_GLOBAL 0x02 |
| 75 | #define PTE_TYPE_URX_SR 0x04 |
| 76 | #define PTE_TYPE_URWX_SRW 0x06 |
| 77 | #define PTE_TYPE_UR_SR 0x08 |
| 78 | #define PTE_TYPE_URW_SRW 0x0A |
| 79 | #define PTE_TYPE_URX_SRX 0x0C |
| 80 | #define PTE_TYPE_URWX_SRWX 0x0E |
| 81 | #define PTE_TYPE_SR 0x10 |
| 82 | #define PTE_TYPE_SRW 0x12 |
| 83 | #define PTE_TYPE_SRX 0x14 |
| 84 | #define PTE_TYPE_SRWX 0x16 |
| 85 | #define PTE_TYPE_SR_GLOBAL 0x18 |
| 86 | #define PTE_TYPE_SRW_GLOBAL 0x1A |
| 87 | #define PTE_TYPE_SRX_GLOBAL 0x1C |
| 88 | #define PTE_TYPE_SRWX_GLOBAL 0x1E |
| 89 | |
| 90 | #define PTE_PPN_SHIFT 10 |
| 91 | |
| 92 | #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) |
| 93 | #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) |
| 94 | #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) |
| 95 | #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) |
| 96 | #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) |
| 97 | #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) |
| 98 | #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) |
| 99 | |
| 100 | #define PTE_CHECK_PERM(PTE, SUPERVISOR, STORE, FETCH) \ |
| 101 | ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ |
| 102 | (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ |
| 103 | ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 104 | |
| 105 | #ifdef __riscv |
| 106 | |
| 107 | #ifdef __riscv64 |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 108 | # define MSTATUS_SD MSTATUS64_SD |
| 109 | # define SSTATUS_SD SSTATUS64_SD |
| 110 | # define RISCV_PGLEVEL_BITS 9 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 111 | #else |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 112 | # define MSTATUS_SD MSTATUS32_SD |
| 113 | # define SSTATUS_SD SSTATUS32_SD |
| 114 | # define RISCV_PGLEVEL_BITS 10 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 115 | #endif |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 116 | #define RISCV_PGSHIFT 12 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 117 | #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) |
| 118 | |
| 119 | #ifndef __ASSEMBLER__ |
| 120 | |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 121 | #ifdef __GNUC__ |
| 122 | |
| 123 | #if __GNUC__ < 5 |
| 124 | // stubbed out until we're safely on gcc-5.1+ with the new ABI |
| 125 | #define read_csr(reg) ({ 0; }) |
| 126 | #define write_csr(reg, val) |
| 127 | #define swap_csr(reg, val) ({ val; }) |
| 128 | #define set_csr(reg, bit) ({ bit; }) |
| 129 | #define clear_csr(reg, bit) ({ bit; }) |
| 130 | #else |
| 131 | #define read_csr(reg) ({ unsigned long __tmp; \ |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 132 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ |
| 133 | __tmp; }) |
| 134 | |
| 135 | #define write_csr(reg, val) \ |
| 136 | asm volatile ("csrw " #reg ", %0" :: "r"(val)) |
| 137 | |
| 138 | #define swap_csr(reg, val) ({ long __tmp; \ |
| 139 | asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ |
| 140 | __tmp; }) |
| 141 | |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 142 | #define set_csr(reg, bit) ({ unsigned long __tmp; \ |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 143 | if (__builtin_constant_p(bit) && (bit) < 32) \ |
| 144 | asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ |
| 145 | else \ |
| 146 | asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ |
| 147 | __tmp; }) |
| 148 | |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 149 | #define clear_csr(reg, bit) ({ unsigned long __tmp; \ |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 150 | if (__builtin_constant_p(bit) && (bit) < 32) \ |
| 151 | asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ |
| 152 | else \ |
| 153 | asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ |
| 154 | __tmp; }) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 155 | #endif |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 156 | |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 157 | #define rdtime() read_csr(time) |
| 158 | #define rdcycle() read_csr(cycle) |
| 159 | #define rdinstret() read_csr(instret) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 160 | |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 161 | #endif |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 162 | |
| 163 | #endif |
| 164 | |
| 165 | #endif |
| 166 | |
| 167 | #endif |
| 168 | /* Automatically generated by parse-opcodes */ |
| 169 | #ifndef RISCV_ENCODING_H |
| 170 | #define RISCV_ENCODING_H |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 171 | #define MATCH_ADD 0x33 |
| 172 | #define MASK_ADD 0xfe00707f |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 173 | #define MATCH_ADDI 0x13 |
| 174 | #define MASK_ADDI 0x707f |
| 175 | #define MATCH_ADDIW 0x1b |
| 176 | #define MASK_ADDIW 0x707f |
| 177 | #define MATCH_ADDW 0x3b |
| 178 | #define MASK_ADDW 0xfe00707f |
| 179 | #define MATCH_AMOADD_D 0x302f |
| 180 | #define MASK_AMOADD_D 0xf800707f |
| 181 | #define MATCH_AMOADD_W 0x202f |
| 182 | #define MASK_AMOADD_W 0xf800707f |
| 183 | #define MATCH_AMOAND_D 0x6000302f |
| 184 | #define MASK_AMOAND_D 0xf800707f |
| 185 | #define MATCH_AMOAND_W 0x6000202f |
| 186 | #define MASK_AMOAND_W 0xf800707f |
| 187 | #define MATCH_AMOMAX_D 0xa000302f |
| 188 | #define MASK_AMOMAX_D 0xf800707f |
| 189 | #define MATCH_AMOMAX_W 0xa000202f |
| 190 | #define MASK_AMOMAX_W 0xf800707f |
| 191 | #define MATCH_AMOMAXU_D 0xe000302f |
| 192 | #define MASK_AMOMAXU_D 0xf800707f |
| 193 | #define MATCH_AMOMAXU_W 0xe000202f |
| 194 | #define MASK_AMOMAXU_W 0xf800707f |
| 195 | #define MATCH_AMOMIN_D 0x8000302f |
| 196 | #define MASK_AMOMIN_D 0xf800707f |
| 197 | #define MATCH_AMOMIN_W 0x8000202f |
| 198 | #define MASK_AMOMIN_W 0xf800707f |
| 199 | #define MATCH_AMOMINU_D 0xc000302f |
| 200 | #define MASK_AMOMINU_D 0xf800707f |
| 201 | #define MATCH_AMOMINU_W 0xc000202f |
| 202 | #define MASK_AMOMINU_W 0xf800707f |
| 203 | #define MATCH_AMOOR_D 0x4000302f |
| 204 | #define MASK_AMOOR_D 0xf800707f |
| 205 | #define MATCH_AMOOR_W 0x4000202f |
| 206 | #define MASK_AMOOR_W 0xf800707f |
| 207 | #define MATCH_AMOSWAP_D 0x800302f |
| 208 | #define MASK_AMOSWAP_D 0xf800707f |
| 209 | #define MATCH_AMOSWAP_W 0x800202f |
| 210 | #define MASK_AMOSWAP_W 0xf800707f |
| 211 | #define MATCH_AMOXOR_D 0x2000302f |
| 212 | #define MASK_AMOXOR_D 0xf800707f |
| 213 | #define MATCH_AMOXOR_W 0x2000202f |
| 214 | #define MASK_AMOXOR_W 0xf800707f |
| 215 | #define MATCH_AND 0x7033 |
| 216 | #define MASK_AND 0xfe00707f |
| 217 | #define MATCH_ANDI 0x7013 |
| 218 | #define MASK_ANDI 0x707f |
| 219 | #define MATCH_AUIPC 0x17 |
| 220 | #define MASK_AUIPC 0x7f |
| 221 | #define MATCH_BEQ 0x63 |
| 222 | #define MASK_BEQ 0x707f |
| 223 | #define MATCH_BGE 0x5063 |
| 224 | #define MASK_BGE 0x707f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 225 | #define MATCH_BGEU 0x7063 |
| 226 | #define MASK_BGEU 0x707f |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 227 | #define MATCH_BLT 0x4063 |
| 228 | #define MASK_BLT 0x707f |
| 229 | #define MATCH_BLTU 0x6063 |
| 230 | #define MASK_BLTU 0x707f |
| 231 | #define MATCH_BNE 0x1063 |
| 232 | #define MASK_BNE 0x707f |
| 233 | #define MATCH_C_ADD 0x1000 |
| 234 | #define MASK_C_ADD 0xf003 |
| 235 | #define MATCH_C_ADD3 0xa000 |
| 236 | #define MASK_C_ADD3 0xe063 |
| 237 | #define MATCH_C_ADDI 0xc002 |
| 238 | #define MASK_C_ADDI 0xe003 |
| 239 | #define MATCH_C_ADDI4SPN 0xa001 |
| 240 | #define MASK_C_ADDI4SPN 0xe003 |
| 241 | #define MATCH_C_ADDIW 0xe002 |
| 242 | #define MASK_C_ADDIW 0xe003 |
| 243 | #define MATCH_C_ADDW 0x9000 |
| 244 | #define MASK_C_ADDW 0xf003 |
| 245 | #define MATCH_C_AND3 0xa060 |
| 246 | #define MASK_C_AND3 0xe063 |
| 247 | #define MATCH_C_BEQZ 0x4002 |
| 248 | #define MASK_C_BEQZ 0xe003 |
| 249 | #define MATCH_C_BNEZ 0x6002 |
| 250 | #define MASK_C_BNEZ 0xe003 |
| 251 | #define MATCH_C_J 0x2 |
| 252 | #define MASK_C_J 0xe003 |
| 253 | #define MATCH_C_JAL 0x2002 |
| 254 | #define MASK_C_JAL 0xe003 |
| 255 | #define MATCH_C_LD 0xe000 |
| 256 | #define MASK_C_LD 0xe003 |
| 257 | #define MATCH_C_LDSP 0xe001 |
| 258 | #define MASK_C_LDSP 0xe003 |
| 259 | #define MATCH_C_LI 0x8002 |
| 260 | #define MASK_C_LI 0xe003 |
| 261 | #define MATCH_C_LUI 0xa002 |
| 262 | #define MASK_C_LUI 0xe003 |
| 263 | #define MATCH_C_LW 0xc000 |
| 264 | #define MASK_C_LW 0xe003 |
| 265 | #define MATCH_C_LWSP 0xc001 |
| 266 | #define MASK_C_LWSP 0xe003 |
| 267 | #define MATCH_C_MV 0x0 |
| 268 | #define MASK_C_MV 0xf003 |
| 269 | #define MATCH_C_OR3 0xa040 |
| 270 | #define MASK_C_OR3 0xe063 |
| 271 | #define MATCH_C_SD 0x6000 |
| 272 | #define MASK_C_SD 0xe003 |
| 273 | #define MATCH_C_SDSP 0x6001 |
| 274 | #define MASK_C_SDSP 0xe003 |
| 275 | #define MATCH_C_SLLI 0x1 |
| 276 | #define MASK_C_SLLI 0xe003 |
| 277 | #define MATCH_C_SLLIW 0x8001 |
| 278 | #define MASK_C_SLLIW 0xe003 |
| 279 | #define MATCH_C_SRAI 0x2000 |
| 280 | #define MASK_C_SRAI 0xe003 |
| 281 | #define MATCH_C_SRLI 0x2001 |
| 282 | #define MASK_C_SRLI 0xe003 |
| 283 | #define MATCH_C_SUB 0x8000 |
| 284 | #define MASK_C_SUB 0xf003 |
| 285 | #define MATCH_C_SUB3 0xa020 |
| 286 | #define MASK_C_SUB3 0xe063 |
| 287 | #define MATCH_C_SW 0x4000 |
| 288 | #define MASK_C_SW 0xe003 |
| 289 | #define MATCH_C_SWSP 0x4001 |
| 290 | #define MASK_C_SWSP 0xe003 |
| 291 | #define MATCH_CSRRC 0x3073 |
| 292 | #define MASK_CSRRC 0x707f |
| 293 | #define MATCH_CSRRCI 0x7073 |
| 294 | #define MASK_CSRRCI 0x707f |
| 295 | #define MATCH_CSRRS 0x2073 |
| 296 | #define MASK_CSRRS 0x707f |
| 297 | #define MATCH_CSRRSI 0x6073 |
| 298 | #define MASK_CSRRSI 0x707f |
| 299 | #define MATCH_CSRRW 0x1073 |
| 300 | #define MASK_CSRRW 0x707f |
| 301 | #define MATCH_CSRRWI 0x5073 |
| 302 | #define MASK_CSRRWI 0x707f |
| 303 | #define MATCH_DIV 0x2004033 |
| 304 | #define MASK_DIV 0xfe00707f |
| 305 | #define MATCH_DIVU 0x2005033 |
| 306 | #define MASK_DIVU 0xfe00707f |
| 307 | #define MATCH_DIVUW 0x200503b |
| 308 | #define MASK_DIVUW 0xfe00707f |
| 309 | #define MATCH_DIVW 0x200403b |
| 310 | #define MASK_DIVW 0xfe00707f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 311 | #define MATCH_FADD_D 0x2000053 |
| 312 | #define MASK_FADD_D 0xfe00007f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 313 | #define MATCH_FADD_S 0x53 |
| 314 | #define MASK_FADD_S 0xfe00007f |
| 315 | #define MATCH_FCLASS_D 0xe2001053 |
| 316 | #define MASK_FCLASS_D 0xfff0707f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 317 | #define MATCH_FCLASS_S 0xe0001053 |
| 318 | #define MASK_FCLASS_S 0xfff0707f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 319 | #define MATCH_FCVT_D_L 0xd2200053 |
| 320 | #define MASK_FCVT_D_L 0xfff0007f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 321 | #define MATCH_FCVT_D_LU 0xd2300053 |
| 322 | #define MASK_FCVT_D_LU 0xfff0007f |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 323 | #define MATCH_FCVT_D_S 0x42000053 |
| 324 | #define MASK_FCVT_D_S 0xfff0007f |
| 325 | #define MATCH_FCVT_D_W 0xd2000053 |
| 326 | #define MASK_FCVT_D_W 0xfff0007f |
| 327 | #define MATCH_FCVT_D_WU 0xd2100053 |
| 328 | #define MASK_FCVT_D_WU 0xfff0007f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 329 | #define MATCH_FCVT_L_D 0xc2200053 |
| 330 | #define MASK_FCVT_L_D 0xfff0007f |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 331 | #define MATCH_FCVT_L_S 0xc0200053 |
| 332 | #define MASK_FCVT_L_S 0xfff0007f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 333 | #define MATCH_FCVT_LU_D 0xc2300053 |
| 334 | #define MASK_FCVT_LU_D 0xfff0007f |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 335 | #define MATCH_FCVT_LU_S 0xc0300053 |
| 336 | #define MASK_FCVT_LU_S 0xfff0007f |
| 337 | #define MATCH_FCVT_S_D 0x40100053 |
| 338 | #define MASK_FCVT_S_D 0xfff0007f |
| 339 | #define MATCH_FCVT_S_L 0xd0200053 |
| 340 | #define MASK_FCVT_S_L 0xfff0007f |
| 341 | #define MATCH_FCVT_S_LU 0xd0300053 |
| 342 | #define MASK_FCVT_S_LU 0xfff0007f |
| 343 | #define MATCH_FCVT_S_W 0xd0000053 |
| 344 | #define MASK_FCVT_S_W 0xfff0007f |
| 345 | #define MATCH_FCVT_S_WU 0xd0100053 |
| 346 | #define MASK_FCVT_S_WU 0xfff0007f |
| 347 | #define MATCH_FCVT_W_D 0xc2000053 |
| 348 | #define MASK_FCVT_W_D 0xfff0007f |
| 349 | #define MATCH_FCVT_W_S 0xc0000053 |
| 350 | #define MASK_FCVT_W_S 0xfff0007f |
| 351 | #define MATCH_FCVT_WU_D 0xc2100053 |
| 352 | #define MASK_FCVT_WU_D 0xfff0007f |
| 353 | #define MATCH_FCVT_WU_S 0xc0100053 |
| 354 | #define MASK_FCVT_WU_S 0xfff0007f |
| 355 | #define MATCH_FDIV_D 0x1a000053 |
| 356 | #define MASK_FDIV_D 0xfe00007f |
| 357 | #define MATCH_FDIV_S 0x18000053 |
| 358 | #define MASK_FDIV_S 0xfe00007f |
| 359 | #define MATCH_FENCE 0xf |
| 360 | #define MASK_FENCE 0x707f |
| 361 | #define MATCH_FENCE_I 0x100f |
| 362 | #define MASK_FENCE_I 0x707f |
| 363 | #define MATCH_FEQ_D 0xa2002053 |
| 364 | #define MASK_FEQ_D 0xfe00707f |
| 365 | #define MATCH_FEQ_S 0xa0002053 |
| 366 | #define MASK_FEQ_S 0xfe00707f |
| 367 | #define MATCH_FLD 0x3007 |
| 368 | #define MASK_FLD 0x707f |
| 369 | #define MATCH_FLE_D 0xa2000053 |
| 370 | #define MASK_FLE_D 0xfe00707f |
| 371 | #define MATCH_FLE_S 0xa0000053 |
| 372 | #define MASK_FLE_S 0xfe00707f |
| 373 | #define MATCH_FLT_D 0xa2001053 |
| 374 | #define MASK_FLT_D 0xfe00707f |
| 375 | #define MATCH_FLT_S 0xa0001053 |
| 376 | #define MASK_FLT_S 0xfe00707f |
| 377 | #define MATCH_FLW 0x2007 |
| 378 | #define MASK_FLW 0x707f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 379 | #define MATCH_FMADD_D 0x2000043 |
| 380 | #define MASK_FMADD_D 0x600007f |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 381 | #define MATCH_FMADD_S 0x43 |
| 382 | #define MASK_FMADD_S 0x600007f |
| 383 | #define MATCH_FMAX_D 0x2a001053 |
| 384 | #define MASK_FMAX_D 0xfe00707f |
| 385 | #define MATCH_FMAX_S 0x28001053 |
| 386 | #define MASK_FMAX_S 0xfe00707f |
| 387 | #define MATCH_FMIN_D 0x2a000053 |
| 388 | #define MASK_FMIN_D 0xfe00707f |
| 389 | #define MATCH_FMIN_S 0x28000053 |
| 390 | #define MASK_FMIN_S 0xfe00707f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 391 | #define MATCH_FMSUB_D 0x2000047 |
| 392 | #define MASK_FMSUB_D 0x600007f |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 393 | #define MATCH_FMSUB_S 0x47 |
| 394 | #define MASK_FMSUB_S 0x600007f |
| 395 | #define MATCH_FMUL_D 0x12000053 |
| 396 | #define MASK_FMUL_D 0xfe00007f |
| 397 | #define MATCH_FMUL_S 0x10000053 |
| 398 | #define MASK_FMUL_S 0xfe00007f |
| 399 | #define MATCH_FMV_D_X 0xf2000053 |
| 400 | #define MASK_FMV_D_X 0xfff0707f |
| 401 | #define MATCH_FMV_S_X 0xf0000053 |
| 402 | #define MASK_FMV_S_X 0xfff0707f |
| 403 | #define MATCH_FMV_X_D 0xe2000053 |
| 404 | #define MASK_FMV_X_D 0xfff0707f |
| 405 | #define MATCH_FMV_X_S 0xe0000053 |
| 406 | #define MASK_FMV_X_S 0xfff0707f |
| 407 | #define MATCH_FNMADD_D 0x200004f |
| 408 | #define MASK_FNMADD_D 0x600007f |
| 409 | #define MATCH_FNMADD_S 0x4f |
| 410 | #define MASK_FNMADD_S 0x600007f |
| 411 | #define MATCH_FNMSUB_D 0x200004b |
| 412 | #define MASK_FNMSUB_D 0x600007f |
| 413 | #define MATCH_FNMSUB_S 0x4b |
| 414 | #define MASK_FNMSUB_S 0x600007f |
| 415 | #define MATCH_FSD 0x3027 |
| 416 | #define MASK_FSD 0x707f |
| 417 | #define MATCH_FSGNJ_D 0x22000053 |
| 418 | #define MASK_FSGNJ_D 0xfe00707f |
| 419 | #define MATCH_FSGNJ_S 0x20000053 |
| 420 | #define MASK_FSGNJ_S 0xfe00707f |
| 421 | #define MATCH_FSGNJN_D 0x22001053 |
| 422 | #define MASK_FSGNJN_D 0xfe00707f |
| 423 | #define MATCH_FSGNJN_S 0x20001053 |
| 424 | #define MASK_FSGNJN_S 0xfe00707f |
| 425 | #define MATCH_FSGNJX_D 0x22002053 |
| 426 | #define MASK_FSGNJX_D 0xfe00707f |
| 427 | #define MATCH_FSGNJX_S 0x20002053 |
| 428 | #define MASK_FSGNJX_S 0xfe00707f |
| 429 | #define MATCH_FSQRT_D 0x5a000053 |
| 430 | #define MASK_FSQRT_D 0xfff0007f |
| 431 | #define MATCH_FSQRT_S 0x58000053 |
| 432 | #define MASK_FSQRT_S 0xfff0007f |
| 433 | #define MATCH_FSUB_D 0xa000053 |
| 434 | #define MASK_FSUB_D 0xfe00007f |
| 435 | #define MATCH_FSUB_S 0x8000053 |
| 436 | #define MASK_FSUB_S 0xfe00007f |
| 437 | #define MATCH_FSW 0x2027 |
| 438 | #define MASK_FSW 0x707f |
| 439 | #define MATCH_HRTS 0x20500073 |
| 440 | #define MASK_HRTS 0xffffffff |
| 441 | #define MATCH_JAL 0x6f |
| 442 | #define MASK_JAL 0x7f |
| 443 | #define MATCH_JALR 0x67 |
| 444 | #define MASK_JALR 0x707f |
| 445 | #define MATCH_LB 0x3 |
| 446 | #define MASK_LB 0x707f |
| 447 | #define MATCH_LBU 0x4003 |
| 448 | #define MASK_LBU 0x707f |
| 449 | #define MATCH_LD 0x3003 |
| 450 | #define MASK_LD 0x707f |
| 451 | #define MATCH_LH 0x1003 |
| 452 | #define MASK_LH 0x707f |
| 453 | #define MATCH_LHU 0x5003 |
| 454 | #define MASK_LHU 0x707f |
| 455 | #define MATCH_LR_D 0x1000302f |
| 456 | #define MASK_LR_D 0xf9f0707f |
| 457 | #define MATCH_LR_W 0x1000202f |
| 458 | #define MASK_LR_W 0xf9f0707f |
| 459 | #define MATCH_LUI 0x37 |
| 460 | #define MASK_LUI 0x7f |
| 461 | #define MATCH_LW 0x2003 |
| 462 | #define MASK_LW 0x707f |
| 463 | #define MATCH_LWU 0x6003 |
| 464 | #define MASK_LWU 0x707f |
| 465 | #define MATCH_MRTH 0x30600073 |
| 466 | #define MASK_MRTH 0xffffffff |
| 467 | #define MATCH_MRTS 0x30500073 |
| 468 | #define MASK_MRTS 0xffffffff |
| 469 | #define MATCH_MUL 0x2000033 |
| 470 | #define MASK_MUL 0xfe00707f |
| 471 | #define MATCH_MULH 0x2001033 |
| 472 | #define MASK_MULH 0xfe00707f |
| 473 | #define MATCH_MULHSU 0x2002033 |
| 474 | #define MASK_MULHSU 0xfe00707f |
| 475 | #define MATCH_MULHU 0x2003033 |
| 476 | #define MASK_MULHU 0xfe00707f |
| 477 | #define MATCH_MULW 0x200003b |
| 478 | #define MASK_MULW 0xfe00707f |
| 479 | #define MATCH_OR 0x6033 |
| 480 | #define MASK_OR 0xfe00707f |
| 481 | #define MATCH_ORI 0x6013 |
| 482 | #define MASK_ORI 0x707f |
| 483 | #define MATCH_REM 0x2006033 |
| 484 | #define MASK_REM 0xfe00707f |
| 485 | #define MATCH_REMU 0x2007033 |
| 486 | #define MASK_REMU 0xfe00707f |
| 487 | #define MATCH_REMUW 0x200703b |
| 488 | #define MASK_REMUW 0xfe00707f |
| 489 | #define MATCH_REMW 0x200603b |
| 490 | #define MASK_REMW 0xfe00707f |
| 491 | #define MATCH_SB 0x23 |
| 492 | #define MASK_SB 0x707f |
| 493 | #define MATCH_SBREAK 0x100073 |
| 494 | #define MASK_SBREAK 0xffffffff |
| 495 | #define MATCH_SC_D 0x1800302f |
| 496 | #define MASK_SC_D 0xf800707f |
| 497 | #define MATCH_SC_W 0x1800202f |
| 498 | #define MASK_SC_W 0xf800707f |
| 499 | #define MATCH_SCALL 0x73 |
| 500 | #define MASK_SCALL 0xffffffff |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 501 | #define MATCH_SD 0x3023 |
| 502 | #define MASK_SD 0x707f |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 503 | #define MATCH_SFENCE_VM 0x10100073 |
| 504 | #define MASK_SFENCE_VM 0xfff07fff |
| 505 | #define MATCH_SH 0x1023 |
| 506 | #define MASK_SH 0x707f |
| 507 | #define MATCH_SLL 0x1033 |
| 508 | #define MASK_SLL 0xfe00707f |
| 509 | #define MATCH_SLLI 0x1013 |
| 510 | #define MASK_SLLI 0xfc00707f |
| 511 | #define MATCH_SLLIW 0x101b |
| 512 | #define MASK_SLLIW 0xfe00707f |
| 513 | #define MATCH_SLLW 0x103b |
| 514 | #define MASK_SLLW 0xfe00707f |
| 515 | #define MATCH_SLT 0x2033 |
| 516 | #define MASK_SLT 0xfe00707f |
| 517 | #define MATCH_SLTI 0x2013 |
| 518 | #define MASK_SLTI 0x707f |
| 519 | #define MATCH_SLTIU 0x3013 |
| 520 | #define MASK_SLTIU 0x707f |
| 521 | #define MATCH_SLTU 0x3033 |
| 522 | #define MASK_SLTU 0xfe00707f |
| 523 | #define MATCH_SRA 0x40005033 |
| 524 | #define MASK_SRA 0xfe00707f |
| 525 | #define MATCH_SRAI 0x40005013 |
| 526 | #define MASK_SRAI 0xfc00707f |
| 527 | #define MATCH_SRAIW 0x4000501b |
| 528 | #define MASK_SRAIW 0xfe00707f |
| 529 | #define MATCH_SRAW 0x4000503b |
| 530 | #define MASK_SRAW 0xfe00707f |
| 531 | #define MATCH_SRET 0x10000073 |
| 532 | #define MASK_SRET 0xffffffff |
| 533 | #define MATCH_SRL 0x5033 |
| 534 | #define MASK_SRL 0xfe00707f |
| 535 | #define MATCH_SRLI 0x5013 |
| 536 | #define MASK_SRLI 0xfc00707f |
| 537 | #define MATCH_SRLIW 0x501b |
| 538 | #define MASK_SRLIW 0xfe00707f |
| 539 | #define MATCH_SRLW 0x503b |
| 540 | #define MASK_SRLW 0xfe00707f |
| 541 | #define MATCH_SUB 0x40000033 |
| 542 | #define MASK_SUB 0xfe00707f |
| 543 | #define MATCH_SUBW 0x4000003b |
| 544 | #define MASK_SUBW 0xfe00707f |
| 545 | #define MATCH_SW 0x2023 |
| 546 | #define MASK_SW 0x707f |
| 547 | #define MATCH_WFI 0x10200073 |
| 548 | #define MASK_WFI 0xffffffff |
| 549 | #define MATCH_XOR 0x4033 |
| 550 | #define MASK_XOR 0xfe00707f |
| 551 | #define MATCH_XORI 0x4013 |
| 552 | #define MASK_XORI 0x707f |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 553 | #define CSR_FFLAGS 0x1 |
| 554 | #define CSR_FRM 0x2 |
| 555 | #define CSR_FCSR 0x3 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 556 | #define CSR_CYCLE 0xc00 |
| 557 | #define CSR_TIME 0xc01 |
| 558 | #define CSR_INSTRET 0xc02 |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 559 | #define CSR_STATS 0xc0 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 560 | #define CSR_UARCH0 0xcc0 |
| 561 | #define CSR_UARCH1 0xcc1 |
| 562 | #define CSR_UARCH2 0xcc2 |
| 563 | #define CSR_UARCH3 0xcc3 |
| 564 | #define CSR_UARCH4 0xcc4 |
| 565 | #define CSR_UARCH5 0xcc5 |
| 566 | #define CSR_UARCH6 0xcc6 |
| 567 | #define CSR_UARCH7 0xcc7 |
| 568 | #define CSR_UARCH8 0xcc8 |
| 569 | #define CSR_UARCH9 0xcc9 |
| 570 | #define CSR_UARCH10 0xcca |
| 571 | #define CSR_UARCH11 0xccb |
| 572 | #define CSR_UARCH12 0xccc |
| 573 | #define CSR_UARCH13 0xccd |
| 574 | #define CSR_UARCH14 0xcce |
| 575 | #define CSR_UARCH15 0xccf |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 576 | #define CSR_SSTATUS 0x100 |
| 577 | #define CSR_STVEC 0x101 |
| 578 | #define CSR_SIE 0x104 |
| 579 | #define CSR_SSCRATCH 0x140 |
| 580 | #define CSR_SEPC 0x141 |
| 581 | #define CSR_SIP 0x144 |
| 582 | #define CSR_SPTBR 0x180 |
| 583 | #define CSR_SASID 0x181 |
| 584 | #define CSR_CYCLEW 0x900 |
| 585 | #define CSR_TIMEW 0x901 |
| 586 | #define CSR_INSTRETW 0x902 |
| 587 | #define CSR_STIME 0xd01 |
| 588 | #define CSR_SCAUSE 0xd42 |
| 589 | #define CSR_SBADADDR 0xd43 |
| 590 | #define CSR_STIMEW 0xa01 |
| 591 | #define CSR_MSTATUS 0x300 |
| 592 | #define CSR_MTVEC 0x301 |
| 593 | #define CSR_MTDELEG 0x302 |
| 594 | #define CSR_MIE 0x304 |
| 595 | #define CSR_MTIMECMP 0x321 |
| 596 | #define CSR_MSCRATCH 0x340 |
| 597 | #define CSR_MEPC 0x341 |
| 598 | #define CSR_MCAUSE 0x342 |
| 599 | #define CSR_MBADADDR 0x343 |
| 600 | #define CSR_MIP 0x344 |
| 601 | #define CSR_MTIME 0x701 |
| 602 | #define CSR_MCPUID 0xf00 |
| 603 | #define CSR_MIMPID 0xf01 |
| 604 | #define CSR_MHARTID 0xf10 |
| 605 | #define CSR_MTOHOST 0x780 |
| 606 | #define CSR_MFROMHOST 0x781 |
| 607 | #define CSR_MRESET 0x782 |
| 608 | #define CSR_SEND_IPI 0x783 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 609 | #define CSR_CYCLEH 0xc80 |
| 610 | #define CSR_TIMEH 0xc81 |
| 611 | #define CSR_INSTRETH 0xc82 |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 612 | #define CSR_CYCLEHW 0x980 |
| 613 | #define CSR_TIMEHW 0x981 |
| 614 | #define CSR_INSTRETHW 0x982 |
| 615 | #define CSR_STIMEH 0xd81 |
| 616 | #define CSR_STIMEHW 0xa81 |
| 617 | #define CSR_MTIMECMPH 0x361 |
| 618 | #define CSR_MTIMEH 0x741 |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 619 | #define CAUSE_MISALIGNED_FETCH 0x0 |
| 620 | #define CAUSE_FAULT_FETCH 0x1 |
| 621 | #define CAUSE_ILLEGAL_INSTRUCTION 0x2 |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 622 | #define CAUSE_BREAKPOINT 0x3 |
| 623 | #define CAUSE_MISALIGNED_LOAD 0x4 |
| 624 | #define CAUSE_FAULT_LOAD 0x5 |
| 625 | #define CAUSE_MISALIGNED_STORE 0x6 |
| 626 | #define CAUSE_FAULT_STORE 0x7 |
| 627 | #define CAUSE_USER_ECALL 0x8 |
| 628 | #define CAUSE_SUPERVISOR_ECALL 0x9 |
| 629 | #define CAUSE_HYPERVISOR_ECALL 0xa |
| 630 | #define CAUSE_MACHINE_ECALL 0xb |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 631 | #endif |
| 632 | #ifdef DECLARE_INSN |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 633 | DECLARE_INSN(add, MATCH_ADD, MASK_ADD) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 634 | DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) |
| 635 | DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) |
| 636 | DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) |
| 637 | DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) |
| 638 | DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) |
| 639 | DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) |
| 640 | DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) |
| 641 | DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) |
| 642 | DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) |
| 643 | DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) |
| 644 | DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) |
| 645 | DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) |
| 646 | DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) |
| 647 | DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) |
| 648 | DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) |
| 649 | DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) |
| 650 | DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) |
| 651 | DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) |
| 652 | DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) |
| 653 | DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) |
| 654 | DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) |
| 655 | DECLARE_INSN(and, MATCH_AND, MASK_AND) |
| 656 | DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) |
| 657 | DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) |
| 658 | DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) |
| 659 | DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 660 | DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 661 | DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) |
| 662 | DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) |
| 663 | DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) |
| 664 | DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) |
| 665 | DECLARE_INSN(c_add3, MATCH_C_ADD3, MASK_C_ADD3) |
| 666 | DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) |
| 667 | DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) |
| 668 | DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) |
| 669 | DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) |
| 670 | DECLARE_INSN(c_and3, MATCH_C_AND3, MASK_C_AND3) |
| 671 | DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) |
| 672 | DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) |
| 673 | DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) |
| 674 | DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) |
| 675 | DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) |
| 676 | DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) |
| 677 | DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) |
| 678 | DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) |
| 679 | DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) |
| 680 | DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) |
| 681 | DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) |
| 682 | DECLARE_INSN(c_or3, MATCH_C_OR3, MASK_C_OR3) |
| 683 | DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) |
| 684 | DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) |
| 685 | DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) |
| 686 | DECLARE_INSN(c_slliw, MATCH_C_SLLIW, MASK_C_SLLIW) |
| 687 | DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) |
| 688 | DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) |
| 689 | DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) |
| 690 | DECLARE_INSN(c_sub3, MATCH_C_SUB3, MASK_C_SUB3) |
| 691 | DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) |
| 692 | DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) |
| 693 | DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) |
| 694 | DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) |
| 695 | DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) |
| 696 | DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) |
| 697 | DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) |
| 698 | DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) |
| 699 | DECLARE_INSN(div, MATCH_DIV, MASK_DIV) |
| 700 | DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) |
| 701 | DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) |
| 702 | DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 703 | DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 704 | DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) |
| 705 | DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 706 | DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 707 | DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 708 | DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 709 | DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) |
| 710 | DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) |
| 711 | DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 712 | DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 713 | DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 714 | DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 715 | DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) |
| 716 | DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) |
| 717 | DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) |
| 718 | DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) |
| 719 | DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) |
| 720 | DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) |
| 721 | DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) |
| 722 | DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) |
| 723 | DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) |
| 724 | DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) |
| 725 | DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) |
| 726 | DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) |
| 727 | DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) |
| 728 | DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) |
| 729 | DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) |
| 730 | DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) |
| 731 | DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) |
| 732 | DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) |
| 733 | DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) |
| 734 | DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) |
| 735 | DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) |
| 736 | DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 737 | DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 738 | DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) |
| 739 | DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) |
| 740 | DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) |
| 741 | DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) |
| 742 | DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 743 | DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 744 | DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) |
| 745 | DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) |
| 746 | DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) |
| 747 | DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) |
| 748 | DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) |
| 749 | DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) |
| 750 | DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) |
| 751 | DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) |
| 752 | DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) |
| 753 | DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) |
| 754 | DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) |
| 755 | DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) |
| 756 | DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) |
| 757 | DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) |
| 758 | DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) |
| 759 | DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) |
| 760 | DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) |
| 761 | DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) |
| 762 | DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) |
| 763 | DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) |
| 764 | DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) |
| 765 | DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) |
| 766 | DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) |
| 767 | DECLARE_INSN(hrts, MATCH_HRTS, MASK_HRTS) |
| 768 | DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) |
| 769 | DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) |
| 770 | DECLARE_INSN(lb, MATCH_LB, MASK_LB) |
| 771 | DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) |
| 772 | DECLARE_INSN(ld, MATCH_LD, MASK_LD) |
| 773 | DECLARE_INSN(lh, MATCH_LH, MASK_LH) |
| 774 | DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) |
| 775 | DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) |
| 776 | DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) |
| 777 | DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) |
| 778 | DECLARE_INSN(lw, MATCH_LW, MASK_LW) |
| 779 | DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) |
| 780 | DECLARE_INSN(mrth, MATCH_MRTH, MASK_MRTH) |
| 781 | DECLARE_INSN(mrts, MATCH_MRTS, MASK_MRTS) |
| 782 | DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) |
| 783 | DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) |
| 784 | DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) |
| 785 | DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) |
| 786 | DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) |
| 787 | DECLARE_INSN(or, MATCH_OR, MASK_OR) |
| 788 | DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) |
| 789 | DECLARE_INSN(rem, MATCH_REM, MASK_REM) |
| 790 | DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) |
| 791 | DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) |
| 792 | DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) |
| 793 | DECLARE_INSN(sb, MATCH_SB, MASK_SB) |
| 794 | DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) |
| 795 | DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) |
| 796 | DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) |
| 797 | DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 798 | DECLARE_INSN(sd, MATCH_SD, MASK_SD) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 799 | DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) |
| 800 | DECLARE_INSN(sh, MATCH_SH, MASK_SH) |
| 801 | DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) |
| 802 | DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) |
| 803 | DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) |
| 804 | DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) |
| 805 | DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) |
| 806 | DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) |
| 807 | DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) |
| 808 | DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) |
| 809 | DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) |
| 810 | DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) |
| 811 | DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) |
| 812 | DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) |
| 813 | DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) |
| 814 | DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) |
| 815 | DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) |
| 816 | DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) |
| 817 | DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) |
| 818 | DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) |
| 819 | DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) |
| 820 | DECLARE_INSN(sw, MATCH_SW, MASK_SW) |
| 821 | DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) |
| 822 | DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) |
| 823 | DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 824 | #endif |
| 825 | #ifdef DECLARE_CSR |
| 826 | DECLARE_CSR(fflags, CSR_FFLAGS) |
| 827 | DECLARE_CSR(frm, CSR_FRM) |
| 828 | DECLARE_CSR(fcsr, CSR_FCSR) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 829 | DECLARE_CSR(cycle, CSR_CYCLE) |
| 830 | DECLARE_CSR(time, CSR_TIME) |
| 831 | DECLARE_CSR(instret, CSR_INSTRET) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 832 | DECLARE_CSR(stats, CSR_STATS) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 833 | DECLARE_CSR(uarch0, CSR_UARCH0) |
| 834 | DECLARE_CSR(uarch1, CSR_UARCH1) |
| 835 | DECLARE_CSR(uarch2, CSR_UARCH2) |
| 836 | DECLARE_CSR(uarch3, CSR_UARCH3) |
| 837 | DECLARE_CSR(uarch4, CSR_UARCH4) |
| 838 | DECLARE_CSR(uarch5, CSR_UARCH5) |
| 839 | DECLARE_CSR(uarch6, CSR_UARCH6) |
| 840 | DECLARE_CSR(uarch7, CSR_UARCH7) |
| 841 | DECLARE_CSR(uarch8, CSR_UARCH8) |
| 842 | DECLARE_CSR(uarch9, CSR_UARCH9) |
| 843 | DECLARE_CSR(uarch10, CSR_UARCH10) |
| 844 | DECLARE_CSR(uarch11, CSR_UARCH11) |
| 845 | DECLARE_CSR(uarch12, CSR_UARCH12) |
| 846 | DECLARE_CSR(uarch13, CSR_UARCH13) |
| 847 | DECLARE_CSR(uarch14, CSR_UARCH14) |
| 848 | DECLARE_CSR(uarch15, CSR_UARCH15) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 849 | DECLARE_CSR(sstatus, CSR_SSTATUS) |
| 850 | DECLARE_CSR(stvec, CSR_STVEC) |
| 851 | DECLARE_CSR(sie, CSR_SIE) |
| 852 | DECLARE_CSR(sscratch, CSR_SSCRATCH) |
| 853 | DECLARE_CSR(sepc, CSR_SEPC) |
| 854 | DECLARE_CSR(sip, CSR_SIP) |
| 855 | DECLARE_CSR(sptbr, CSR_SPTBR) |
| 856 | DECLARE_CSR(sasid, CSR_SASID) |
| 857 | DECLARE_CSR(cyclew, CSR_CYCLEW) |
| 858 | DECLARE_CSR(timew, CSR_TIMEW) |
| 859 | DECLARE_CSR(instretw, CSR_INSTRETW) |
| 860 | DECLARE_CSR(stime, CSR_STIME) |
| 861 | DECLARE_CSR(scause, CSR_SCAUSE) |
| 862 | DECLARE_CSR(sbadaddr, CSR_SBADADDR) |
| 863 | DECLARE_CSR(stimew, CSR_STIMEW) |
| 864 | DECLARE_CSR(mstatus, CSR_MSTATUS) |
| 865 | DECLARE_CSR(mtvec, CSR_MTVEC) |
| 866 | DECLARE_CSR(mtdeleg, CSR_MTDELEG) |
| 867 | DECLARE_CSR(mie, CSR_MIE) |
| 868 | DECLARE_CSR(mtimecmp, CSR_MTIMECMP) |
| 869 | DECLARE_CSR(mscratch, CSR_MSCRATCH) |
| 870 | DECLARE_CSR(mepc, CSR_MEPC) |
| 871 | DECLARE_CSR(mcause, CSR_MCAUSE) |
| 872 | DECLARE_CSR(mbadaddr, CSR_MBADADDR) |
| 873 | DECLARE_CSR(mip, CSR_MIP) |
| 874 | DECLARE_CSR(mtime, CSR_MTIME) |
| 875 | DECLARE_CSR(mcpuid, CSR_MCPUID) |
| 876 | DECLARE_CSR(mimpid, CSR_MIMPID) |
| 877 | DECLARE_CSR(mhartid, CSR_MHARTID) |
| 878 | DECLARE_CSR(mtohost, CSR_MTOHOST) |
| 879 | DECLARE_CSR(mfromhost, CSR_MFROMHOST) |
| 880 | DECLARE_CSR(mreset, CSR_MRESET) |
| 881 | DECLARE_CSR(send_ipi, CSR_SEND_IPI) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 882 | DECLARE_CSR(cycleh, CSR_CYCLEH) |
| 883 | DECLARE_CSR(timeh, CSR_TIMEH) |
| 884 | DECLARE_CSR(instreth, CSR_INSTRETH) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 885 | DECLARE_CSR(cyclehw, CSR_CYCLEHW) |
| 886 | DECLARE_CSR(timehw, CSR_TIMEHW) |
| 887 | DECLARE_CSR(instrethw, CSR_INSTRETHW) |
| 888 | DECLARE_CSR(stimeh, CSR_STIMEH) |
| 889 | DECLARE_CSR(stimehw, CSR_STIMEHW) |
| 890 | DECLARE_CSR(mtimecmph, CSR_MTIMECMPH) |
| 891 | DECLARE_CSR(mtimeh, CSR_MTIMEH) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 892 | #endif |
| 893 | #ifdef DECLARE_CAUSE |
| 894 | DECLARE_CAUSE("fflags", CAUSE_FFLAGS) |
| 895 | DECLARE_CAUSE("frm", CAUSE_FRM) |
| 896 | DECLARE_CAUSE("fcsr", CAUSE_FCSR) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 897 | DECLARE_CAUSE("cycle", CAUSE_CYCLE) |
| 898 | DECLARE_CAUSE("time", CAUSE_TIME) |
| 899 | DECLARE_CAUSE("instret", CAUSE_INSTRET) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 900 | DECLARE_CAUSE("stats", CAUSE_STATS) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 901 | DECLARE_CAUSE("uarch0", CAUSE_UARCH0) |
| 902 | DECLARE_CAUSE("uarch1", CAUSE_UARCH1) |
| 903 | DECLARE_CAUSE("uarch2", CAUSE_UARCH2) |
| 904 | DECLARE_CAUSE("uarch3", CAUSE_UARCH3) |
| 905 | DECLARE_CAUSE("uarch4", CAUSE_UARCH4) |
| 906 | DECLARE_CAUSE("uarch5", CAUSE_UARCH5) |
| 907 | DECLARE_CAUSE("uarch6", CAUSE_UARCH6) |
| 908 | DECLARE_CAUSE("uarch7", CAUSE_UARCH7) |
| 909 | DECLARE_CAUSE("uarch8", CAUSE_UARCH8) |
| 910 | DECLARE_CAUSE("uarch9", CAUSE_UARCH9) |
| 911 | DECLARE_CAUSE("uarch10", CAUSE_UARCH10) |
| 912 | DECLARE_CAUSE("uarch11", CAUSE_UARCH11) |
| 913 | DECLARE_CAUSE("uarch12", CAUSE_UARCH12) |
| 914 | DECLARE_CAUSE("uarch13", CAUSE_UARCH13) |
| 915 | DECLARE_CAUSE("uarch14", CAUSE_UARCH14) |
| 916 | DECLARE_CAUSE("uarch15", CAUSE_UARCH15) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 917 | DECLARE_CAUSE("sstatus", CAUSE_SSTATUS) |
| 918 | DECLARE_CAUSE("stvec", CAUSE_STVEC) |
| 919 | DECLARE_CAUSE("sie", CAUSE_SIE) |
| 920 | DECLARE_CAUSE("sscratch", CAUSE_SSCRATCH) |
| 921 | DECLARE_CAUSE("sepc", CAUSE_SEPC) |
| 922 | DECLARE_CAUSE("sip", CAUSE_SIP) |
| 923 | DECLARE_CAUSE("sptbr", CAUSE_SPTBR) |
| 924 | DECLARE_CAUSE("sasid", CAUSE_SASID) |
| 925 | DECLARE_CAUSE("cyclew", CAUSE_CYCLEW) |
| 926 | DECLARE_CAUSE("timew", CAUSE_TIMEW) |
| 927 | DECLARE_CAUSE("instretw", CAUSE_INSTRETW) |
| 928 | DECLARE_CAUSE("stime", CAUSE_STIME) |
| 929 | DECLARE_CAUSE("scause", CAUSE_SCAUSE) |
| 930 | DECLARE_CAUSE("sbadaddr", CAUSE_SBADADDR) |
| 931 | DECLARE_CAUSE("stimew", CAUSE_STIMEW) |
| 932 | DECLARE_CAUSE("mstatus", CAUSE_MSTATUS) |
| 933 | DECLARE_CAUSE("mtvec", CAUSE_MTVEC) |
| 934 | DECLARE_CAUSE("mtdeleg", CAUSE_MTDELEG) |
| 935 | DECLARE_CAUSE("mie", CAUSE_MIE) |
| 936 | DECLARE_CAUSE("mtimecmp", CAUSE_MTIMECMP) |
| 937 | DECLARE_CAUSE("mscratch", CAUSE_MSCRATCH) |
| 938 | DECLARE_CAUSE("mepc", CAUSE_MEPC) |
| 939 | DECLARE_CAUSE("mcause", CAUSE_MCAUSE) |
| 940 | DECLARE_CAUSE("mbadaddr", CAUSE_MBADADDR) |
| 941 | DECLARE_CAUSE("mip", CAUSE_MIP) |
| 942 | DECLARE_CAUSE("mtime", CAUSE_MTIME) |
| 943 | DECLARE_CAUSE("mcpuid", CAUSE_MCPUID) |
| 944 | DECLARE_CAUSE("mimpid", CAUSE_MIMPID) |
| 945 | DECLARE_CAUSE("mhartid", CAUSE_MHARTID) |
| 946 | DECLARE_CAUSE("mtohost", CAUSE_MTOHOST) |
| 947 | DECLARE_CAUSE("mfromhost", CAUSE_MFROMHOST) |
| 948 | DECLARE_CAUSE("mreset", CAUSE_MRESET) |
| 949 | DECLARE_CAUSE("send_ipi", CAUSE_SEND_IPI) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 950 | DECLARE_CAUSE("cycleh", CAUSE_CYCLEH) |
| 951 | DECLARE_CAUSE("timeh", CAUSE_TIMEH) |
| 952 | DECLARE_CAUSE("instreth", CAUSE_INSTRETH) |
Thaminda Edirisooriya | 8fad21d | 2015-07-29 17:43:20 -0700 | [diff] [blame] | 953 | DECLARE_CAUSE("cyclehw", CAUSE_CYCLEHW) |
| 954 | DECLARE_CAUSE("timehw", CAUSE_TIMEHW) |
| 955 | DECLARE_CAUSE("instrethw", CAUSE_INSTRETHW) |
| 956 | DECLARE_CAUSE("stimeh", CAUSE_STIMEH) |
| 957 | DECLARE_CAUSE("stimehw", CAUSE_STIMEHW) |
| 958 | DECLARE_CAUSE("mtimecmph", CAUSE_MTIMECMPH) |
| 959 | DECLARE_CAUSE("mtimeh", CAUSE_MTIMEH) |
Ronald G. Minnich | e0e784a | 2014-11-26 19:25:47 +0000 | [diff] [blame] | 960 | #endif |