Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Chromium OS Authors |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <console/console.h> |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 18 | #include <bootmode.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 19 | #include <delay.h> |
Vladimir Serbinenko | f2e206a | 2014-02-23 00:13:56 +0100 | [diff] [blame] | 20 | #include <string.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 24 | #include <device/pci_ops.h> |
Nico Huber | 1822816 | 2017-06-08 16:31:57 +0200 | [diff] [blame] | 25 | #include <drivers/intel/gma/libgfxinit.h> |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 26 | #include <southbridge/intel/bd82x6x/nvs.h> |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 27 | #include <drivers/intel/gma/opregion.h> |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 28 | #include <cbmem.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 29 | |
| 30 | #include "chip.h" |
| 31 | #include "sandybridge.h" |
Patrick Rudolph | 45a0dbc | 2017-03-30 17:07:42 +0200 | [diff] [blame] | 32 | #include "gma.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 33 | |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 34 | struct gt_powermeter { |
| 35 | u16 reg; |
| 36 | u32 value; |
| 37 | }; |
| 38 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 39 | static const struct gt_powermeter snb_pm_gt1[] = { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 40 | { 0xa200, 0xcc000000 }, |
| 41 | { 0xa204, 0x07000040 }, |
| 42 | { 0xa208, 0x0000fe00 }, |
| 43 | { 0xa20c, 0x00000000 }, |
| 44 | { 0xa210, 0x17000000 }, |
| 45 | { 0xa214, 0x00000021 }, |
| 46 | { 0xa218, 0x0817fe19 }, |
| 47 | { 0xa21c, 0x00000000 }, |
| 48 | { 0xa220, 0x00000000 }, |
| 49 | { 0xa224, 0xcc000000 }, |
| 50 | { 0xa228, 0x07000040 }, |
| 51 | { 0xa22c, 0x0000fe00 }, |
| 52 | { 0xa230, 0x00000000 }, |
| 53 | { 0xa234, 0x17000000 }, |
| 54 | { 0xa238, 0x00000021 }, |
| 55 | { 0xa23c, 0x0817fe19 }, |
| 56 | { 0xa240, 0x00000000 }, |
| 57 | { 0xa244, 0x00000000 }, |
| 58 | { 0xa248, 0x8000421e }, |
| 59 | { 0 } |
| 60 | }; |
| 61 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 62 | static const struct gt_powermeter snb_pm_gt2[] = { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 63 | { 0xa200, 0x330000a6 }, |
| 64 | { 0xa204, 0x402d0031 }, |
| 65 | { 0xa208, 0x00165f83 }, |
| 66 | { 0xa20c, 0xf1000000 }, |
| 67 | { 0xa210, 0x00000000 }, |
| 68 | { 0xa214, 0x00160016 }, |
| 69 | { 0xa218, 0x002a002b }, |
| 70 | { 0xa21c, 0x00000000 }, |
| 71 | { 0xa220, 0x00000000 }, |
| 72 | { 0xa224, 0x330000a6 }, |
| 73 | { 0xa228, 0x402d0031 }, |
| 74 | { 0xa22c, 0x00165f83 }, |
| 75 | { 0xa230, 0xf1000000 }, |
| 76 | { 0xa234, 0x00000000 }, |
| 77 | { 0xa238, 0x00160016 }, |
| 78 | { 0xa23c, 0x002a002b }, |
| 79 | { 0xa240, 0x00000000 }, |
| 80 | { 0xa244, 0x00000000 }, |
| 81 | { 0xa248, 0x8000421e }, |
| 82 | { 0 } |
| 83 | }; |
| 84 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 85 | static const struct gt_powermeter ivb_pm_gt1[] = { |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 86 | { 0xa800, 0x00000000 }, |
| 87 | { 0xa804, 0x00021c00 }, |
| 88 | { 0xa808, 0x00000403 }, |
| 89 | { 0xa80c, 0x02001700 }, |
| 90 | { 0xa810, 0x05000200 }, |
| 91 | { 0xa814, 0x00000000 }, |
| 92 | { 0xa818, 0x00690500 }, |
| 93 | { 0xa81c, 0x0000007f }, |
| 94 | { 0xa820, 0x01002501 }, |
| 95 | { 0xa824, 0x00000300 }, |
| 96 | { 0xa828, 0x01000331 }, |
| 97 | { 0xa82c, 0x0000000c }, |
| 98 | { 0xa830, 0x00010016 }, |
| 99 | { 0xa834, 0x01100101 }, |
| 100 | { 0xa838, 0x00010103 }, |
| 101 | { 0xa83c, 0x00041300 }, |
| 102 | { 0xa840, 0x00000b30 }, |
| 103 | { 0xa844, 0x00000000 }, |
| 104 | { 0xa848, 0x7f000000 }, |
| 105 | { 0xa84c, 0x05000008 }, |
| 106 | { 0xa850, 0x00000001 }, |
| 107 | { 0xa854, 0x00000004 }, |
| 108 | { 0xa858, 0x00000007 }, |
| 109 | { 0xa85c, 0x00000000 }, |
| 110 | { 0xa860, 0x00010000 }, |
| 111 | { 0xa248, 0x0000221e }, |
| 112 | { 0xa900, 0x00000000 }, |
| 113 | { 0xa904, 0x00001c00 }, |
| 114 | { 0xa908, 0x00000000 }, |
| 115 | { 0xa90c, 0x06000000 }, |
| 116 | { 0xa910, 0x09000200 }, |
| 117 | { 0xa914, 0x00000000 }, |
| 118 | { 0xa918, 0x00590000 }, |
| 119 | { 0xa91c, 0x00000000 }, |
| 120 | { 0xa920, 0x04002501 }, |
| 121 | { 0xa924, 0x00000100 }, |
| 122 | { 0xa928, 0x03000410 }, |
| 123 | { 0xa92c, 0x00000000 }, |
| 124 | { 0xa930, 0x00020000 }, |
| 125 | { 0xa934, 0x02070106 }, |
| 126 | { 0xa938, 0x00010100 }, |
| 127 | { 0xa93c, 0x00401c00 }, |
| 128 | { 0xa940, 0x00000000 }, |
| 129 | { 0xa944, 0x00000000 }, |
| 130 | { 0xa948, 0x10000e00 }, |
| 131 | { 0xa94c, 0x02000004 }, |
| 132 | { 0xa950, 0x00000001 }, |
| 133 | { 0xa954, 0x00000004 }, |
| 134 | { 0xa960, 0x00060000 }, |
| 135 | { 0xaa3c, 0x00001c00 }, |
| 136 | { 0xaa54, 0x00000004 }, |
| 137 | { 0xaa60, 0x00060000 }, |
| 138 | { 0 } |
| 139 | }; |
| 140 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 141 | static const struct gt_powermeter ivb_pm_gt2_17w[] = { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 142 | { 0xa800, 0x20000000 }, |
| 143 | { 0xa804, 0x000e3800 }, |
| 144 | { 0xa808, 0x00000806 }, |
| 145 | { 0xa80c, 0x0c002f00 }, |
| 146 | { 0xa810, 0x0c000800 }, |
| 147 | { 0xa814, 0x00000000 }, |
| 148 | { 0xa818, 0x00d20d00 }, |
| 149 | { 0xa81c, 0x000000ff }, |
| 150 | { 0xa820, 0x03004b02 }, |
| 151 | { 0xa824, 0x00000600 }, |
| 152 | { 0xa828, 0x07000773 }, |
| 153 | { 0xa82c, 0x00000000 }, |
| 154 | { 0xa830, 0x00020032 }, |
| 155 | { 0xa834, 0x1520040d }, |
| 156 | { 0xa838, 0x00020105 }, |
| 157 | { 0xa83c, 0x00083700 }, |
| 158 | { 0xa840, 0x000016ff }, |
| 159 | { 0xa844, 0x00000000 }, |
| 160 | { 0xa848, 0xff000000 }, |
| 161 | { 0xa84c, 0x0a000010 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 162 | { 0xa850, 0x00000002 }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 163 | { 0xa854, 0x00000008 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 164 | { 0xa858, 0x0000000f }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 165 | { 0xa85c, 0x00000000 }, |
| 166 | { 0xa860, 0x00020000 }, |
| 167 | { 0xa248, 0x0000221e }, |
| 168 | { 0xa900, 0x00000000 }, |
| 169 | { 0xa904, 0x00003800 }, |
| 170 | { 0xa908, 0x00000000 }, |
| 171 | { 0xa90c, 0x0c000000 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 172 | { 0xa910, 0x12000800 }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 173 | { 0xa914, 0x00000000 }, |
| 174 | { 0xa918, 0x00b20000 }, |
| 175 | { 0xa91c, 0x00000000 }, |
| 176 | { 0xa920, 0x08004b02 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 177 | { 0xa924, 0x00000300 }, |
| 178 | { 0xa928, 0x01000820 }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 179 | { 0xa92c, 0x00000000 }, |
| 180 | { 0xa930, 0x00030000 }, |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 181 | { 0xa934, 0x15150406 }, |
| 182 | { 0xa938, 0x00020300 }, |
| 183 | { 0xa93c, 0x00903900 }, |
| 184 | { 0xa940, 0x00000000 }, |
| 185 | { 0xa944, 0x00000000 }, |
| 186 | { 0xa948, 0x20001b00 }, |
| 187 | { 0xa94c, 0x0a000010 }, |
| 188 | { 0xa950, 0x00000000 }, |
| 189 | { 0xa954, 0x00000008 }, |
| 190 | { 0xa960, 0x00110000 }, |
| 191 | { 0xaa3c, 0x00003900 }, |
| 192 | { 0xaa54, 0x00000008 }, |
| 193 | { 0xaa60, 0x00110000 }, |
| 194 | { 0 } |
| 195 | }; |
| 196 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 197 | static const struct gt_powermeter ivb_pm_gt2_35w[] = { |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 198 | { 0xa800, 0x00000000 }, |
| 199 | { 0xa804, 0x00030400 }, |
| 200 | { 0xa808, 0x00000806 }, |
| 201 | { 0xa80c, 0x0c002f00 }, |
| 202 | { 0xa810, 0x0c000300 }, |
| 203 | { 0xa814, 0x00000000 }, |
| 204 | { 0xa818, 0x00d20d00 }, |
| 205 | { 0xa81c, 0x000000ff }, |
| 206 | { 0xa820, 0x03004b02 }, |
| 207 | { 0xa824, 0x00000600 }, |
| 208 | { 0xa828, 0x07000773 }, |
| 209 | { 0xa82c, 0x00000000 }, |
| 210 | { 0xa830, 0x00020032 }, |
| 211 | { 0xa834, 0x1520040d }, |
| 212 | { 0xa838, 0x00020105 }, |
| 213 | { 0xa83c, 0x00083700 }, |
| 214 | { 0xa840, 0x000016ff }, |
| 215 | { 0xa844, 0x00000000 }, |
| 216 | { 0xa848, 0xff000000 }, |
| 217 | { 0xa84c, 0x0a000010 }, |
| 218 | { 0xa850, 0x00000001 }, |
| 219 | { 0xa854, 0x00000008 }, |
| 220 | { 0xa858, 0x00000008 }, |
| 221 | { 0xa85c, 0x00000000 }, |
| 222 | { 0xa860, 0x00020000 }, |
| 223 | { 0xa248, 0x0000221e }, |
| 224 | { 0xa900, 0x00000000 }, |
| 225 | { 0xa904, 0x00003800 }, |
| 226 | { 0xa908, 0x00000000 }, |
| 227 | { 0xa90c, 0x0c000000 }, |
| 228 | { 0xa910, 0x12000800 }, |
| 229 | { 0xa914, 0x00000000 }, |
| 230 | { 0xa918, 0x00b20000 }, |
| 231 | { 0xa91c, 0x00000000 }, |
| 232 | { 0xa920, 0x08004b02 }, |
| 233 | { 0xa924, 0x00000300 }, |
| 234 | { 0xa928, 0x01000820 }, |
| 235 | { 0xa92c, 0x00000000 }, |
| 236 | { 0xa930, 0x00030000 }, |
| 237 | { 0xa934, 0x15150406 }, |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 238 | { 0xa938, 0x00020300 }, |
| 239 | { 0xa93c, 0x00903900 }, |
| 240 | { 0xa940, 0x00000000 }, |
| 241 | { 0xa944, 0x00000000 }, |
| 242 | { 0xa948, 0x20001b00 }, |
| 243 | { 0xa94c, 0x0a000010 }, |
| 244 | { 0xa950, 0x00000000 }, |
| 245 | { 0xa954, 0x00000008 }, |
| 246 | { 0xa960, 0x00110000 }, |
| 247 | { 0xaa3c, 0x00003900 }, |
| 248 | { 0xaa54, 0x00000008 }, |
| 249 | { 0xaa60, 0x00110000 }, |
| 250 | { 0 } |
| 251 | }; |
| 252 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 253 | /* some vga option roms are used for several chipsets but they only have one |
| 254 | * PCI ID in their header. If we encounter such an option rom, we need to do |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 255 | * the mapping ourselves |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 256 | */ |
| 257 | |
| 258 | u32 map_oprom_vendev(u32 vendev) |
| 259 | { |
Nico Huber | 23b93dd | 2017-07-29 01:46:23 +0200 | [diff] [blame] | 260 | u32 new_vendev = vendev; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 261 | |
| 262 | switch (vendev) { |
Nico Huber | 23b93dd | 2017-07-29 01:46:23 +0200 | [diff] [blame] | 263 | case 0x80860102: /* SNB GT1 Desktop */ |
| 264 | case 0x8086010a: /* SNB GT1 Server */ |
| 265 | case 0x80860112: /* SNB GT2 Desktop */ |
| 266 | case 0x80860116: /* SNB GT2 Mobile */ |
| 267 | case 0x80860122: /* SNB GT2 Desktop >=1.3GHz */ |
| 268 | case 0x80860126: /* SNB GT2 Mobile >=1.3GHz */ |
| 269 | case 0x80860152: /* IVB GT1 Desktop */ |
| 270 | case 0x80860156: /* IVB GT1 Mobile */ |
| 271 | case 0x80860162: /* IVB GT2 Desktop */ |
| 272 | case 0x80860166: /* IVB GT2 Mobile */ |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 273 | case 0x8086016a: /* IVB GT2 Server */ |
Nico Huber | 23b93dd | 2017-07-29 01:46:23 +0200 | [diff] [blame] | 274 | new_vendev = 0x80860106;/* SNB GT1 Mobile */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 275 | break; |
| 276 | } |
| 277 | |
| 278 | return new_vendev; |
| 279 | } |
| 280 | |
| 281 | static struct resource *gtt_res = NULL; |
| 282 | |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 283 | u32 gtt_read(u32 reg) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 284 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 285 | return read32(res2mmio(gtt_res, reg, 0)); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 286 | } |
| 287 | |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 288 | void gtt_write(u32 reg, u32 data) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 289 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 290 | write32(res2mmio(gtt_res, reg, 0), data); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 291 | } |
| 292 | |
Stefan Reinauer | 4c8027a | 2012-09-07 10:53:56 -0700 | [diff] [blame] | 293 | static inline void gtt_write_powermeter(const struct gt_powermeter *pm) |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 294 | { |
| 295 | for (; pm && pm->reg; pm++) |
| 296 | gtt_write(pm->reg, pm->value); |
| 297 | } |
| 298 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 299 | #define GTT_RETRY 1000 |
Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 300 | int gtt_poll(u32 reg, u32 mask, u32 value) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 301 | { |
| 302 | unsigned try = GTT_RETRY; |
| 303 | u32 data; |
| 304 | |
| 305 | while (try--) { |
| 306 | data = gtt_read(reg); |
| 307 | if ((data & mask) == value) |
| 308 | return 1; |
| 309 | udelay(10); |
| 310 | } |
| 311 | |
| 312 | printk(BIOS_ERR, "GT init timeout\n"); |
| 313 | return 0; |
| 314 | } |
| 315 | |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 316 | uintptr_t gma_get_gnvs_aslb(const void *gnvs) |
| 317 | { |
| 318 | const global_nvs_t *gnvs_ptr = gnvs; |
| 319 | return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0); |
| 320 | } |
| 321 | |
| 322 | void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) |
| 323 | { |
| 324 | global_nvs_t *gnvs_ptr = gnvs; |
| 325 | if (gnvs_ptr) |
| 326 | gnvs_ptr->aslb = aslb; |
| 327 | } |
| 328 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 329 | static void gma_pm_init_pre_vbios(struct device *dev) |
| 330 | { |
| 331 | u32 reg32; |
| 332 | |
| 333 | printk(BIOS_DEBUG, "GT Power Management Init\n"); |
| 334 | |
| 335 | gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 336 | if (!gtt_res || !gtt_res->base) |
| 337 | return; |
| 338 | |
| 339 | if (bridge_silicon_revision() < IVB_STEP_C0) { |
| 340 | /* 1: Enable force wake */ |
| 341 | gtt_write(0xa18c, 0x00000001); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 342 | gtt_poll(0x130090, (1 << 0), (1 << 0)); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 343 | } else { |
| 344 | gtt_write(0xa180, 1 << 5); |
| 345 | gtt_write(0xa188, 0xffff0001); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 346 | gtt_poll(0x130040, (1 << 0), (1 << 0)); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 347 | } |
| 348 | |
| 349 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 350 | /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ |
| 351 | reg32 = gtt_read(0x42004); |
| 352 | reg32 |= (1 << 14) | (1 << 15); |
| 353 | gtt_write(0x42004, reg32); |
| 354 | } |
| 355 | |
| 356 | if (bridge_silicon_revision() >= IVB_STEP_A0) { |
| 357 | /* Display Reset Acknowledge Settings */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 358 | reg32 = gtt_read(0x45010); |
| 359 | reg32 |= (1 << 1) | (1 << 0); |
| 360 | gtt_write(0x45010, reg32); |
| 361 | } |
| 362 | |
| 363 | /* 2: Get GT SKU from GTT+0x911c[13] */ |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 364 | reg32 = gtt_read(0x911c); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 365 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 366 | if (reg32 & (1 << 13)) { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 367 | printk(BIOS_DEBUG, "SNB GT1 Power Meter Weights\n"); |
| 368 | gtt_write_powermeter(snb_pm_gt1); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 369 | } else { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 370 | printk(BIOS_DEBUG, "SNB GT2 Power Meter Weights\n"); |
| 371 | gtt_write_powermeter(snb_pm_gt2); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 372 | } |
| 373 | } else { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 374 | u32 unit = MCHBAR32(0x5938) & 0xf; |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 375 | |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 376 | if (reg32 & (1 << 13)) { |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 377 | /* GT1 SKU */ |
| 378 | printk(BIOS_DEBUG, "IVB GT1 Power Meter Weights\n"); |
| 379 | gtt_write_powermeter(ivb_pm_gt1); |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 380 | } else { |
| 381 | /* GT2 SKU */ |
| 382 | u32 tdp = MCHBAR32(0x5930) & 0x7fff; |
| 383 | tdp /= (1 << unit); |
| 384 | |
| 385 | if (tdp <= 17) { |
| 386 | /* <=17W ULV */ |
| 387 | printk(BIOS_DEBUG, "IVB GT2 17W " |
| 388 | "Power Meter Weights\n"); |
| 389 | gtt_write_powermeter(ivb_pm_gt2_17w); |
| 390 | } else if ((tdp >= 25) && (tdp <= 35)) { |
| 391 | /* 25W-35W */ |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 392 | printk(BIOS_DEBUG, "IVB GT2 25W-35W " |
Duncan Laurie | 8508cff | 2012-04-12 16:02:43 -0700 | [diff] [blame] | 393 | "Power Meter Weights\n"); |
| 394 | gtt_write_powermeter(ivb_pm_gt2_35w); |
| 395 | } else { |
| 396 | /* All others */ |
| 397 | printk(BIOS_DEBUG, "IVB GT2 35W " |
| 398 | "Power Meter Weights\n"); |
| 399 | gtt_write_powermeter(ivb_pm_gt2_35w); |
| 400 | } |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 401 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 402 | } |
| 403 | |
| 404 | /* 3: Gear ratio map */ |
| 405 | gtt_write(0xa004, 0x00000010); |
| 406 | |
| 407 | /* 4: GFXPAUSE */ |
| 408 | gtt_write(0xa000, 0x00070020); |
| 409 | |
| 410 | /* 5: Dynamic EU trip control */ |
| 411 | gtt_write(0xa080, 0x00000004); |
| 412 | |
| 413 | /* 6: ECO bits */ |
| 414 | reg32 = gtt_read(0xa180); |
| 415 | reg32 |= (1 << 26) | (1 << 31); |
| 416 | /* (bit 20=1 for SNB step D1+ / IVB A0+) */ |
| 417 | if (bridge_silicon_revision() >= SNB_STEP_D1) |
| 418 | reg32 |= (1 << 20); |
| 419 | gtt_write(0xa180, reg32); |
| 420 | |
| 421 | /* 6a: for SnB step D2+ only */ |
| 422 | if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && |
| 423 | (bridge_silicon_revision() >= SNB_STEP_D2)) { |
| 424 | reg32 = gtt_read(0x9400); |
| 425 | reg32 |= (1 << 7); |
| 426 | gtt_write(0x9400, reg32); |
| 427 | |
| 428 | reg32 = gtt_read(0x941c); |
| 429 | reg32 &= 0xf; |
| 430 | reg32 |= (1 << 1); |
| 431 | gtt_write(0x941c, reg32); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 432 | gtt_poll(0x941c, (1 << 1), (0 << 1)); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 436 | reg32 = gtt_read(0x907c); |
| 437 | reg32 |= (1 << 16); |
| 438 | gtt_write(0x907c, reg32); |
| 439 | |
| 440 | /* 6b: Clocking reset controls */ |
| 441 | gtt_write(0x9424, 0x00000001); |
| 442 | } else { |
| 443 | /* 6b: Clocking reset controls */ |
| 444 | gtt_write(0x9424, 0x00000000); |
| 445 | } |
| 446 | |
| 447 | /* 7 */ |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 448 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) { |
| 449 | gtt_write(0x138128, 0x00000029); /* Mailbox Data */ |
| 450 | gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */ |
| 451 | if (gtt_poll(0x138124, (1 << 31), (0 << 31))) |
| 452 | gtt_write(0x138124, 0x8000000a); |
| 453 | gtt_poll(0x138124, (1 << 31), (0 << 31)); |
| 454 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 455 | |
| 456 | /* 8 */ |
| 457 | gtt_write(0xa090, 0x00000000); /* RC Control */ |
| 458 | gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ |
| 459 | gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ |
| 460 | gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ |
| 461 | gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */ |
| 462 | gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */ |
| 463 | |
| 464 | /* 9 */ |
| 465 | gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */ |
| 466 | gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */ |
| 467 | gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */ |
| 468 | |
| 469 | /* 10 */ |
| 470 | gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */ |
| 471 | gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */ |
| 472 | gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */ |
| 473 | gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */ |
| 474 | gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */ |
| 475 | |
| 476 | /* 11 */ |
| 477 | gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */ |
| 478 | gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */ |
| 479 | gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */ |
| 480 | gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */ |
| 481 | gtt_write(0xa068, 0x000186a0); /* RP Up EI */ |
| 482 | gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ |
| 483 | gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */ |
| 484 | |
| 485 | /* 11a: Enable Render Standby (RC6) */ |
| 486 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 487 | /* |
| 488 | * IvyBridge should also support DeepRenderStandby. |
| 489 | * |
| 490 | * Unfortunately it does not work reliably on all SKUs so |
| 491 | * disable it here and it can be enabled by the kernel. |
| 492 | */ |
| 493 | gtt_write(0xa090, 0x88040000); /* HW RC Control */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 494 | } else { |
| 495 | gtt_write(0xa090, 0x88040000); /* HW RC Control */ |
| 496 | } |
| 497 | |
| 498 | /* 12: Normal Frequency Request */ |
Felix Held | 6b6c94b | 2017-11-25 00:45:23 +0100 | [diff] [blame] | 499 | /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ |
| 500 | /* only the lower 7 bits are used and shifted left by 25 */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 501 | reg32 = MCHBAR32(0x5998); |
| 502 | reg32 >>= 16; |
Felix Held | 6b6c94b | 2017-11-25 00:45:23 +0100 | [diff] [blame] | 503 | reg32 &= 0x7f; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 504 | reg32 <<= 25; |
| 505 | gtt_write(0xa008, reg32); |
| 506 | |
| 507 | /* 13: RP Control */ |
| 508 | gtt_write(0xa024, 0x00000592); |
| 509 | |
| 510 | /* 14: Enable PM Interrupts */ |
| 511 | gtt_write(0x4402c, 0x03000076); |
| 512 | |
| 513 | /* Clear 0x6c024 [8:6] */ |
| 514 | reg32 = gtt_read(0x6c024); |
| 515 | reg32 &= ~0x000001c0; |
| 516 | gtt_write(0x6c024, reg32); |
Nico Huber | 07e206a | 2016-10-19 15:20:17 +0200 | [diff] [blame] | 517 | |
| 518 | /* Initialize DP buffer translation with recommended defaults */ |
| 519 | gtt_write(0xe4f00, 0x0100030c); |
| 520 | gtt_write(0xe4f04, 0x00b8230c); |
| 521 | gtt_write(0xe4f08, 0x06f8930c); |
| 522 | gtt_write(0xe4f0c, 0x05f8e38e); |
| 523 | gtt_write(0xe4f10, 0x00b8030c); |
| 524 | gtt_write(0xe4f14, 0x0b78830c); |
| 525 | gtt_write(0xe4f18, 0x09f8d3cf); |
| 526 | gtt_write(0xe4f1c, 0x01e8030c); |
| 527 | gtt_write(0xe4f20, 0x09f863cf); |
| 528 | gtt_write(0xe4f24, 0x0ff803cf); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 529 | } |
| 530 | |
| 531 | static void gma_pm_init_post_vbios(struct device *dev) |
| 532 | { |
| 533 | struct northbridge_intel_sandybridge_config *conf = dev->chip_info; |
| 534 | u32 reg32; |
| 535 | |
| 536 | printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); |
| 537 | |
| 538 | /* 15: Deassert Force Wake */ |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 539 | if (bridge_silicon_revision() < IVB_STEP_C0) { |
| 540 | gtt_write(0xa18c, gtt_read(0xa18c) & ~1); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 541 | gtt_poll(0x130090, (1 << 0), (0 << 0)); |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 542 | } else { |
| 543 | gtt_write(0xa188, 0x1fffe); |
Duncan Laurie | da83a5f | 2012-05-25 10:04:17 -0700 | [diff] [blame] | 544 | if (gtt_poll(0x130040, (1 << 0), (0 << 0))) |
| 545 | gtt_write(0xa188, gtt_read(0xa188) | 1); |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 546 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 547 | |
| 548 | /* 16: SW RC Control */ |
| 549 | gtt_write(0xa094, 0x00060000); |
| 550 | |
| 551 | /* Setup Digital Port Hotplug */ |
| 552 | reg32 = gtt_read(0xc4030); |
| 553 | if (!reg32) { |
| 554 | reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2; |
| 555 | reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10; |
| 556 | reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18; |
| 557 | gtt_write(0xc4030, reg32); |
| 558 | } |
| 559 | |
| 560 | /* Setup Panel Power On Delays */ |
| 561 | reg32 = gtt_read(0xc7208); |
| 562 | if (!reg32) { |
| 563 | reg32 = (conf->gpu_panel_port_select & 0x3) << 30; |
| 564 | reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; |
| 565 | reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); |
| 566 | gtt_write(0xc7208, reg32); |
| 567 | } |
| 568 | |
| 569 | /* Setup Panel Power Off Delays */ |
| 570 | reg32 = gtt_read(0xc720c); |
| 571 | if (!reg32) { |
| 572 | reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; |
| 573 | reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); |
| 574 | gtt_write(0xc720c, reg32); |
| 575 | } |
| 576 | |
| 577 | /* Setup Panel Power Cycle Delay */ |
| 578 | if (conf->gpu_panel_power_cycle_delay) { |
| 579 | reg32 = gtt_read(0xc7210); |
| 580 | reg32 &= ~0xff; |
| 581 | reg32 |= conf->gpu_panel_power_cycle_delay & 0xff; |
| 582 | gtt_write(0xc7210, reg32); |
| 583 | } |
Duncan Laurie | dd585b8 | 2012-04-09 12:05:18 -0700 | [diff] [blame] | 584 | |
| 585 | /* Enable Backlight if needed */ |
| 586 | if (conf->gpu_cpu_backlight) { |
| 587 | gtt_write(0x48250, (1 << 31)); |
| 588 | gtt_write(0x48254, conf->gpu_cpu_backlight); |
| 589 | } |
| 590 | if (conf->gpu_pch_backlight) { |
| 591 | gtt_write(0xc8250, (1 << 31)); |
| 592 | gtt_write(0xc8254, conf->gpu_pch_backlight); |
| 593 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 594 | } |
| 595 | |
Patrick Rudolph | 76b93fe | 2017-06-20 17:55:40 +0200 | [diff] [blame] | 596 | /* Enable SCI to ACPI _GPE._L06 */ |
| 597 | static void gma_enable_swsci(void) |
| 598 | { |
| 599 | u16 reg16; |
| 600 | |
| 601 | /* clear DMISCI status */ |
| 602 | reg16 = inw(DEFAULT_PMBASE + TCO1_STS); |
| 603 | reg16 &= DMISCI_STS; |
| 604 | outw(DEFAULT_PMBASE + TCO1_STS, reg16); |
| 605 | |
| 606 | /* clear acpi tco status */ |
| 607 | outl(DEFAULT_PMBASE + GPE0_STS, TCOSCI_STS); |
| 608 | |
| 609 | /* enable acpi tco scis */ |
| 610 | reg16 = inw(DEFAULT_PMBASE + GPE0_EN); |
| 611 | reg16 |= TCOSCI_EN; |
| 612 | outw(DEFAULT_PMBASE + GPE0_EN, reg16); |
| 613 | } |
| 614 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 615 | static void gma_func0_init(struct device *dev) |
| 616 | { |
| 617 | u32 reg32; |
| 618 | |
| 619 | /* IGD needs to be Bus Master */ |
| 620 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 621 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
| 622 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 623 | |
| 624 | /* Init graphics power management */ |
| 625 | gma_pm_init_pre_vbios(dev); |
| 626 | |
Alexandru Gagniuc | 9647094 | 2015-09-07 03:06:31 -0700 | [diff] [blame] | 627 | if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) |
| 628 | /* PCI Init, will run VBIOS */ |
| 629 | pci_dev_init(dev); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 630 | |
| 631 | /* Post VBIOS init */ |
| 632 | gma_pm_init_post_vbios(dev); |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 633 | |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 634 | int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; |
| 635 | |
Patrick Rudolph | de4a1a0 | 2017-06-20 19:13:33 +0200 | [diff] [blame] | 636 | /* Running graphics init on S3 breaks Linux drm driver. */ |
| 637 | if (!acpi_is_wakeup_s3() && |
| 638 | (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) || |
| 639 | IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT))) { |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 640 | if (vga_disable) { |
| 641 | printk(BIOS_INFO, |
| 642 | "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n"); |
Nico Huber | 88c6487 | 2016-10-05 18:02:01 +0200 | [diff] [blame] | 643 | } else { |
Arthur Heymans | e6c8f7e | 2018-08-09 11:31:51 +0200 | [diff] [blame] | 644 | /* This should probably run before post VBIOS init. */ |
| 645 | printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); |
| 646 | u8 *mmiobase; |
| 647 | u32 iobase, physbase, graphics_base; |
| 648 | struct northbridge_intel_sandybridge_config *conf = dev->chip_info; |
| 649 | iobase = dev->resource_list[2].base; |
| 650 | mmiobase = res2mmio(&dev->resource_list[0], 0, 0); |
| 651 | physbase = pci_read_config32(dev, 0x5c) & ~0xf; |
| 652 | graphics_base = dev->resource_list[1].base; |
| 653 | |
| 654 | int lightup_ok; |
| 655 | if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { |
| 656 | gma_gfxinit(&lightup_ok); |
| 657 | } else { |
| 658 | lightup_ok = i915lightup_sandy(&conf->gfx, |
| 659 | physbase, |
| 660 | iobase, mmiobase, |
| 661 | graphics_base); |
| 662 | } |
| 663 | if (lightup_ok) |
| 664 | gfx_set_init_done(1); |
Nico Huber | 88c6487 | 2016-10-05 18:02:01 +0200 | [diff] [blame] | 665 | } |
Alexandru Gagniuc | 9647094 | 2015-09-07 03:06:31 -0700 | [diff] [blame] | 666 | } |
Patrick Rudolph | 76b93fe | 2017-06-20 17:55:40 +0200 | [diff] [blame] | 667 | |
| 668 | gma_enable_swsci(); |
| 669 | intel_gma_restore_opregion(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 670 | } |
| 671 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 672 | static void gma_set_subsystem(struct device *dev, unsigned vendor, unsigned device) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 673 | { |
| 674 | if (!vendor || !device) { |
| 675 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 676 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 677 | } else { |
| 678 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 679 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 680 | } |
| 681 | } |
| 682 | |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 683 | const struct i915_gpu_controller_info * |
| 684 | intel_gma_get_controller_info(void) |
| 685 | { |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 686 | struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 687 | if (!dev) { |
| 688 | return NULL; |
| 689 | } |
| 690 | struct northbridge_intel_sandybridge_config *chip = dev->chip_info; |
| 691 | return &chip->gfx; |
| 692 | } |
| 693 | |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 694 | static void gma_ssdt(struct device *device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 695 | { |
| 696 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 697 | if (!gfx) { |
| 698 | return; |
| 699 | } |
| 700 | |
| 701 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 702 | } |
| 703 | |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 704 | static unsigned long |
| 705 | gma_write_acpi_tables(struct device *const dev, |
| 706 | unsigned long current, |
| 707 | struct acpi_rsdp *const rsdp) |
| 708 | { |
Patrick Rudolph | 402e9c1 | 2017-05-18 18:26:30 +0200 | [diff] [blame] | 709 | igd_opregion_t *opregion = (igd_opregion_t *)current; |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 710 | global_nvs_t *gnvs; |
| 711 | |
Matt DeVillier | ebe08e0 | 2017-07-14 13:28:42 -0500 | [diff] [blame] | 712 | if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS) |
Patrick Rudolph | 402e9c1 | 2017-05-18 18:26:30 +0200 | [diff] [blame] | 713 | return current; |
| 714 | |
| 715 | current += sizeof(igd_opregion_t); |
| 716 | |
| 717 | /* GNVS has been already set up */ |
| 718 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 719 | if (gnvs) { |
| 720 | /* IGD OpRegion Base Address */ |
Patrick Rudolph | 19c2ad8 | 2017-06-30 14:52:01 +0200 | [diff] [blame] | 721 | gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion); |
Patrick Rudolph | 402e9c1 | 2017-05-18 18:26:30 +0200 | [diff] [blame] | 722 | } else { |
| 723 | printk(BIOS_ERR, "Error: GNVS table not found.\n"); |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 724 | } |
| 725 | |
Patrick Rudolph | 402e9c1 | 2017-05-18 18:26:30 +0200 | [diff] [blame] | 726 | current = acpi_align_current(current); |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 727 | return current; |
| 728 | } |
| 729 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 730 | static const char *gma_acpi_name(const struct device *dev) |
Patrick Rudolph | 3e47fc9 | 2017-06-07 09:44:07 +0200 | [diff] [blame] | 731 | { |
| 732 | return "GFX0"; |
| 733 | } |
| 734 | |
Patrick Rudolph | e11f6c3 | 2015-10-15 15:35:12 +0200 | [diff] [blame] | 735 | /* called by pci set_vga_bridge function */ |
| 736 | static void gma_func0_disable(struct device *dev) |
| 737 | { |
| 738 | u16 reg16; |
Elyes HAOUAS | ab8743c | 2018-02-09 08:21:40 +0100 | [diff] [blame] | 739 | struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0,0)); |
Patrick Rudolph | e11f6c3 | 2015-10-15 15:35:12 +0200 | [diff] [blame] | 740 | |
| 741 | reg16 = pci_read_config16(dev_host, GGC); |
| 742 | reg16 |= (1 << 1); /* disable VGA decode */ |
| 743 | pci_write_config16(dev_host, GGC, reg16); |
| 744 | |
| 745 | dev->enabled = 0; |
| 746 | } |
| 747 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 748 | static struct pci_operations gma_pci_ops = { |
| 749 | .set_subsystem = gma_set_subsystem, |
| 750 | }; |
| 751 | |
| 752 | static struct device_operations gma_func0_ops = { |
Vladimir Serbinenko | 30fe612 | 2014-02-05 23:25:28 +0100 | [diff] [blame] | 753 | .read_resources = pci_dev_read_resources, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 754 | .set_resources = pci_dev_set_resources, |
| 755 | .enable_resources = pci_dev_enable_resources, |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 756 | .acpi_fill_ssdt_generator = gma_ssdt, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 757 | .init = gma_func0_init, |
| 758 | .scan_bus = 0, |
| 759 | .enable = 0, |
Patrick Rudolph | e11f6c3 | 2015-10-15 15:35:12 +0200 | [diff] [blame] | 760 | .disable = gma_func0_disable, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 761 | .ops_pci = &gma_pci_ops, |
Patrick Rudolph | 3e47fc9 | 2017-06-07 09:44:07 +0200 | [diff] [blame] | 762 | .acpi_name = gma_acpi_name, |
Patrick Rudolph | 281ccca | 2017-04-12 16:55:32 +0200 | [diff] [blame] | 763 | .write_acpi_tables = gma_write_acpi_tables, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 764 | }; |
| 765 | |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 766 | static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, |
| 767 | 0x0116, 0x0122, 0x0126, 0x0156, |
Vagiz Trakhanov | 1dd448c | 2017-09-28 14:42:11 +0000 | [diff] [blame] | 768 | 0x0166, 0x0162, 0x016a, 0x0152, |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 769 | 0 }; |
| 770 | |
| 771 | static const struct pci_driver gma __pci_driver = { |
| 772 | .ops = &gma_func0_ops, |
| 773 | .vendor = PCI_VENDOR_ID_INTEL, |
| 774 | .devices = pci_device_ids, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 775 | }; |