Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 1 | #include <console/console.h> |
| 2 | #include <arch/io.h> |
| 3 | #include <stdint.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <stdlib.h> |
| 8 | #include <string.h> |
| 9 | #include <bitops.h> |
Corey Osgood | e562f72 | 2008-12-19 03:36:48 +0000 | [diff] [blame] | 10 | #include <cpu/cpu.h> |
| 11 | #include <pc80/keyboard.h> |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 12 | #include "chip.h" |
| 13 | #include "northbridge.h" |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 14 | #include "i440bx.h" |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 15 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 16 | static void northbridge_init(device_t dev) |
| 17 | { |
| 18 | printk_spew("Northbridge Init\n"); |
| 19 | } |
| 20 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 21 | static struct device_operations northbridge_operations = { |
| 22 | .read_resources = pci_dev_read_resources, |
| 23 | .set_resources = pci_dev_set_resources, |
| 24 | .enable_resources = pci_dev_enable_resources, |
| 25 | .init = northbridge_init, |
| 26 | .enable = 0, |
| 27 | .ops_pci = 0, |
| 28 | }; |
| 29 | |
Stefan Reinauer | f1cf1f7 | 2007-10-24 09:08:58 +0000 | [diff] [blame] | 30 | static const struct pci_driver northbridge_driver __pci_driver = { |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 31 | .ops = &northbridge_operations, |
| 32 | .vendor = PCI_VENDOR_ID_INTEL, |
| 33 | .device = 0x7190, |
| 34 | }; |
| 35 | |
| 36 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 37 | #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) |
| 38 | |
| 39 | static void pci_domain_read_resources(device_t dev) |
| 40 | { |
| 41 | struct resource *resource; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 42 | unsigned reg; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 43 | |
| 44 | /* Initialize the system wide io space constraints */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 45 | resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 46 | resource->limit = 0xffffUL; |
| 47 | resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; |
| 48 | |
| 49 | /* Initialize the system wide memory resources constraints */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 50 | resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 51 | resource->limit = 0xffffffffULL; |
| 52 | resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; |
| 53 | } |
| 54 | |
| 55 | static void ram_resource(device_t dev, unsigned long index, |
| 56 | unsigned long basek, unsigned long sizek) |
| 57 | { |
| 58 | struct resource *resource; |
| 59 | |
| 60 | if (!sizek) { |
| 61 | return; |
| 62 | } |
| 63 | resource = new_resource(dev, index); |
| 64 | resource->base = ((resource_t)basek) << 10; |
| 65 | resource->size = ((resource_t)sizek) << 10; |
| 66 | resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ |
| 67 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 68 | } |
| 69 | |
| 70 | static void tolm_test(void *gp, struct device *dev, struct resource *new) |
| 71 | { |
| 72 | struct resource **best_p = gp; |
| 73 | struct resource *best; |
| 74 | best = *best_p; |
| 75 | if (!best || (best->base > new->base)) { |
| 76 | best = new; |
| 77 | } |
| 78 | *best_p = best; |
| 79 | } |
| 80 | |
| 81 | static uint32_t find_pci_tolm(struct bus *bus) |
| 82 | { |
| 83 | struct resource *min; |
| 84 | uint32_t tolm; |
| 85 | min = 0; |
| 86 | search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); |
| 87 | tolm = 0xffffffffUL; |
| 88 | if (min && tolm > min->base) { |
| 89 | tolm = min->base; |
| 90 | } |
| 91 | return tolm; |
| 92 | } |
| 93 | |
| 94 | static void pci_domain_set_resources(device_t dev) |
| 95 | { |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 96 | device_t mc_dev; |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 97 | uint32_t pci_tolm; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 98 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 99 | pci_tolm = find_pci_tolm(&dev->link[0]); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 100 | mc_dev = dev->link[0].children; |
Uwe Hermann | f03e4e9 | 2007-05-10 23:59:20 +0000 | [diff] [blame] | 101 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 102 | if (mc_dev) { |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 103 | uint16_t tolm_r; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 104 | unsigned long tomk, tolmk; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 105 | int idx; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 106 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 107 | /* Figure out which areas are/should be occupied by RAM. The |
| 108 | * value of the highest DRB denotes the end of the physical |
| 109 | * memory (in units of 8MB). |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 110 | */ |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 111 | tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7)); |
Uwe Hermann | f03e4e9 | 2007-05-10 23:59:20 +0000 | [diff] [blame] | 112 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 113 | /* Convert to KB. */ |
| 114 | tomk *= (8 * 1024); |
| 115 | |
| 116 | printk_debug("Setting RAM size to %d MB\n", tomk / 1024); |
| 117 | |
| 118 | /* Compute the top of low memory. */ |
| 119 | tolmk = pci_tolm / 1024; |
| 120 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 121 | if (tolmk >= tomk) { |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 122 | /* The PCI hole does does not overlap the memory. */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 123 | tolmk = tomk; |
| 124 | } |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 125 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 126 | /* Report the memory regions. */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 127 | idx = 10; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 128 | ram_resource(dev, idx++, 0, 640); |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 129 | ram_resource(dev, idx++, 768, tolmk - 768); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 130 | } |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 131 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 132 | assign_resources(&dev->link[0]); |
| 133 | } |
| 134 | |
| 135 | static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) |
| 136 | { |
| 137 | max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); |
| 138 | return max; |
| 139 | } |
| 140 | |
| 141 | static struct device_operations pci_domain_ops = { |
| 142 | .read_resources = pci_domain_read_resources, |
| 143 | .set_resources = pci_domain_set_resources, |
| 144 | .enable_resources = enable_childrens_resources, |
| 145 | .init = 0, |
| 146 | .scan_bus = pci_domain_scan_bus, |
| 147 | }; |
| 148 | |
| 149 | static void cpu_bus_init(device_t dev) |
| 150 | { |
| 151 | initialize_cpus(&dev->link[0]); |
| 152 | } |
| 153 | |
| 154 | static void cpu_bus_noop(device_t dev) |
| 155 | { |
| 156 | } |
| 157 | |
| 158 | static struct device_operations cpu_bus_ops = { |
| 159 | .read_resources = cpu_bus_noop, |
| 160 | .set_resources = cpu_bus_noop, |
| 161 | .enable_resources = cpu_bus_noop, |
| 162 | .init = cpu_bus_init, |
| 163 | .scan_bus = 0, |
| 164 | }; |
| 165 | |
| 166 | static void enable_dev(struct device *dev) |
| 167 | { |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 168 | struct device_path path; |
| 169 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 170 | /* Set the operations if it is a special bus type */ |
| 171 | if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { |
| 172 | dev->ops = &pci_domain_ops; |
| 173 | pci_set_method(dev); |
| 174 | } |
| 175 | else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { |
| 176 | dev->ops = &cpu_bus_ops; |
| 177 | } |
| 178 | } |
| 179 | |
| 180 | struct chip_operations northbridge_intel_i440bx_ops = { |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 181 | CHIP_NAME("Intel 82443BX (440BX) Northbridge") |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 182 | .enable_dev = enable_dev, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 183 | }; |