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review.coreboot.org / coreboot / b4a54424df27a396efd0ccadb959550ceaa9038d / . / src / devices / pcix_device.c
blob: 8915e56a1b5e5764d7bed62788e1373138d5e51f [file] [log] [blame]
Yinghai Lu13f1c2a2005-07-08 02:49:49 +0000[diff] [blame]1/* (c) 2005 Linux Networx GPL see COPYING for details */
2
3#include <console/console.h>
4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_ids.h>
7#include <device/pcix.h>
8
9
10static void pcix_tune_dev(device_t dev)
11{
12 unsigned cap;
13 unsigned status, orig_cmd, cmd;
14 unsigned max_read, max_tran;
15
16 if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) {
17 return;
18 }
19 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
20 if (!cap) {
21 return;
22 }
23 printk_debug("%s PCI-X tuning\n", dev_path(dev));
24 status = pci_read_config32(dev, cap + PCI_X_STATUS);
25 orig_cmd = cmd = pci_read_config16(dev,cap + PCI_X_CMD);
26
27 max_read = (status & PCI_X_STATUS_MAX_READ) >> 21;
28 max_tran = (status & PCI_X_STATUS_MAX_SPLIT) >> 23;
29 if (max_read != ((cmd & PCI_X_CMD_MAX_READ) >> 2)) {
30 cmd &= ~PCI_X_CMD_MAX_READ;
31 cmd |= max_read << 2;
32 }
33 if (max_tran != ((cmd & PCI_X_CMD_MAX_SPLIT) >> 4)) {
34 cmd &= ~PCI_X_CMD_MAX_SPLIT;
35 cmd |= max_tran << 4;
36 }
37 /* Don't attempt to handle PCI-X errors */
38 cmd &= ~PCI_X_CMD_DPERR_E;
39 /* Enable Relaxed Ordering */
40 cmd |= PCI_X_CMD_ERO;
41 if (orig_cmd != cmd) {
42 pci_write_config16(dev, cap + PCI_X_CMD, cmd);
43 }
44}
45
46unsigned int pcix_scan_bus(struct bus *bus,
47 unsigned min_devfn, unsigned max_devfn, unsigned int max)
48{
49 device_t child;
50 max = pci_scan_bus(bus, min_devfn, max_devfn, max);
51 for(child = bus->children; child; child = child->sibling) {
52 if ( (child->path.u.pci.devfn < min_devfn) ||
53 (child->path.u.pci.devfn > max_devfn))
54 {
55 continue;
56 }
57 pcix_tune_dev(child);
58 }
59 return max;
60}
61
62const char *pcix_speed(unsigned sstatus)
63{
64 static const char conventional[] = "Conventional PCI";
65 static const char pcix_66mhz[] = "66MHz PCI-X";
66 static const char pcix_100mhz[] = "100MHz PCI-X";
67 static const char pcix_133mhz[] = "133MHz PCI-X";
68 static const char pcix_266mhz[] = "266MHz PCI-X";
69 static const char pcix_533mhz[] = "533MHZ PCI-X";
70 static const char unknown[] = "Unknown";
71
72 const char *result;
73 result = unknown;
74 switch(PCI_X_SSTATUS_MFREQ(sstatus)) {
75 case PCI_X_SSTATUS_CONVENTIONAL_PCI:
76 result = conventional;
77 break;
78 case PCI_X_SSTATUS_MODE1_66MHZ:
79 result = pcix_66mhz;
80 break;
81 case PCI_X_SSTATUS_MODE1_100MHZ:
82 result = pcix_100mhz;
83 break;
84
85 case PCI_X_SSTATUS_MODE1_133MHZ:
86 result = pcix_133mhz;
87 break;
88
89 case PCI_X_SSTATUS_MODE2_266MHZ_REF_66MHZ:
90 case PCI_X_SSTATUS_MODE2_266MHZ_REF_100MHZ:
91 case PCI_X_SSTATUS_MODE2_266MHZ_REF_133MHZ:
92 result = pcix_266mhz;
93 break;
94
95 case PCI_X_SSTATUS_MODE2_533MHZ_REF_66MHZ:
96 case PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ:
97 case PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ:
98 result = pcix_533mhz;
99 break;
100 }
101 return result;
102}
103
104unsigned int pcix_scan_bridge(device_t dev, unsigned int max)
105{
106 unsigned pos;
107 unsigned sstatus;
108
109 /* Find the PCI-X capability */
110 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
111 sstatus = pci_read_config16(dev, pos + PCI_X_SEC_STATUS);
112
113 if (PCI_X_SSTATUS_MFREQ(sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) {
114 max = do_pci_scan_bridge(dev, max, pci_scan_bus);
115 } else {
116 max = do_pci_scan_bridge(dev, max, pcix_scan_bus);
117 }
118
119 /* Print the PCI-X bus speed */
120 printk_debug("PCI: %02x: %s\n", dev->link[0].secondary, pcix_speed(sstatus));
121
122 return max;
123}
124
125
126/** Default device operations for PCI-X bridges */
127static struct pci_operations pcix_bus_ops_pci = {
128 .set_subsystem = 0,
129};
130
131struct device_operations default_pcix_ops_bus = {
132 .read_resources = pci_bus_read_resources,
133 .set_resources = pci_dev_set_resources,
134 .enable_resources = pci_bus_enable_resources,
135 .init = 0,
136 .scan_bus = pcix_scan_bridge,
137 .enable = 0,
138 .reset_bus = pci_bus_reset,
139 .ops_pci = &pcix_bus_ops_pci,
140};