Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <acpi/acpigen.h> |
| 4 | #include <acpi/acpi_device.h> |
| 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/pci_ids.h> |
| 8 | #include <device/pci_ops.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <intelblocks/pmc.h> |
| 11 | #include <intelblocks/pmc_ipc.h> |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 12 | #include <intelblocks/pcie_rp.h> |
| 13 | #include <soc/iomap.h> |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 14 | #include "chip.h" |
| 15 | |
| 16 | /* |
| 17 | * The "ExternalFacingPort" and "HotPlugSupportInD3" properties are defined at |
| 18 | * https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports |
| 19 | */ |
| 20 | #define PCIE_EXTERNAL_PORT_UUID "EFCC06CC-73AC-4BC3-BFF0-76143807C389" |
| 21 | #define PCIE_EXTERNAL_PORT_PROPERTY "ExternalFacingPort" |
| 22 | |
| 23 | #define PCIE_HOTPLUG_IN_D3_UUID "6211E2C0-58A3-4AF3-90E1-927A4E0C55A4" |
| 24 | #define PCIE_HOTPLUG_IN_D3_PROPERTY "HotPlugSupportInD3" |
| 25 | |
| 26 | /* |
| 27 | * This UUID and the resulting ACPI Device Property is defined by the |
| 28 | * Power Management for Storage Hardware Devices: |
| 29 | * |
| 30 | * https://docs.microsoft.com/en-us/windows-hardware/design/component-guidelines/power-management-for-storage-hardware-devices-intro |
| 31 | */ |
| 32 | #define PCIE_RTD3_STORAGE_UUID "5025030F-842F-4AB4-A561-99A5189762D0" |
| 33 | #define PCIE_RTD3_STORAGE_PROPERTY "StorageD3Enable" |
| 34 | |
| 35 | /* PCIe Root Port registers for link status and L23 control. */ |
| 36 | #define PCH_PCIE_CFG_LSTS 0x52 /* Link Status Register */ |
| 37 | #define PCH_PCIE_CFG_SPR 0xe0 /* Scratchpad */ |
| 38 | #define PCH_PCIE_CFG_RPPGEN 0xe2 /* Root Port Power Gating Enable */ |
| 39 | #define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ |
| 40 | |
| 41 | /* ACPI register names corresponding to PCIe root port registers. */ |
| 42 | #define ACPI_REG_PCI_LINK_ACTIVE "LASX" /* Link active status */ |
| 43 | #define ACPI_REG_PCI_L23_RDY_ENTRY "L23E" /* L23_Rdy Entry Request */ |
| 44 | #define ACPI_REG_PCI_L23_RDY_DETECT "L23R" /* L23_Rdy Detect Transition */ |
| 45 | #define ACPI_REG_PCI_L23_SAVE_STATE "NCB7" /* Scratch bit to save L23 state */ |
| 46 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 47 | /* ACPI path to the mutex that protects accesses to PMC ModPhy power gating registers */ |
| 48 | #define RTD3_MUTEX_PATH "\\_SB.PCI0.R3MX" |
| 49 | |
| 50 | enum modphy_pg_state { |
| 51 | PG_DISABLE = 0, |
| 52 | PG_ENABLE = 1, |
| 53 | }; |
| 54 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 55 | /* Called from _ON to get PCIe link back to active state. */ |
| 56 | static void pcie_rtd3_acpi_l23_exit(void) |
| 57 | { |
| 58 | /* Skip if port is not in L2/L3. */ |
| 59 | acpigen_write_if_lequal_namestr_int(ACPI_REG_PCI_L23_SAVE_STATE, 1); |
| 60 | |
| 61 | /* Initiate L2/L3 Ready To Detect transition. */ |
| 62 | acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_DETECT); |
| 63 | |
| 64 | /* Wait for transition to detect. */ |
| 65 | acpigen_write_delay_until_namestr_int(320, ACPI_REG_PCI_L23_RDY_DETECT, 0); |
| 66 | |
| 67 | acpigen_write_store_int_to_namestr(0, ACPI_REG_PCI_L23_SAVE_STATE); |
| 68 | |
| 69 | /* Once in detect, wait for link active. */ |
| 70 | acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_LINK_ACTIVE, 1); |
| 71 | |
| 72 | acpigen_pop_len(); /* If */ |
| 73 | } |
| 74 | |
| 75 | /* Called from _OFF to put PCIe link into L2/L3 state. */ |
| 76 | static void pcie_rtd3_acpi_l23_entry(void) |
| 77 | { |
| 78 | /* Initiate L2/L3 Entry request. */ |
| 79 | acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_ENTRY); |
| 80 | |
| 81 | /* Wait for L2/L3 Entry request to clear. */ |
| 82 | acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_L23_RDY_ENTRY, 0); |
| 83 | |
| 84 | acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); |
| 85 | } |
| 86 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 87 | /* Called from _ON/_OFF to disable/enable ModPHY power gating */ |
| 88 | static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp, enum modphy_pg_state state) |
| 89 | { |
| 90 | /* Enter the critical section */ |
| 91 | acpigen_emit_ext_op(ACQUIRE_OP); |
| 92 | acpigen_emit_namestring(RTD3_MUTEX_PATH); |
| 93 | acpigen_emit_word(ACPI_MUTEX_NO_TIMEOUT); |
| 94 | |
| 95 | acpigen_write_store_int_to_namestr(state, "EMPG"); |
| 96 | acpigen_write_delay_until_namestr_int(100, "AMPG", state); |
| 97 | |
| 98 | /* Exit the critical section */ |
| 99 | acpigen_emit_ext_op(RELEASE_OP); |
| 100 | acpigen_emit_namestring(RTD3_MUTEX_PATH); |
| 101 | } |
| 102 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 103 | static void |
| 104 | pcie_rtd3_acpi_method_on(unsigned int pcie_rp, |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 105 | const struct soc_intel_common_block_pcie_rtd3_config *config, |
| 106 | enum pcie_rp_type rp_type) |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 107 | { |
| 108 | acpigen_write_method_serialized("_ON", 0); |
| 109 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 110 | /* Disable modPHY power gating for PCH RPs. */ |
| 111 | if (rp_type == PCIE_RP_PCH) |
| 112 | pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); |
| 113 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 114 | /* Assert enable GPIO to turn on device power. */ |
| 115 | if (config->enable_gpio.pin_count) { |
| 116 | acpigen_enable_tx_gpio(&config->enable_gpio); |
| 117 | if (config->enable_delay_ms) |
| 118 | acpigen_write_sleep(config->enable_delay_ms); |
| 119 | } |
| 120 | |
| 121 | /* Enable SRCCLK for root port if pin is defined. */ |
| 122 | if (config->srcclk_pin >= 0) |
| 123 | pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); |
| 124 | |
| 125 | /* De-assert reset GPIO to bring device out of reset. */ |
| 126 | if (config->reset_gpio.pin_count) { |
| 127 | acpigen_disable_tx_gpio(&config->reset_gpio); |
| 128 | if (config->reset_delay_ms) |
| 129 | acpigen_write_sleep(config->reset_delay_ms); |
| 130 | } |
| 131 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 132 | /* Trigger L23 ready exit flow unless disabled by config. */ |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 133 | if (!config->disable_l23) |
| 134 | pcie_rtd3_acpi_l23_exit(); |
| 135 | |
| 136 | acpigen_pop_len(); /* Method */ |
| 137 | } |
| 138 | |
| 139 | static void |
| 140 | pcie_rtd3_acpi_method_off(int pcie_rp, |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 141 | const struct soc_intel_common_block_pcie_rtd3_config *config, |
| 142 | enum pcie_rp_type rp_type) |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 143 | { |
| 144 | acpigen_write_method_serialized("_OFF", 0); |
| 145 | |
| 146 | /* Trigger L23 ready entry flow unless disabled by config. */ |
| 147 | if (!config->disable_l23) |
| 148 | pcie_rtd3_acpi_l23_entry(); |
| 149 | |
| 150 | /* Assert reset GPIO to place device into reset. */ |
| 151 | if (config->reset_gpio.pin_count) { |
| 152 | acpigen_enable_tx_gpio(&config->reset_gpio); |
| 153 | if (config->reset_off_delay_ms) |
| 154 | acpigen_write_sleep(config->reset_off_delay_ms); |
| 155 | } |
| 156 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 157 | /* Enable modPHY power gating for PCH RPs */ |
| 158 | if (rp_type == PCIE_RP_PCH) |
| 159 | pcie_rtd3_enable_modphy_pg(pcie_rp, PG_ENABLE); |
| 160 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 161 | /* Disable SRCCLK for this root port if pin is defined. */ |
| 162 | if (config->srcclk_pin >= 0) |
| 163 | pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); |
| 164 | |
| 165 | /* De-assert enable GPIO to turn off device power. */ |
| 166 | if (config->enable_gpio.pin_count) { |
| 167 | acpigen_disable_tx_gpio(&config->enable_gpio); |
| 168 | if (config->enable_off_delay_ms) |
| 169 | acpigen_write_sleep(config->enable_off_delay_ms); |
| 170 | } |
| 171 | |
| 172 | acpigen_pop_len(); /* Method */ |
| 173 | } |
| 174 | |
| 175 | static void |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 176 | pcie_rtd3_acpi_method_status(const struct soc_intel_common_block_pcie_rtd3_config *config) |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 177 | { |
| 178 | const struct acpi_gpio *gpio; |
| 179 | |
| 180 | acpigen_write_method("_STA", 0); |
| 181 | |
| 182 | /* Use enable GPIO for status if provided, otherwise use reset GPIO. */ |
| 183 | if (config->enable_gpio.pin_count) |
| 184 | gpio = &config->enable_gpio; |
| 185 | else |
| 186 | gpio = &config->reset_gpio; |
| 187 | |
| 188 | /* Read current GPIO value into Local0. */ |
| 189 | acpigen_get_tx_gpio(gpio); |
| 190 | |
| 191 | /* Ensure check works for both active low and active high GPIOs. */ |
| 192 | acpigen_write_store_int_to_op(gpio->active_low, LOCAL1_OP); |
| 193 | |
| 194 | acpigen_write_if_lequal_op_op(LOCAL0_OP, LOCAL1_OP); |
| 195 | acpigen_write_return_op(ZERO_OP); |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 196 | acpigen_write_else(); |
| 197 | acpigen_write_return_op(ONE_OP); |
| 198 | acpigen_pop_len(); /* Else */ |
| 199 | |
| 200 | acpigen_pop_len(); /* Method */ |
| 201 | } |
| 202 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 203 | static void write_modphy_opregion(unsigned int pcie_rp) |
| 204 | { |
| 205 | /* The register containing the Power Gate enable sequence bits is at |
| 206 | PCH_PWRM_BASE + 0x10D0, and the bits to check for sequence completion are at |
| 207 | PCH_PWRM_BASE + 0x10D4. */ |
| 208 | const struct opregion opregion = OPREGION("PMCP", SYSTEMMEMORY, |
| 209 | PCH_PWRM_BASE_ADDRESS + 0x1000, 0xff); |
| 210 | const struct fieldlist fieldlist[] = { |
| 211 | FIELDLIST_OFFSET(0xD0), |
| 212 | FIELDLIST_RESERVED(pcie_rp), |
| 213 | FIELDLIST_NAMESTR("EMPG", 1), /* Enable ModPHY Power Gate */ |
| 214 | FIELDLIST_OFFSET(0xD4), |
| 215 | FIELDLIST_RESERVED(pcie_rp), |
| 216 | FIELDLIST_NAMESTR("AMPG", 1), /* Is ModPHY Power Gate active? */ |
| 217 | }; |
| 218 | |
| 219 | acpigen_write_opregion(&opregion); |
| 220 | acpigen_write_field("PMCP", fieldlist, ARRAY_SIZE(fieldlist), |
| 221 | FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); |
| 222 | } |
| 223 | |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 224 | static int get_pcie_rp_pmc_idx(enum pcie_rp_type rp_type, const struct device *dev) |
| 225 | { |
| 226 | int idx = -1; |
| 227 | |
| 228 | switch (rp_type) { |
| 229 | case PCIE_RP_PCH: |
| 230 | /* Read port number of root port that this device is attached to. */ |
| 231 | idx = pci_read_config8(dev, PCH_PCIE_CFG_LCAP_PN); |
| 232 | |
| 233 | /* Port number is 1-based, PMC IPC method expects 0-based. */ |
| 234 | idx--; |
| 235 | break; |
| 236 | case PCIE_RP_CPU: |
| 237 | /* CPU RPs are indexed by their "virtual wire index" to the PCH */ |
| 238 | idx = soc_get_cpu_rp_vw_idx(dev); |
| 239 | break; |
| 240 | default: |
| 241 | break; |
| 242 | } |
| 243 | |
| 244 | return idx; |
| 245 | } |
| 246 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 247 | static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) |
| 248 | { |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 249 | static bool mutex_created = false; |
| 250 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 251 | const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); |
| 252 | static const char *const power_res_states[] = {"_PR0"}; |
| 253 | const struct device *parent = dev->bus->dev; |
| 254 | const char *scope = acpi_device_path(parent); |
| 255 | const struct opregion opregion = OPREGION("PXCS", PCI_CONFIG, 0, 0xff); |
| 256 | const struct fieldlist fieldlist[] = { |
| 257 | FIELDLIST_OFFSET(PCH_PCIE_CFG_LSTS), |
| 258 | FIELDLIST_RESERVED(13), |
| 259 | FIELDLIST_NAMESTR(ACPI_REG_PCI_LINK_ACTIVE, 1), |
| 260 | FIELDLIST_OFFSET(PCH_PCIE_CFG_SPR), |
| 261 | FIELDLIST_RESERVED(7), |
| 262 | FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_SAVE_STATE, 1), |
| 263 | FIELDLIST_OFFSET(PCH_PCIE_CFG_RPPGEN), |
| 264 | FIELDLIST_RESERVED(2), |
| 265 | FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_ENTRY, 1), |
| 266 | FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_DETECT, 1), |
| 267 | }; |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 268 | int pcie_rp; |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 269 | struct acpi_dp *dsd, *pkg; |
| 270 | |
| 271 | if (!is_dev_enabled(parent)) { |
| 272 | printk(BIOS_ERR, "%s: root port not enabled\n", __func__); |
| 273 | return; |
| 274 | } |
| 275 | if (!scope) { |
| 276 | printk(BIOS_ERR, "%s: root port scope not found\n", __func__); |
| 277 | return; |
| 278 | } |
| 279 | if (!config->enable_gpio.pin_count && !config->reset_gpio.pin_count) { |
| 280 | printk(BIOS_ERR, "%s: Enable and/or Reset GPIO required for %s.\n", |
| 281 | __func__, scope); |
| 282 | return; |
| 283 | } |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 284 | if (config->srcclk_pin > CONFIG_MAX_PCIE_CLOCK_SRC) { |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 285 | printk(BIOS_ERR, "%s: Invalid clock pin %u for %s.\n", __func__, |
| 286 | config->srcclk_pin, scope); |
| 287 | return; |
| 288 | } |
| 289 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 290 | const enum pcie_rp_type rp_type = soc_get_pcie_rp_type(parent); |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 291 | pcie_rp = get_pcie_rp_pmc_idx(rp_type, parent); |
| 292 | if (pcie_rp < 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { |
| 293 | printk(BIOS_ERR, "%s: Unknown PCIe root port\n", __func__); |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 294 | return; |
| 295 | } |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 296 | |
| 297 | printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), |
| 298 | config->desc ?: dev->chip_ops->name); |
| 299 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 300 | /* Create a mutex for exclusive access to the PMC registers. */ |
| 301 | if (rp_type == PCIE_RP_PCH && !mutex_created) { |
| 302 | acpigen_write_scope("\\_SB.PCI0"); |
| 303 | acpigen_write_mutex("R3MX", 0); |
| 304 | acpigen_write_scope_end(); |
| 305 | mutex_created = true; |
| 306 | } |
| 307 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 308 | /* The RTD3 power resource is added to the root port, not the device. */ |
| 309 | acpigen_write_scope(scope); |
| 310 | |
| 311 | if (config->desc) |
| 312 | acpigen_write_name_string("_DDN", config->desc); |
| 313 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 314 | /* Create OpRegions for MMIO accesses. */ |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 315 | acpigen_write_opregion(&opregion); |
| 316 | acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), |
| 317 | FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); |
| 318 | |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 319 | /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ |
| 320 | if (rp_type == PCIE_RP_PCH) |
| 321 | write_modphy_opregion(pcie_rp); |
| 322 | |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 323 | /* ACPI Power Resource for controlling the attached device power. */ |
| 324 | acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); |
Tim Wawrzynczak | b6a15a7 | 2021-12-08 10:43:56 -0700 | [diff] [blame] | 325 | pcie_rtd3_acpi_method_status(config); |
Tim Wawrzynczak | 32f883e | 2021-12-02 16:19:47 -0700 | [diff] [blame] | 326 | pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); |
| 327 | pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 328 | acpigen_pop_len(); /* PowerResource */ |
| 329 | |
| 330 | /* Indicate to the OS that device supports hotplug in D3. */ |
| 331 | dsd = acpi_dp_new_table("_DSD"); |
| 332 | pkg = acpi_dp_new_table(PCIE_HOTPLUG_IN_D3_UUID); |
| 333 | acpi_dp_add_integer(pkg, PCIE_HOTPLUG_IN_D3_PROPERTY, 1); |
| 334 | acpi_dp_add_package(dsd, pkg); |
| 335 | |
| 336 | /* Indicate to the OS if the device provides an External facing port. */ |
| 337 | if (config->is_external) { |
| 338 | pkg = acpi_dp_new_table(PCIE_EXTERNAL_PORT_UUID); |
| 339 | acpi_dp_add_integer(pkg, PCIE_EXTERNAL_PORT_PROPERTY, 1); |
| 340 | acpi_dp_add_package(dsd, pkg); |
| 341 | } |
| 342 | acpi_dp_write(dsd); |
| 343 | |
| 344 | /* |
| 345 | * Check the sibling device on the root port to see if it is storage class and add the |
| 346 | * property for the OS to enable storage D3, or allow it to be enabled by config. |
| 347 | */ |
| 348 | if (config->is_storage |
| 349 | || (dev->sibling && (dev->sibling->class >> 16) == PCI_BASE_CLASS_STORAGE)) { |
| 350 | acpigen_write_device(acpi_device_name(dev)); |
| 351 | acpigen_write_ADR(0); |
| 352 | acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); |
Tim Wawrzynczak | 6108321 | 2021-08-05 09:40:19 -0600 | [diff] [blame] | 353 | acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); |
Duncan Laurie | 64bc26a | 2020-10-10 00:15:28 +0000 | [diff] [blame] | 354 | |
| 355 | dsd = acpi_dp_new_table("_DSD"); |
| 356 | pkg = acpi_dp_new_table(PCIE_RTD3_STORAGE_UUID); |
| 357 | acpi_dp_add_integer(pkg, PCIE_RTD3_STORAGE_PROPERTY, 1); |
| 358 | acpi_dp_add_package(dsd, pkg); |
| 359 | acpi_dp_write(dsd); |
| 360 | |
| 361 | acpigen_pop_len(); /* Device */ |
| 362 | |
| 363 | printk(BIOS_INFO, "%s: Added StorageD3Enable property\n", scope); |
| 364 | } |
| 365 | |
| 366 | acpigen_pop_len(); /* Scope */ |
| 367 | } |
| 368 | |
| 369 | static const char *pcie_rtd3_acpi_name(const struct device *dev) |
| 370 | { |
| 371 | /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ |
| 372 | return "PXSX"; |
| 373 | } |
| 374 | |
| 375 | static struct device_operations pcie_rtd3_ops = { |
| 376 | .read_resources = noop_read_resources, |
| 377 | .set_resources = noop_set_resources, |
| 378 | .acpi_fill_ssdt = pcie_rtd3_acpi_fill_ssdt, |
| 379 | .acpi_name = pcie_rtd3_acpi_name, |
| 380 | }; |
| 381 | |
| 382 | static void pcie_rtd3_acpi_enable(struct device *dev) |
| 383 | { |
| 384 | dev->ops = &pcie_rtd3_ops; |
| 385 | } |
| 386 | |
| 387 | struct chip_operations soc_intel_common_block_pcie_rtd3_ops = { |
| 388 | CHIP_NAME("Intel PCIe Runtime D3") |
| 389 | .enable_dev = pcie_rtd3_acpi_enable |
| 390 | }; |