Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2008 Arastra, Inc. |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License version 2 as |
| 8 | ## published by the Free Software Foundation. |
| 9 | ## |
| 10 | ## This program is distributed in the hope that it will be useful, |
| 11 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | ## GNU General Public License for more details. |
| 14 | ## |
| 15 | ## You should have received a copy of the GNU General Public License |
| 16 | ## along with this program; if not, write to the Free Software |
| 17 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | ## |
| 19 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 20 | ## CONFIG_XIP_ROM_SIZE must be a power of 2. |
Patrick Georgi | b339e10 | 2009-08-11 17:35:02 +0000 | [diff] [blame^] | 21 | default CONFIG_XIP_ROM_SIZE = 64 * 1024 |
Carl-Daniel Hailfinger | cff071a | 2009-06-06 16:50:38 +0000 | [diff] [blame] | 22 | include /config/nofailovercalculation.lb |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 23 | |
| 24 | ## |
| 25 | ## Set all of the defaults for an x86 architecture |
| 26 | ## |
| 27 | |
| 28 | arch i386 end |
| 29 | |
| 30 | ## |
| 31 | ## Build the objects we have code for in this directory. |
| 32 | ## |
| 33 | |
| 34 | driver mainboard.o |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 35 | if CONFIG_HAVE_MP_TABLE object mptable.o end |
| 36 | if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 37 | |
| 38 | ## |
| 39 | ## Romcc output |
| 40 | ## |
| 41 | makerule ./failover.E |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 42 | depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" |
| 43 | action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 44 | end |
| 45 | |
| 46 | makerule ./failover.inc |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 47 | depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" |
| 48 | action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 49 | end |
| 50 | |
| 51 | makerule ./auto.E |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 52 | depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" |
| 53 | action "../romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 54 | end |
| 55 | makerule ./auto.inc |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 56 | depends "$(CONFIG_MAINBOARD)/auto.c ../romcc" |
| 57 | action "../romcc -mcpu=p4 -fno-simplify-phi -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 58 | end |
| 59 | |
| 60 | ## |
| 61 | ## Build our 16 bit and 32 bit coreboot entry code |
| 62 | ## |
| 63 | mainboardinit cpu/x86/16bit/entry16.inc |
| 64 | mainboardinit cpu/x86/32bit/entry32.inc |
| 65 | ldscript /cpu/x86/16bit/entry16.lds |
| 66 | ldscript /cpu/x86/32bit/entry32.lds |
| 67 | |
| 68 | ## |
| 69 | ## Build our reset vector (This is where coreboot is entered) |
| 70 | ## |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 71 | if CONFIG_USE_FALLBACK_IMAGE |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 72 | mainboardinit cpu/x86/16bit/reset16.inc |
| 73 | ldscript /cpu/x86/16bit/reset16.lds |
| 74 | else |
| 75 | mainboardinit cpu/x86/32bit/reset32.inc |
| 76 | ldscript /cpu/x86/32bit/reset32.lds |
| 77 | end |
| 78 | |
| 79 | ### Should this be in the northbridge code? |
| 80 | mainboardinit arch/i386/lib/cpu_reset.inc |
| 81 | |
| 82 | ## |
| 83 | ## Include an id string (For safe flashing) |
| 84 | ## |
| 85 | mainboardinit arch/i386/lib/id.inc |
| 86 | ldscript /arch/i386/lib/id.lds |
| 87 | |
| 88 | ### |
| 89 | ### This is the early phase of coreboot startup |
| 90 | ### Things are delicate and we test to see if we should |
| 91 | ### failover to another image. |
| 92 | ### |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 93 | if CONFIG_USE_FALLBACK_IMAGE |
Ed Swierk | 354e2d3 | 2008-03-16 23:39:24 +0000 | [diff] [blame] | 94 | ldscript /arch/i386/lib/failover.lds |
| 95 | mainboardinit ./failover.inc |
| 96 | end |
| 97 | |
| 98 | ### |
| 99 | ### O.k. We aren't just an intermediary anymore! |
| 100 | ### |
| 101 | |
| 102 | ## |
| 103 | ## Setup RAM |
| 104 | ## |
| 105 | mainboardinit cpu/x86/fpu/enable_fpu.inc |
| 106 | mainboardinit cpu/x86/mmx/enable_mmx.inc |
| 107 | mainboardinit cpu/x86/sse/enable_sse.inc |
| 108 | mainboardinit ./auto.inc |
| 109 | mainboardinit cpu/x86/sse/disable_sse.inc |
| 110 | mainboardinit cpu/x86/mmx/disable_mmx.inc |
| 111 | |
| 112 | ## |
| 113 | ## Include the secondary Configuration files |
| 114 | ## |
| 115 | dir /pc80 |
| 116 | config chip.h |
| 117 | |
| 118 | chip northbridge/intel/i3100 |
| 119 | device pci_domain 0 on |
| 120 | device pci 00.0 on end # IMCH |
| 121 | device pci 00.1 on end # IMCH error status |
| 122 | device pci 01.0 on end # IMCH EDMA engine |
| 123 | device pci 02.0 on end # PCIe port A/A0 |
| 124 | device pci 03.0 on end # PCIe port A1 |
| 125 | chip southbridge/intel/i3100 |
| 126 | # PIRQ line -> legacy IRQ mappings |
| 127 | register "pirq_a_d" = "0x0b070a05" |
| 128 | register "pirq_e_h" = "0x0a808080" |
| 129 | |
| 130 | device pci 1c.0 on end # PCIe port B0 |
| 131 | device pci 1c.1 on end # PCIe port B1 |
| 132 | device pci 1c.2 on end # PCIe port B2 |
| 133 | device pci 1c.3 on end # PCIe port B3 |
| 134 | device pci 1d.0 on end # USB (UHCI) 1 |
| 135 | device pci 1d.1 on end # USB (UHCI) 2 |
| 136 | device pci 1d.7 on end # USB (EHCI) |
| 137 | device pci 1e.0 on end # PCI bridge |
| 138 | device pci 1e.2 on end # audio |
| 139 | device pci 1e.3 on end # modem |
| 140 | device pci 1f.0 on # LPC bridge |
| 141 | chip superio/intel/i3100 |
| 142 | device pnp 4e.4 on # Com1 |
| 143 | io 0x60 = 0x3f8 |
| 144 | irq 0x70 = 4 |
| 145 | end |
| 146 | device pnp 4e.5 on # Com2 |
| 147 | io 0x60 = 0x2f8 |
| 148 | irq 0x70 = 3 |
| 149 | end |
| 150 | end |
| 151 | end |
| 152 | device pci 1f.2 on end # SATA |
| 153 | device pci 1f.3 on end # SMBus |
| 154 | end |
| 155 | end |
| 156 | device apic_cluster 0 on |
| 157 | chip cpu/intel/socket_mPGA479M |
| 158 | device apic 0 on end |
| 159 | end |
| 160 | end |
| 161 | end |