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efdesign98b0969d62011-06-16 16:35:54 -07001/* $NoKeywords:$ */
2/**
3 * @file
4 *
5 * Agesa structures and definitions
6 *
7 * Contains AMD AGESA core interface
8 *
9 * @xrefitem bom "File Content Label" "Release Content"
10 * @e project: AGESA
11 * @e sub-project: Include
12 * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
13 */
14/*****************************************************************************/
15/*
16 *****************************************************************************
17 *
18 * Copyright (c) 2011, Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * ***************************************************************************
44 *
45 */
46
47
48#ifndef _AMD_H_
49#define _AMD_H_
50
51#define AGESA_REVISION "Arch2008"
52#define AGESA_ID "AGESA"
53
54#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
55#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
56//
57//
58// AGESA Types and Definitions
59//
60//
61#define LAST_ENTRY 0xFFFFFFFF
62#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
63#define IOCF8 0xCF8
64#define IOCFC 0xCFC
65
66/// The return status for all AGESA public services.
67///
68/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
69/// will have log entries with more detail.
70///
71typedef enum {
72 AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
73 AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
74 ///< Not logged.
75 AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
76 ///< Example, memory address not installed, heap buffer handle not found.
77 ///< Not Logged.
78 // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
79 AGESA_ALERT, ///< An observed condition, but no loss of function.
80 ///< See log. Example, HT CRC.
81 AGESA_WARNING, ///< Possible or minor loss of function. See Log.
82 AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
83 AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
84 AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
85 ///< may not be able to reliably produce log events.
86 AgesaStatusMax ///< Not a status, for limit checking.
87} AGESA_STATUS;
88
89/// For checking whether a status is at or above the mandatory log level.
90#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
91
92/**
93 * Callout method to the host environment.
94 *
95 * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
96 *
97 * @param[in] Function The specific callout function being invoked.
98 * @param[in] FcnData Function specific data item.
99 * @param[in,out] ConfigPtr Reference to Callout params.
100 */
101typedef AGESA_STATUS (*CALLOUT_ENTRY) (
102 IN UINT32 Function,
103 IN UINTN FcnData,
104 IN OUT VOID *ConfigPtr
105 );
106
107typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
108typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
109
110///This allocation type is used by the AmdCreateStruct entry point
111typedef enum {
112 PreMemHeap = 0, ///< Create heap in cache.
113 PostMemDram, ///< Create heap in memory.
114 ByHost ///< Create heap by Host.
115} ALLOCATION_METHOD;
116
117/// These width descriptors are used by the library function, and others, to specify the data size
118typedef enum ACCESS_WIDTH {
119 AccessWidth8 = 1, ///< Access width is 8 bits.
120 AccessWidth16, ///< Access width is 16 bits.
121 AccessWidth32, ///< Access width is 32 bits.
122 AccessWidth64, ///< Access width is 64 bits.
123
124 AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
125 AccessS3SaveWidth16, ///< Save 16 bits data.
126 AccessS3SaveWidth32, ///< Save 32 bits data.
127 AccessS3SaveWidth64, ///< Save 64 bits data.
128} ACCESS_WIDTH;
129
130/// AGESA struct name
131typedef enum {
132 // AGESA BASIC FUNCTIONS
133 AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
134 AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
135 AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
136 AMD_INIT_ENV, ///< AmdInitEnv entry point handle
137 AMD_INIT_LATE, ///< AmdInitLate entry point handle
138 AMD_INIT_MID, ///< AmdInitMid entry point handle
139 AMD_INIT_POST, ///< AmdInitPost entry point handle
140 AMD_INIT_RESET, ///< AmdInitReset entry point handle
141 AMD_INIT_RESUME, ///< AmdInitResume entry point handle
142 AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
143 AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
144 AMD_S3_SAVE, ///< AmdS3Save entry point handle
145 AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
146 AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
147 AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
148 AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
149 AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
150 AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
151 AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
152} AGESA_STRUCT_NAME;
153
154 /* ResetType constant values */
155#define WARM_RESET_WHENEVER 1
156#define COLD_RESET_WHENEVER 2
157#define WARM_RESET_IMMEDIATELY 3
158#define COLD_RESET_IMMEDIATELY 4
159
160
161// AGESA Structures
162
163/// The standard header for all AGESA services.
164/// For internal AGESA naming conventions, see @ref amdconfigparamname .
165typedef struct {
166 IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
167 IN UINT32 Func; ///< The service desired
168 IN UINT32 AltImageBasePtr; ///< Alternate Image location
169 IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
170 IN UINT8 HeapStatus; ///< For heap status from boot time slide.
171 IN UINT64 HeapBasePtr; ///< Location of the heap
172 IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
173} AMD_CONFIG_PARAMS;
174
175
176/// Create Struct Interface.
177typedef struct {
178 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
179 IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
180 IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
181 IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
182 IN OUT VOID *NewStructPtr; ///< The struct for the service.
183 ///< The struct to init for ByHost allocation,
184 ///< the initialized struct on return.
185} AMD_INTERFACE_PARAMS;
186
187#define FUNC_0 0 // bit-placed for PCI address creation
188#define FUNC_1 1
189#define FUNC_2 2
190#define FUNC_3 3
191#define FUNC_4 4
192#define FUNC_5 5
193#define FUNC_6 6
194#define FUNC_7 7
195
196/// AGESA Binary module header structure
197typedef struct {
198 IN UINT32 Signature; ///< Binary Signature
199 IN CHAR8 CreatorID[8]; ///< 8 characters ID
200 IN CHAR8 Version[12]; ///< 12 characters version
201 IN UINT32 ModuleInfoOffset; ///< Offset of module
202 IN UINT32 EntryPointAddress; ///< Entry address
203 IN UINT32 ImageBase; ///< Image base
204 IN UINT32 RelocTableOffset; ///< Relocate Table offset
205 IN UINT32 ImageSize; ///< Size
206 IN UINT16 Checksum; ///< Checksum
207 IN UINT8 ImageType; ///< Type
208 IN UINT8 V_Reserved; ///< Reserved
209} AMD_IMAGE_HEADER;
210/// AGESA Binary module header structure
211typedef struct _AMD_MODULE_HEADER {
212 IN UINT32 ModuleHeaderSignature; ///< Module signature
213 IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
214 IN CHAR8 ModuleVersion[12]; ///< 12 characters version
215 IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
216 IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
217} AMD_MODULE_HEADER;
218
219// AMD_CODE_HEADER Signatures.
220#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
221#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
222#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
223
224/// AGESA_CODE_SIGNATURE
225typedef struct {
226 IN CHAR8 Signature[8]; ///< code header Signature
227 IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
228 IN CHAR8 Version[12]; ///< 12 character version string
229 IN CHAR8 TerminatorNull; ///< null terminated string
230 IN CHAR8 VerReserved[7]; ///< reserved space
231} AMD_CODE_HEADER;
232
233/// Extended PCI address format
234typedef struct {
235 IN OUT UINT32 Register:12; ///< Register offset
236 IN OUT UINT32 Function:3; ///< Function number
237 IN OUT UINT32 Device:5; ///< Device number
238 IN OUT UINT32 Bus:8; ///< Bus number
239 IN OUT UINT32 Segment:4; ///< Segment
240} EXT_PCI_ADDR;
241
242/// Union type for PCI address
243typedef union _PCI_ADDR {
244 IN UINT32 AddressValue; ///< Formal address
245 IN EXT_PCI_ADDR Address; ///< Extended address
246} PCI_ADDR;
247
248// SBDFO - Segment Bus Device Function Offset
249// 31:28 Segment (4-bits)
250// 27:20 Bus (8-bits)
251// 19:15 Device (5-bits)
252// 14:12 Function(3-bits)
253// 11:00 Offset (12-bits)
254
255#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
256 (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
257#define ILLEGAL_SBDFO 0xFFFFFFFF
258
259/// CPUID data received registers format
260typedef struct {
261 OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
262 OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
263 OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
264 OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
265} CPUID_DATA;
266
267/// HT frequency for external callbacks
268typedef enum {
269 HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
270 HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
271 HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
272 HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
273 HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
274 HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
275 HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
276 HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
277 HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
278 HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
279 HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
280 HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
281 HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
282 HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
283 HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
284 HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
285 HT_FREQUENCY_MAX ///< Limit check.
286} HT_FREQUENCIES;
287// The minimum HT3 frequency
288#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
289
290#ifndef BIT0
291 #define BIT0 0x0000000000000001ull
292#endif
293#ifndef BIT1
294 #define BIT1 0x0000000000000002ull
295#endif
296#ifndef BIT2
297 #define BIT2 0x0000000000000004ull
298#endif
299#ifndef BIT3
300 #define BIT3 0x0000000000000008ull
301#endif
302#ifndef BIT4
303 #define BIT4 0x0000000000000010ull
304#endif
305#ifndef BIT5
306 #define BIT5 0x0000000000000020ull
307#endif
308#ifndef BIT6
309 #define BIT6 0x0000000000000040ull
310#endif
311#ifndef BIT7
312 #define BIT7 0x0000000000000080ull
313#endif
314#ifndef BIT8
315 #define BIT8 0x0000000000000100ull
316#endif
317#ifndef BIT9
318 #define BIT9 0x0000000000000200ull
319#endif
320#ifndef BIT10
321 #define BIT10 0x0000000000000400ull
322#endif
323#ifndef BIT11
324 #define BIT11 0x0000000000000800ull
325#endif
326#ifndef BIT12
327 #define BIT12 0x0000000000001000ull
328#endif
329#ifndef BIT13
330 #define BIT13 0x0000000000002000ull
331#endif
332#ifndef BIT14
333 #define BIT14 0x0000000000004000ull
334#endif
335#ifndef BIT15
336 #define BIT15 0x0000000000008000ull
337#endif
338#ifndef BIT16
339 #define BIT16 0x0000000000010000ull
340#endif
341#ifndef BIT17
342 #define BIT17 0x0000000000020000ull
343#endif
344#ifndef BIT18
345 #define BIT18 0x0000000000040000ull
346#endif
347#ifndef BIT19
348 #define BIT19 0x0000000000080000ull
349#endif
350#ifndef BIT20
351 #define BIT20 0x0000000000100000ull
352#endif
353#ifndef BIT21
354 #define BIT21 0x0000000000200000ull
355#endif
356#ifndef BIT22
357 #define BIT22 0x0000000000400000ull
358#endif
359#ifndef BIT23
360 #define BIT23 0x0000000000800000ull
361#endif
362#ifndef BIT24
363 #define BIT24 0x0000000001000000ull
364#endif
365#ifndef BIT25
366 #define BIT25 0x0000000002000000ull
367#endif
368#ifndef BIT26
369 #define BIT26 0x0000000004000000ull
370#endif
371#ifndef BIT27
372 #define BIT27 0x0000000008000000ull
373#endif
374#ifndef BIT28
375 #define BIT28 0x0000000010000000ull
376#endif
377#ifndef BIT29
378 #define BIT29 0x0000000020000000ull
379#endif
380#ifndef BIT30
381 #define BIT30 0x0000000040000000ull
382#endif
383#ifndef BIT31
384 #define BIT31 0x0000000080000000ull
385#endif
386#ifndef BIT32
387 #define BIT32 0x0000000100000000ull
388#endif
389#ifndef BIT33
390 #define BIT33 0x0000000200000000ull
391#endif
392#ifndef BIT34
393 #define BIT34 0x0000000400000000ull
394#endif
395#ifndef BIT35
396 #define BIT35 0x0000000800000000ull
397#endif
398#ifndef BIT36
399 #define BIT36 0x0000001000000000ull
400#endif
401#ifndef BIT37
402 #define BIT37 0x0000002000000000ull
403#endif
404#ifndef BIT38
405 #define BIT38 0x0000004000000000ull
406#endif
407#ifndef BIT39
408 #define BIT39 0x0000008000000000ull
409#endif
410#ifndef BIT40
411 #define BIT40 0x0000010000000000ull
412#endif
413#ifndef BIT41
414 #define BIT41 0x0000020000000000ull
415#endif
416#ifndef BIT42
417 #define BIT42 0x0000040000000000ull
418#endif
419#ifndef BIT43
420 #define BIT43 0x0000080000000000ull
421#endif
422#ifndef BIT44
423 #define BIT44 0x0000100000000000ull
424#endif
425#ifndef BIT45
426 #define BIT45 0x0000200000000000ull
427#endif
428#ifndef BIT46
429 #define BIT46 0x0000400000000000ull
430#endif
431#ifndef BIT47
432 #define BIT47 0x0000800000000000ull
433#endif
434#ifndef BIT48
435 #define BIT48 0x0001000000000000ull
436#endif
437#ifndef BIT49
438 #define BIT49 0x0002000000000000ull
439#endif
440#ifndef BIT50
441 #define BIT50 0x0004000000000000ull
442#endif
443#ifndef BIT51
444 #define BIT51 0x0008000000000000ull
445#endif
446#ifndef BIT52
447 #define BIT52 0x0010000000000000ull
448#endif
449#ifndef BIT53
450 #define BIT53 0x0020000000000000ull
451#endif
452#ifndef BIT54
453 #define BIT54 0x0040000000000000ull
454#endif
455#ifndef BIT55
456 #define BIT55 0x0080000000000000ull
457#endif
458#ifndef BIT56
459 #define BIT56 0x0100000000000000ull
460#endif
461#ifndef BIT57
462 #define BIT57 0x0200000000000000ull
463#endif
464#ifndef BIT58
465 #define BIT58 0x0400000000000000ull
466#endif
467#ifndef BIT59
468 #define BIT59 0x0800000000000000ull
469#endif
470#ifndef BIT60
471 #define BIT60 0x1000000000000000ull
472#endif
473#ifndef BIT61
474 #define BIT61 0x2000000000000000ull
475#endif
476#ifndef BIT62
477 #define BIT62 0x4000000000000000ull
478#endif
479#ifndef BIT63
480 #define BIT63 0x8000000000000000ull
481#endif
482
483#endif // _AMD_H_