Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 1 | #include <arch/io.h> |
| 2 | |
| 3 | /* Just define these here, there is no gm35.h file to include. */ |
| 4 | #define D0F0_PCIEXBAR_LO 0x60 |
| 5 | #define D0F0_PCIEXBAR_HI 0x64 |
| 6 | |
| 7 | static void bootblock_northbridge_init(void) |
| 8 | { |
| 9 | uint32_t reg; |
| 10 | |
| 11 | /* |
| 12 | * The "io" variant of the config access is explicitly used to |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 13 | * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 14 | * to true. That way all subsequent non-explicit config accesses use |
| 15 | * MCFG. This code also assumes that bootblock_northbridge_init() is |
| 16 | * the first thing called in the non-asm boot block code. The final |
| 17 | * assumption is that no assembly code is using the |
Kyösti Mälkki | 6f66f41 | 2016-12-01 22:08:18 +0200 | [diff] [blame] | 18 | * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. |
Kyösti Mälkki | b9646a2 | 2013-07-03 08:06:32 +0300 | [diff] [blame] | 19 | * |
| 20 | * The PCIEXBAR is assumed to live in the memory mapped IO space under |
| 21 | * 4GiB. |
| 22 | */ |
| 23 | reg = 0; |
| 24 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg); |
| 25 | reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */ |
| 26 | pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg); |
| 27 | } |
| 28 | |
| 29 | static void bootblock_mainboard_init(void) |
| 30 | { |
| 31 | bootblock_northbridge_init(); |
| 32 | bootblock_southbridge_init(); |
| 33 | } |