| Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <amdblocks/memmap.h> |
| 4 | #include <cbmem.h> |
| 5 | #include <console/console.h> |
| 6 | #include <cpu/amd/msr.h> |
| 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <device/pci_ids.h> |
| 10 | #include <fsp/util.h> |
| 11 | #include <stdint.h> |
| 12 | |
| 13 | /* |
| 14 | * |
| 15 | * +--------------------------------+ |
| 16 | * | | |
| 17 | * | | |
| 18 | * | | |
| 19 | * | | |
| 20 | * | | |
| 21 | * | | |
| 22 | * | | |
| 23 | * reserved_dram_end +--------------------------------+ |
| 24 | * | | |
| 25 | * | verstage (if reqd) | |
| 26 | * | (VERSTAGE_SIZE) | |
| 27 | * +--------------------------------+ VERSTAGE_ADDR |
| 28 | * | | |
| 29 | * | FSP-M | |
| 30 | * | (FSP_M_SIZE) | |
| 31 | * +--------------------------------+ FSP_M_ADDR |
| 32 | * | romstage | |
| 33 | * | (ROMSTAGE_SIZE) | |
| 34 | * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END |
| 35 | * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 |
| 36 | * | bootblock | |
| 37 | * | (C_ENV_BOOTBLOCK_SIZE) | |
| 38 | * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE |
| 39 | * | Unused hole | |
| 40 | * | (86KiB) | |
| 41 | * +--------------------------------+ |
| 42 | * | FMAP cache (FMAP_SIZE) | |
| 43 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 |
| 44 | * | Early Timestamp region (512B) | |
| 45 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE |
| 46 | * | Preram CBMEM console | |
| 47 | * | (PRERAM_CBMEM_CONSOLE_SIZE) | |
| 48 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE |
| 49 | * | PSP shared (vboot workbuf) | |
| 50 | * | (PSP_SHAREDMEM_SIZE) | |
| 51 | * +--------------------------------+ PSP_SHAREDMEM_BASE |
| 52 | * | APOB (64KiB) | |
| 53 | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS |
| 54 | * | Early BSP stack | |
| 55 | * | (EARLYRAM_BSP_STACK_SIZE) | |
| 56 | * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE |
| 57 | * | DRAM | |
| 58 | * +--------------------------------+ 0x100000 |
| 59 | * | Option ROM | |
| 60 | * +--------------------------------+ 0xc0000 |
| 61 | * | Legacy VGA | |
| 62 | * +--------------------------------+ 0xa0000 |
| 63 | * | DRAM | |
| 64 | * +--------------------------------+ 0x0 |
| 65 | */ |
| 66 | static void read_resources(struct device *dev) |
| 67 | { |
| 68 | uint32_t mem_usable = (uintptr_t)cbmem_top(); |
| 69 | unsigned int idx = 0; |
| 70 | const struct hob_header *hob = fsp_get_hob_list(); |
| 71 | const struct hob_resource *res; |
| 72 | |
| 73 | uintptr_t early_reserved_dram_start, early_reserved_dram_end; |
| 74 | const struct memmap_early_dram *e = memmap_get_early_dram_usage(); |
| 75 | |
| 76 | early_reserved_dram_start = e->base; |
| 77 | early_reserved_dram_end = e->base + e->size; |
| 78 | |
| 79 | /* 0x0 - 0x9ffff */ |
| 80 | ram_resource(dev, idx++, 0, 0xa0000 / KiB); |
| 81 | |
| 82 | /* 0xa0000 - 0xbffff: legacy VGA */ |
| 83 | mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); |
| 84 | |
| 85 | /* 0xc0000 - 0xfffff: Option ROM */ |
| 86 | reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); |
| 87 | |
| 88 | /* 1MiB - bottom of DRAM reserved for early coreboot usage */ |
| 89 | ram_resource(dev, idx++, (1 * MiB) / KiB, |
| 90 | (early_reserved_dram_start - (1 * MiB)) / KiB); |
| 91 | |
| 92 | /* DRAM reserved for early coreboot usage */ |
| 93 | reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB, |
| 94 | (early_reserved_dram_end - early_reserved_dram_start) / KiB); |
| 95 | |
| 96 | /* |
| 97 | * top of DRAM consumed early - low top usable RAM |
| 98 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
| 99 | */ |
| 100 | ram_resource(dev, idx++, early_reserved_dram_end / KiB, |
| 101 | (mem_usable - early_reserved_dram_end) / KiB); |
| 102 | |
| 103 | mmconf_resource(dev, MMIO_CONF_BASE); |
| 104 | |
| 105 | if (!hob) { |
| 106 | printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", |
| 107 | __func__); |
| 108 | return; |
| 109 | } |
| 110 | |
| 111 | for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { |
| 112 | |
| 113 | if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) |
| 114 | continue; |
| 115 | |
| 116 | res = fsp_hob_header_to_resource(hob); |
| 117 | |
| 118 | if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable) |
| 119 | continue; /* 0 through low usable was set above */ |
| 120 | if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO) |
| 121 | continue; /* Done separately */ |
| 122 | |
| 123 | if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) |
| 124 | ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); |
| 125 | else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) |
| 126 | reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); |
| 127 | else |
| 128 | printk(BIOS_ERR, "Error: failed to set resources for type %d\n", |
| 129 | res->type); |
| 130 | } |
| 131 | } |
| 132 | |
| 133 | static struct device_operations root_complex_operations = { |
| 134 | .read_resources = read_resources, |
| 135 | .set_resources = noop_set_resources, |
| 136 | .enable_resources = pci_dev_enable_resources, |
| 137 | }; |
| 138 | |
| 139 | static const struct pci_driver family17_root_complex __pci_driver = { |
| 140 | .ops = &root_complex_operations, |
| 141 | .vendor = PCI_VENDOR_ID_AMD, |
| 142 | .device = PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB, |
| 143 | }; |