Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <console/console.h> |
| 25 | #include <arch/smp/mpspec.h> |
| 26 | #include <arch/ioapic.h> |
| 27 | #include <string.h> |
| 28 | #include <stdint.h> |
| 29 | |
| 30 | static void *smp_write_config_table(void *v) |
| 31 | { |
| 32 | struct mp_config_table *mc; |
| 33 | int isa_bus; |
| 34 | |
| 35 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 36 | |
| 37 | mptable_init(mc, LAPIC_ADDR); |
| 38 | |
| 39 | smp_write_processors(mc); |
| 40 | |
| 41 | mptable_write_buses(mc, NULL, &isa_bus); |
| 42 | |
| 43 | /* I/O APICs: APIC ID Version State Address */ |
| 44 | smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); |
| 45 | |
| 46 | /* Legacy Interrupts */ |
| 47 | mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0); |
| 48 | |
| 49 | smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, isa_bus, 0x00, MP_APIC_ALL, 0x00); |
| 50 | smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x00, MP_APIC_ALL, 0x01); |
| 51 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x01 << 2), 0x02, 0x10); /* PCIe root 0.02.0 */ |
| 52 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x02 << 2), 0x02, 0x10); /* VGA 0.02.0 */ |
| 53 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1b << 2), 0x02, 0x11); /* HD Audio 0:1b.0 */ |
| 54 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2), 0x02, 0x14); /* PCIe 0:1c.0 */ |
| 55 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x01, 0x02, 0x15); /* PCIe 0:1c.1 */ |
| 56 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x02, 0x02, 0x16); /* PCIe 0:1c.2 */ |
| 57 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1c << 2) | 0x03, 0x02, 0x17); /* PCIe 0:1c.3 */ |
| 58 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) , 0x02, 0x10); /* USB 0:1d.0 */ |
| 59 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x01, 0x02, 0x11); /* USB 0:1d.1 */ |
| 60 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x02, 0x02, 0x12); /* USB 0:1d.2 */ |
| 61 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1d << 2) | 0x03, 0x02, 0x13); /* USB 0:1d.3 */ |
| 62 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) , 0x02, 0x17); /* LPC 0:1f.0 */ |
| 63 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x01, 0x02, 0x10); /* IDE 0:1f.1 */ |
| 64 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x00, (0x1f << 2) | 0x02, 0x02, 0x10); /* SATA 0:1f.2 */ |
| 65 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x00, 0x02, 0x10); /* Cardbus 5:00.0 */ |
| 66 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x01, 0x02, 0x11); /* Firewire 5:00.1 */ |
| 67 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x05, (0x00 << 2) | 0x02, 0x02, 0x12); /* SDHC 5:00.2 */ |
| 68 | |
| 69 | smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 0); |
| 70 | smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_HIGH, isa_bus, 0, MP_APIC_ALL, 1); |
| 71 | |
| 72 | mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); |
| 73 | mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); |
| 74 | |
| 75 | printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); |
| 76 | |
| 77 | return smp_next_mpe_entry(mc); |
| 78 | } |
| 79 | |
| 80 | unsigned long write_smp_table(unsigned long addr) |
| 81 | { |
| 82 | void *v; |
Patrick Georgi | c75c79b | 2011-10-07 22:41:07 +0200 | [diff] [blame^] | 83 | v = smp_write_floating_table(addr, 0); |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 84 | return (unsigned long)smp_write_config_table(v); |
| 85 | } |