Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 2 | |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 4 | #include <stdint.h> |
| 5 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 6 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 8 | #include <device/pci_def.h> |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 9 | #include <device/device.h> |
Kyösti Mälkki | 1a1b04e | 2020-01-07 22:34:33 +0200 | [diff] [blame] | 10 | #include <device/smbus_host.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 11 | #include <spd.h> |
| 12 | #include <console/console.h> |
| 13 | #include <lib.h> |
Arthur Heymans | 10141c3 | 2016-10-27 00:31:41 +0200 | [diff] [blame] | 14 | #include <delay.h> |
Arthur Heymans | 049347f | 2017-05-12 11:54:08 +0200 | [diff] [blame] | 15 | #include <timestamp.h> |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 16 | #include "gm45.h" |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 17 | #include "chip.h" |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 18 | |
| 19 | static const gmch_gfx_t gmch_gfx_types[][5] = { |
| 20 | /* MAX_667MHz MAX_533MHz MAX_400MHz MAX_333MHz MAX_800MHz */ |
| 21 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 22 | { GMCH_GM47, GMCH_GM45, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_GM49 }, |
| 23 | { GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45, GMCH_GE45 }, |
| 24 | { GMCH_UNKNOWN, GMCH_GL43, GMCH_GL40, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 25 | { GMCH_UNKNOWN, GMCH_GS45, GMCH_GS40, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 26 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 27 | { GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN, GMCH_UNKNOWN }, |
| 28 | { GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45, GMCH_PM45 }, |
| 29 | }; |
| 30 | |
| 31 | void get_gmch_info(sysinfo_t *sysinfo) |
| 32 | { |
| 33 | sysinfo->stepping = pci_read_config8(PCI_DEV(0, 0, 0), PCI_CLASS_REVISION); |
| 34 | if ((sysinfo->stepping > STEPPING_B3) && |
| 35 | (sysinfo->stepping != STEPPING_CONVERSION_A1)) |
| 36 | die("Unknown stepping.\n"); |
| 37 | if (sysinfo->stepping <= STEPPING_B3) |
| 38 | printk(BIOS_DEBUG, "Stepping %c%d\n", 'A' + sysinfo->stepping / 4, sysinfo->stepping % 4); |
| 39 | else |
| 40 | printk(BIOS_DEBUG, "Conversion stepping A1\n"); |
| 41 | |
| 42 | const u32 eax = cpuid_ext(0x04, 0).eax; |
| 43 | sysinfo->cores = ((eax >> 26) & 0x3f) + 1; |
| 44 | printk(BIOS_SPEW, "%d CPU cores\n", sysinfo->cores); |
| 45 | |
| 46 | u32 capid = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_CAPID0+8); |
| 47 | if (!(capid & (1<<(79-64)))) { |
| 48 | printk(BIOS_SPEW, "iTPM enabled\n"); |
| 49 | } |
| 50 | |
| 51 | capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0+4); |
| 52 | if (!(capid & (1<<(57-32)))) { |
| 53 | printk(BIOS_SPEW, "ME enabled\n"); |
| 54 | } |
| 55 | |
| 56 | if (!(capid & (1<<(56-32)))) { |
| 57 | printk(BIOS_SPEW, "AMT enabled\n"); |
| 58 | } |
| 59 | |
| 60 | sysinfo->max_ddr2_mhz = (capid & (1<<(53-32)))?667:800; |
| 61 | printk(BIOS_SPEW, "capable of DDR2 of %d MHz or lower\n", sysinfo->max_ddr2_mhz); |
| 62 | |
| 63 | if (!(capid & (1<<(48-32)))) { |
| 64 | printk(BIOS_SPEW, "VT-d enabled\n"); |
| 65 | } |
| 66 | |
| 67 | const u32 gfx_variant = (capid>>(42-32)) & 0x7; |
| 68 | const u32 render_freq = ((capid>>(50-32) & 0x1) << 2) | ((capid>>(35-32)) & 0x3); |
| 69 | if (render_freq <= 4) |
| 70 | sysinfo->gfx_type = gmch_gfx_types[gfx_variant][render_freq]; |
| 71 | else |
| 72 | sysinfo->gfx_type = GMCH_UNKNOWN; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 73 | switch (sysinfo->gfx_type) { |
| 74 | case GMCH_GM45: |
| 75 | printk(BIOS_SPEW, "GMCH: GM45\n"); |
| 76 | break; |
| 77 | case GMCH_GM47: |
| 78 | printk(BIOS_SPEW, "GMCH: GM47\n"); |
| 79 | break; |
| 80 | case GMCH_GM49: |
| 81 | printk(BIOS_SPEW, "GMCH: GM49\n"); |
| 82 | break; |
| 83 | case GMCH_GE45: |
| 84 | printk(BIOS_SPEW, "GMCH: GE45\n"); |
| 85 | break; |
| 86 | case GMCH_GL40: |
| 87 | printk(BIOS_SPEW, "GMCH: GL40\n"); |
| 88 | break; |
| 89 | case GMCH_GL43: |
| 90 | printk(BIOS_SPEW, "GMCH: GL43\n"); |
| 91 | break; |
| 92 | case GMCH_GS40: |
| 93 | printk(BIOS_SPEW, "GMCH: GS40\n"); |
| 94 | break; |
| 95 | case GMCH_GS45: |
Nico Huber | 5aaeb27 | 2015-12-30 00:17:27 +0100 | [diff] [blame] | 96 | printk(BIOS_SPEW, "GMCH: GS45, using %s-power mode\n", |
| 97 | sysinfo->gs45_low_power_mode ? "low" : "high"); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 98 | break; |
| 99 | case GMCH_PM45: |
| 100 | printk(BIOS_SPEW, "GMCH: PM45\n"); |
| 101 | break; |
| 102 | case GMCH_UNKNOWN: |
| 103 | printk(BIOS_SPEW, "unknown GMCH\n"); |
| 104 | break; |
| 105 | } |
| 106 | |
| 107 | sysinfo->txt_enabled = !(capid & (1 << (37-32))); |
| 108 | if (sysinfo->txt_enabled) { |
| 109 | printk(BIOS_SPEW, "TXT enabled\n"); |
| 110 | } |
| 111 | |
| 112 | switch (render_freq) { |
| 113 | case 4: |
| 114 | sysinfo->max_render_mhz = 800; |
| 115 | break; |
| 116 | case 0: |
| 117 | sysinfo->max_render_mhz = 667; |
| 118 | break; |
| 119 | case 1: |
| 120 | sysinfo->max_render_mhz = 533; |
| 121 | break; |
| 122 | case 2: |
| 123 | sysinfo->max_render_mhz = 400; |
| 124 | break; |
| 125 | case 3: |
| 126 | sysinfo->max_render_mhz = 333; |
| 127 | break; |
| 128 | default: |
| 129 | printk(BIOS_SPEW, "Unknown render frequency\n"); |
| 130 | sysinfo->max_render_mhz = 0; |
| 131 | break; |
| 132 | } |
| 133 | if (sysinfo->max_render_mhz != 0) { |
| 134 | printk(BIOS_SPEW, "Render frequency: %d MHz\n", sysinfo->max_render_mhz); |
| 135 | } |
| 136 | |
| 137 | if (!(capid & (1<<(33-32)))) { |
| 138 | printk(BIOS_SPEW, "IGD enabled\n"); |
| 139 | } |
| 140 | |
| 141 | if (!(capid & (1<<(32-32)))) { |
| 142 | printk(BIOS_SPEW, "PCIe-to-GMCH enabled\n"); |
| 143 | } |
| 144 | |
| 145 | capid = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0); |
| 146 | |
| 147 | u32 ddr_cap = capid>>30 & 0x3; |
| 148 | switch (ddr_cap) { |
| 149 | case 0: |
| 150 | sysinfo->max_ddr3_mt = 1067; |
| 151 | break; |
| 152 | case 1: |
| 153 | sysinfo->max_ddr3_mt = 800; |
| 154 | break; |
| 155 | case 2: |
| 156 | case 3: |
| 157 | printk(BIOS_SPEW, "GMCH not DDR3 capable\n"); |
| 158 | sysinfo->max_ddr3_mt = 0; |
| 159 | break; |
| 160 | } |
| 161 | if (sysinfo->max_ddr3_mt != 0) { |
| 162 | printk(BIOS_SPEW, "GMCH supports DDR3 with %d MT or less\n", sysinfo->max_ddr3_mt); |
| 163 | } |
| 164 | |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 165 | const unsigned int max_fsb = (capid >> 28) & 0x3; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 166 | switch (max_fsb) { |
| 167 | case 1: |
| 168 | sysinfo->max_fsb_mhz = 1067; |
| 169 | break; |
| 170 | case 2: |
| 171 | sysinfo->max_fsb_mhz = 800; |
| 172 | break; |
| 173 | case 3: |
| 174 | sysinfo->max_fsb_mhz = 667; |
| 175 | break; |
| 176 | default: |
| 177 | die("unknown FSB capability\n"); |
| 178 | break; |
| 179 | } |
| 180 | if (sysinfo->max_fsb_mhz != 0) { |
| 181 | printk(BIOS_SPEW, "GMCH supports FSB with up to %d MHz\n", sysinfo->max_fsb_mhz); |
| 182 | } |
| 183 | sysinfo->max_fsb = max_fsb - 1; |
| 184 | } |
| 185 | |
| 186 | /* |
| 187 | * Detect if the system went through an interrupted RAM init or is incon- |
| 188 | * sistent. If so, initiate a cold reboot. Otherwise mark the system to be |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 189 | * in RAM init, so this function would detect it on an erroneous reboot. |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 190 | */ |
| 191 | void enter_raminit_or_reset(void) |
| 192 | { |
| 193 | /* Interrupted RAM init or inconsistent system? */ |
| 194 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
| 195 | |
| 196 | if (reg8 & (1 << 2)) { /* S4-assertion-width violation */ |
| 197 | /* Ignore S4-assertion-width violation like original BIOS. */ |
| 198 | printk(BIOS_WARNING, |
| 199 | "WARNING: Ignoring S4-assertion-width violation.\n"); |
| 200 | /* Bit2 is R/WC, so it will clear itself below. */ |
| 201 | } |
| 202 | |
| 203 | if (reg8 & (1 << 7)) { /* interrupted RAM init */ |
| 204 | /* Don't enable S4-assertion stretch. Makes trouble on roda/rk9. |
| 205 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 206 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8 | 0x08); |
| 207 | */ |
| 208 | |
| 209 | /* Clear bit7. */ |
| 210 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~(1 << 7)); |
| 211 | |
| 212 | printk(BIOS_INFO, "Interrupted RAM init, reset required.\n"); |
| 213 | gm45_early_reset(); |
| 214 | } |
| 215 | /* Mark system to be in RAM init. */ |
| 216 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 | (1 << 7)); |
| 217 | } |
| 218 | |
| 219 | |
| 220 | /* For a detected DIMM, test the value of an SPD byte to |
| 221 | match the expected value after masking some bits. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 222 | static int test_dimm(sysinfo_t *const sysinfo, |
| 223 | int dimm, int addr, int bitmask, int expected) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 224 | { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 225 | return (smbus_read_byte(sysinfo->spd_map[dimm], addr) & bitmask) == expected; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | /* This function dies if dimm is unsuitable for the chipset. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 229 | static void verify_ddr3_dimm(sysinfo_t *const sysinfo, int dimm) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 230 | { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 231 | if (!test_dimm(sysinfo, dimm, 3, 15, 3)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 232 | die("Chipset only supports SO-DIMM\n"); |
| 233 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 234 | if (!test_dimm(sysinfo, dimm, 8, 0x18, 0)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 235 | die("Chipset doesn't support ECC RAM\n"); |
| 236 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 237 | if (!test_dimm(sysinfo, dimm, 7, 0x38, 0) && |
| 238 | !test_dimm(sysinfo, dimm, 7, 0x38, 8)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 239 | die("Chipset wants single or double sided DIMMs\n"); |
| 240 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 241 | if (!test_dimm(sysinfo, dimm, 7, 7, 1) && |
| 242 | !test_dimm(sysinfo, dimm, 7, 7, 2)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 243 | die("Chipset requires x8 or x16 width\n"); |
| 244 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 245 | if (!test_dimm(sysinfo, dimm, 4, 0x0f, 0) && |
| 246 | !test_dimm(sysinfo, dimm, 4, 0x0f, 1) && |
| 247 | !test_dimm(sysinfo, dimm, 4, 0x0f, 2) && |
| 248 | !test_dimm(sysinfo, dimm, 4, 0x0f, 3)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 249 | die("Chipset requires 256Mb, 512Mb, 1Gb or 2Gb chips."); |
| 250 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 251 | if (!test_dimm(sysinfo, dimm, 4, 0x70, 0)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 252 | die("Chipset requires 8 banks on DDR3\n"); |
| 253 | |
| 254 | /* How to check if burst length is 8? |
| 255 | Other values are not supported, are they even possible? */ |
| 256 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 257 | if (!test_dimm(sysinfo, dimm, 10, 0xff, 1)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 258 | die("Code assumes 1/8ns MTB\n"); |
| 259 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 260 | if (!test_dimm(sysinfo, dimm, 11, 0xff, 8)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 261 | die("Code assumes 1/8ns MTB\n"); |
| 262 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 263 | if (!test_dimm(sysinfo, dimm, 62, 0x9f, 0) && |
| 264 | !test_dimm(sysinfo, dimm, 62, 0x9f, 1) && |
| 265 | !test_dimm(sysinfo, dimm, 62, 0x9f, 2) && |
| 266 | !test_dimm(sysinfo, dimm, 62, 0x9f, 3) && |
| 267 | !test_dimm(sysinfo, dimm, 62, 0x9f, 5)) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 268 | die("Only raw card types A, B, C, D and F are supported.\n"); |
| 269 | } |
| 270 | |
| 271 | /* For every detected DIMM, test if it's suitable for the chipset. */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 272 | static void verify_ddr3(sysinfo_t *const sysinfo, int mask) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 273 | { |
| 274 | int cur = 0; |
| 275 | while (mask) { |
| 276 | if (mask & 1) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 277 | verify_ddr3_dimm(sysinfo, cur); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 278 | } |
| 279 | mask >>= 1; |
| 280 | cur++; |
| 281 | } |
| 282 | } |
| 283 | |
| 284 | |
| 285 | typedef struct { |
| 286 | int dimm_mask; |
| 287 | struct { |
| 288 | unsigned int rows; |
| 289 | unsigned int cols; |
| 290 | unsigned int chip_capacity; |
| 291 | unsigned int banks; |
| 292 | unsigned int ranks; |
| 293 | unsigned int cas_latencies; |
| 294 | unsigned int tAAmin; |
| 295 | unsigned int tCKmin; |
| 296 | unsigned int width; |
| 297 | unsigned int tRAS; |
| 298 | unsigned int tRP; |
| 299 | unsigned int tRCD; |
| 300 | unsigned int tWR; |
| 301 | unsigned int page_size; |
| 302 | unsigned int raw_card; |
| 303 | } channel[2]; |
| 304 | } spdinfo_t; |
| 305 | /* |
| 306 | * This function collects RAM characteristics from SPD, assuming that RAM |
| 307 | * is generally within chipset's requirements, since verify_ddr3() passed. |
| 308 | */ |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 309 | static void collect_ddr3(sysinfo_t *const sysinfo, spdinfo_t *const config) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 310 | { |
| 311 | int mask = config->dimm_mask; |
| 312 | int cur = 0; |
| 313 | while (mask != 0) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 314 | /* FIXME: support several dimms on same channel. */ |
| 315 | if ((mask & 1) && sysinfo->spd_map[2 * cur]) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 316 | int tmp; |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 317 | const int smb_addr = sysinfo->spd_map[2 * cur]; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 318 | |
| 319 | config->channel[cur].rows = ((smbus_read_byte(smb_addr, 5) >> 3) & 7) + 12; |
| 320 | config->channel[cur].cols = (smbus_read_byte(smb_addr, 5) & 7) + 9; |
| 321 | |
| 322 | config->channel[cur].chip_capacity = smbus_read_byte(smb_addr, 4) & 0xf; |
| 323 | |
| 324 | config->channel[cur].banks = 8; /* GM45 only accepts this for DDR3. |
| 325 | verify_ddr3() fails for other values. */ |
| 326 | config->channel[cur].ranks = ((smbus_read_byte(smb_addr, 7) >> 3) & 7) + 1; |
| 327 | |
| 328 | config->channel[cur].cas_latencies = |
| 329 | ((smbus_read_byte(smb_addr, 15) << 8) | smbus_read_byte(smb_addr, 14)) |
| 330 | << 4; /* so bit x is CAS x */ |
| 331 | config->channel[cur].tAAmin = smbus_read_byte(smb_addr, 16); /* in MTB */ |
| 332 | config->channel[cur].tCKmin = smbus_read_byte(smb_addr, 12); /* in MTB */ |
| 333 | |
| 334 | config->channel[cur].width = smbus_read_byte(smb_addr, 7) & 7; |
| 335 | config->channel[cur].page_size = config->channel[cur].width * |
| 336 | (1 << config->channel[cur].cols); /* in Bytes */ |
| 337 | |
| 338 | tmp = smbus_read_byte(smb_addr, 21); |
| 339 | config->channel[cur].tRAS = smbus_read_byte(smb_addr, 22) | ((tmp & 0xf) << 8); |
| 340 | config->channel[cur].tRP = smbus_read_byte(smb_addr, 20); |
| 341 | config->channel[cur].tRCD = smbus_read_byte(smb_addr, 18); |
| 342 | config->channel[cur].tWR = smbus_read_byte(smb_addr, 17); |
| 343 | |
| 344 | config->channel[cur].raw_card = smbus_read_byte(smb_addr, 62) & 0x1f; |
| 345 | } |
| 346 | cur++; |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 347 | mask >>= 2; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 348 | } |
| 349 | } |
| 350 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 351 | static fsb_clock_t read_fsb_clock(void) |
| 352 | { |
| 353 | switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) { |
| 354 | case 6: |
| 355 | return FSB_CLOCK_1067MHz; |
| 356 | case 2: |
| 357 | return FSB_CLOCK_800MHz; |
| 358 | case 3: |
| 359 | return FSB_CLOCK_667MHz; |
| 360 | default: |
| 361 | die("Unsupported FSB clock.\n"); |
| 362 | } |
| 363 | } |
| 364 | static mem_clock_t clock_index(const unsigned int clock) |
| 365 | { |
| 366 | switch (clock) { |
| 367 | case 533: return MEM_CLOCK_533MHz; |
| 368 | case 400: return MEM_CLOCK_400MHz; |
| 369 | case 333: return MEM_CLOCK_333MHz; |
| 370 | default: die("Unknown clock value.\n"); |
| 371 | } |
| 372 | return -1; /* Won't be reached. */ |
| 373 | } |
| 374 | static void normalize_clock(unsigned int *const clock) |
| 375 | { |
| 376 | if (*clock >= 533) |
| 377 | *clock = 533; |
| 378 | else if (*clock >= 400) |
| 379 | *clock = 400; |
| 380 | else if (*clock >= 333) |
| 381 | *clock = 333; |
| 382 | else |
| 383 | *clock = 0; |
| 384 | } |
| 385 | static void lower_clock(unsigned int *const clock) |
| 386 | { |
| 387 | --*clock; |
| 388 | normalize_clock(clock); |
| 389 | } |
| 390 | static unsigned int find_common_clock_cas(sysinfo_t *const sysinfo, |
| 391 | const spdinfo_t *const spdinfo) |
| 392 | { |
| 393 | /* various constraints must be fulfilled: |
| 394 | CAS * tCK < 20ns == 160MTB |
| 395 | tCK_max >= tCK >= tCK_min |
| 396 | CAS >= roundup(tAA_min/tCK) |
| 397 | CAS supported |
| 398 | Clock(MHz) = 1000 / tCK(ns) |
| 399 | Clock(MHz) = 8000 / tCK(MTB) |
| 400 | AND BTW: Clock(MT) = 2000 / tCK(ns) - intel uses MTs but calls them MHz |
| 401 | */ |
| 402 | int i; |
| 403 | |
| 404 | /* Calculate common cas_latencies mask, tCKmin and tAAmin. */ |
| 405 | unsigned int cas_latencies = (unsigned int)-1; |
| 406 | unsigned int tCKmin = 0, tAAmin = 0; |
| 407 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 408 | cas_latencies &= spdinfo->channel[i].cas_latencies; |
| 409 | if (spdinfo->channel[i].tCKmin > tCKmin) |
| 410 | tCKmin = spdinfo->channel[i].tCKmin; |
| 411 | if (spdinfo->channel[i].tAAmin > tAAmin) |
| 412 | tAAmin = spdinfo->channel[i].tAAmin; |
| 413 | } |
| 414 | |
| 415 | /* Get actual value of fsb clock. */ |
| 416 | sysinfo->selected_timings.fsb_clock = read_fsb_clock(); |
| 417 | unsigned int fsb_mhz = 0; |
| 418 | switch (sysinfo->selected_timings.fsb_clock) { |
| 419 | case FSB_CLOCK_1067MHz: fsb_mhz = 1067; break; |
| 420 | case FSB_CLOCK_800MHz: fsb_mhz = 800; break; |
| 421 | case FSB_CLOCK_667MHz: fsb_mhz = 667; break; |
| 422 | } |
| 423 | |
| 424 | unsigned int clock = 8000 / tCKmin; |
| 425 | if ((clock > sysinfo->max_ddr3_mt / 2) || (clock > fsb_mhz / 2)) { |
Elyes HAOUAS | ba9b504 | 2019-12-19 07:47:52 +0100 | [diff] [blame] | 426 | int new_clock = MIN(sysinfo->max_ddr3_mt / 2, fsb_mhz / 2); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 427 | printk(BIOS_SPEW, "DIMMs support %d MHz, but chipset only runs at up to %d. Limiting...\n", |
| 428 | clock, new_clock); |
| 429 | clock = new_clock; |
| 430 | } |
| 431 | normalize_clock(&clock); |
| 432 | |
| 433 | /* Find compatible clock / CAS pair. */ |
| 434 | unsigned int tCKproposed; |
| 435 | unsigned int CAS; |
| 436 | while (1) { |
| 437 | if (!clock) |
| 438 | die("Couldn't find compatible clock / CAS settings.\n"); |
| 439 | tCKproposed = 8000 / clock; |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 440 | CAS = DIV_ROUND_UP(tAAmin, tCKproposed); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 441 | printk(BIOS_SPEW, "Trying CAS %u, tCK %u.\n", CAS, tCKproposed); |
| 442 | for (; CAS <= DDR3_MAX_CAS; ++CAS) |
| 443 | if (cas_latencies & (1 << CAS)) |
| 444 | break; |
| 445 | if ((CAS <= DDR3_MAX_CAS) && (CAS * tCKproposed < 160)) { |
| 446 | /* Found good CAS. */ |
| 447 | printk(BIOS_SPEW, "Found compatible clock / CAS pair: %u / %u.\n", clock, CAS); |
| 448 | break; |
| 449 | } |
| 450 | lower_clock(&clock); |
| 451 | } |
| 452 | sysinfo->selected_timings.CAS = CAS; |
| 453 | sysinfo->selected_timings.mem_clock = clock_index(clock); |
| 454 | |
| 455 | return tCKproposed; |
| 456 | } |
| 457 | |
| 458 | static void calculate_derived_timings(sysinfo_t *const sysinfo, |
| 459 | const unsigned int tCLK, |
| 460 | const spdinfo_t *const spdinfo) |
| 461 | { |
| 462 | int i; |
| 463 | |
| 464 | /* Calculate common tRASmin, tRPmin, tRCDmin and tWRmin. */ |
| 465 | unsigned int tRASmin = 0, tRPmin = 0, tRCDmin = 0, tWRmin = 0; |
| 466 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 467 | if (spdinfo->channel[i].tRAS > tRASmin) |
| 468 | tRASmin = spdinfo->channel[i].tRAS; |
| 469 | if (spdinfo->channel[i].tRP > tRPmin) |
| 470 | tRPmin = spdinfo->channel[i].tRP; |
| 471 | if (spdinfo->channel[i].tRCD > tRCDmin) |
| 472 | tRCDmin = spdinfo->channel[i].tRCD; |
| 473 | if (spdinfo->channel[i].tWR > tWRmin) |
| 474 | tWRmin = spdinfo->channel[i].tWR; |
| 475 | } |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 476 | tRASmin = DIV_ROUND_UP(tRASmin, tCLK); |
| 477 | tRPmin = DIV_ROUND_UP(tRPmin, tCLK); |
| 478 | tRCDmin = DIV_ROUND_UP(tRCDmin, tCLK); |
| 479 | tWRmin = DIV_ROUND_UP(tWRmin, tCLK); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 480 | |
| 481 | /* Lookup tRFC and calculate common tRFCmin. */ |
| 482 | const unsigned int tRFC_from_clock_and_cap[][4] = { |
| 483 | /* CAP_256M CAP_512M CAP_1G CAP_2G */ |
| 484 | /* 533MHz */ { 40, 56, 68, 104 }, |
| 485 | /* 400MHz */ { 30, 42, 51, 78 }, |
| 486 | /* 333MHz */ { 25, 35, 43, 65 }, |
| 487 | }; |
| 488 | unsigned int tRFCmin = 0; |
| 489 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 490 | const unsigned int tRFC = tRFC_from_clock_and_cap |
| 491 | [sysinfo->selected_timings.mem_clock][spdinfo->channel[i].chip_capacity]; |
| 492 | if (tRFC > tRFCmin) |
| 493 | tRFCmin = tRFC; |
| 494 | } |
| 495 | |
| 496 | /* Calculate common tRD from CAS and FSB and DRAM clocks. */ |
| 497 | unsigned int tRDmin = sysinfo->selected_timings.CAS; |
| 498 | switch (sysinfo->selected_timings.fsb_clock) { |
| 499 | case FSB_CLOCK_667MHz: |
| 500 | tRDmin += 1; |
| 501 | break; |
| 502 | case FSB_CLOCK_800MHz: |
| 503 | tRDmin += 2; |
| 504 | break; |
| 505 | case FSB_CLOCK_1067MHz: |
| 506 | tRDmin += 3; |
| 507 | if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) |
| 508 | tRDmin += 1; |
| 509 | break; |
| 510 | } |
| 511 | |
| 512 | /* Calculate common tRRDmin. */ |
| 513 | unsigned int tRRDmin = 0; |
| 514 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 515 | unsigned int tRRD = 2 + (spdinfo->channel[i].page_size / 1024); |
| 516 | if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) |
| 517 | tRRD += (spdinfo->channel[i].page_size / 1024); |
| 518 | if (tRRD > tRRDmin) |
| 519 | tRRDmin = tRRD; |
| 520 | } |
| 521 | |
| 522 | /* Lookup and calculate common tFAWmin. */ |
| 523 | unsigned int tFAW_from_pagesize_and_clock[][3] = { |
| 524 | /* 533MHz 400MHz 333MHz */ |
| 525 | /* 1K */ { 20, 15, 13 }, |
| 526 | /* 2K */ { 27, 20, 17 }, |
| 527 | }; |
| 528 | unsigned int tFAWmin = 0; |
| 529 | FOR_EACH_POPULATED_CHANNEL(sysinfo->dimms, i) { |
| 530 | const unsigned int tFAW = tFAW_from_pagesize_and_clock |
| 531 | [spdinfo->channel[i].page_size / 1024 - 1] |
| 532 | [sysinfo->selected_timings.mem_clock]; |
| 533 | if (tFAW > tFAWmin) |
| 534 | tFAWmin = tFAW; |
| 535 | } |
| 536 | |
| 537 | /* Refresh rate is fixed. */ |
| 538 | unsigned int tWL; |
| 539 | if (sysinfo->selected_timings.mem_clock == MEM_CLOCK_1067MT) { |
| 540 | tWL = 6; |
| 541 | } else { |
| 542 | tWL = 5; |
| 543 | } |
| 544 | |
| 545 | printk(BIOS_SPEW, "Timing values:\n" |
| 546 | " tCLK: %3u\n" |
| 547 | " tRAS: %3u\n" |
| 548 | " tRP: %3u\n" |
| 549 | " tRCD: %3u\n" |
| 550 | " tRFC: %3u\n" |
| 551 | " tWR: %3u\n" |
| 552 | " tRD: %3u\n" |
| 553 | " tRRD: %3u\n" |
| 554 | " tFAW: %3u\n" |
| 555 | " tWL: %3u\n", |
| 556 | tCLK, tRASmin, tRPmin, tRCDmin, tRFCmin, tWRmin, tRDmin, tRRDmin, tFAWmin, tWL); |
| 557 | |
| 558 | sysinfo->selected_timings.tRAS = tRASmin; |
| 559 | sysinfo->selected_timings.tRP = tRPmin; |
| 560 | sysinfo->selected_timings.tRCD = tRCDmin; |
| 561 | sysinfo->selected_timings.tRFC = tRFCmin; |
| 562 | sysinfo->selected_timings.tWR = tWRmin; |
| 563 | sysinfo->selected_timings.tRD = tRDmin; |
| 564 | sysinfo->selected_timings.tRRD = tRRDmin; |
| 565 | sysinfo->selected_timings.tFAW = tFAWmin; |
| 566 | sysinfo->selected_timings.tWL = tWL; |
| 567 | } |
| 568 | |
| 569 | static void collect_dimm_config(sysinfo_t *const sysinfo) |
| 570 | { |
| 571 | int i; |
| 572 | spdinfo_t spdinfo; |
| 573 | |
| 574 | spdinfo.dimm_mask = 0; |
| 575 | sysinfo->spd_type = 0; |
| 576 | |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 577 | for (i = 0; i < 4; i++) |
| 578 | if (sysinfo->spd_map[i]) { |
| 579 | const u8 spd = smbus_read_byte(sysinfo->spd_map[i], 2); |
| 580 | printk (BIOS_DEBUG, "%x:%x:%x\n", |
| 581 | i, sysinfo->spd_map[i], |
| 582 | spd); |
| 583 | if ((spd == 7) || (spd == 8) || (spd == 0xb)) { |
| 584 | spdinfo.dimm_mask |= 1 << i; |
| 585 | if (sysinfo->spd_type && sysinfo->spd_type != spd) { |
| 586 | die("Multiple types of DIMM installed in the system, don't do that!\n"); |
| 587 | } |
| 588 | sysinfo->spd_type = spd; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 589 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 590 | } |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 591 | if (spdinfo.dimm_mask == 0) { |
| 592 | die("Could not find any DIMM.\n"); |
| 593 | } |
| 594 | |
| 595 | /* Normalize spd_type to 1, 2, 3. */ |
| 596 | sysinfo->spd_type = (sysinfo->spd_type & 1) | ((sysinfo->spd_type & 8) >> 2); |
| 597 | printk(BIOS_SPEW, "DDR mask %x, DDR %d\n", spdinfo.dimm_mask, sysinfo->spd_type); |
| 598 | |
| 599 | if (sysinfo->spd_type == DDR2) { |
| 600 | die("DDR2 not supported at this time.\n"); |
| 601 | } else if (sysinfo->spd_type == DDR3) { |
Vladimir Serbinenko | c4d8948 | 2014-06-05 09:14:48 +0200 | [diff] [blame] | 602 | verify_ddr3(sysinfo, spdinfo.dimm_mask); |
| 603 | collect_ddr3(sysinfo, &spdinfo); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 604 | } else { |
| 605 | die("Will never support DDR1.\n"); |
| 606 | } |
| 607 | |
| 608 | for (i = 0; i < 2; i++) { |
| 609 | if ((spdinfo.dimm_mask >> (i*2)) & 1) { |
| 610 | printk(BIOS_SPEW, "Bank %d populated:\n" |
| 611 | " Raw card type: %4c\n" |
| 612 | " Row addr bits: %4u\n" |
| 613 | " Col addr bits: %4u\n" |
| 614 | " byte width: %4u\n" |
| 615 | " page size: %4u\n" |
| 616 | " banks: %4u\n" |
| 617 | " ranks: %4u\n" |
| 618 | " tAAmin: %3u\n" |
| 619 | " tCKmin: %3u\n" |
| 620 | " Max clock: %3u MHz\n" |
| 621 | " CAS: 0x%04x\n", |
| 622 | i, spdinfo.channel[i].raw_card + 'A', |
| 623 | spdinfo.channel[i].rows, spdinfo.channel[i].cols, |
| 624 | spdinfo.channel[i].width, spdinfo.channel[i].page_size, |
| 625 | spdinfo.channel[i].banks, spdinfo.channel[i].ranks, |
| 626 | spdinfo.channel[i].tAAmin, spdinfo.channel[i].tCKmin, |
| 627 | 8000 / spdinfo.channel[i].tCKmin, spdinfo.channel[i].cas_latencies); |
| 628 | } |
| 629 | } |
| 630 | |
| 631 | FOR_EACH_CHANNEL(i) { |
| 632 | sysinfo->dimms[i].card_type = |
| 633 | (spdinfo.dimm_mask & (1 << (i * 2))) ? spdinfo.channel[i].raw_card + 0xa : 0; |
| 634 | } |
| 635 | |
| 636 | /* Find common memory clock and CAS. */ |
| 637 | const unsigned int tCLK = find_common_clock_cas(sysinfo, &spdinfo); |
| 638 | |
| 639 | /* Calculate other timings from clock and CAS. */ |
| 640 | calculate_derived_timings(sysinfo, tCLK, &spdinfo); |
| 641 | |
| 642 | /* Initialize DIMM infos. */ |
| 643 | /* Always prefer interleaved over async channel mode. */ |
| 644 | FOR_EACH_CHANNEL(i) { |
| 645 | IF_CHANNEL_POPULATED(sysinfo->dimms, i) { |
| 646 | sysinfo->dimms[i].banks = spdinfo.channel[i].banks; |
| 647 | sysinfo->dimms[i].ranks = spdinfo.channel[i].ranks; |
| 648 | |
| 649 | /* .width is 1 for x8 or 2 for x16, bus width is 8 bytes. */ |
| 650 | const unsigned int chips_per_rank = 8 / spdinfo.channel[i].width; |
| 651 | |
| 652 | sysinfo->dimms[i].chip_width = spdinfo.channel[i].width; |
| 653 | sysinfo->dimms[i].chip_capacity = spdinfo.channel[i].chip_capacity; |
| 654 | sysinfo->dimms[i].page_size = spdinfo.channel[i].page_size * chips_per_rank; |
| 655 | sysinfo->dimms[i].rank_capacity_mb = |
| 656 | /* offset of chip_capacity is 8 (256M), therefore, add 8 |
| 657 | chip_capacity is in Mbit, we want MByte, therefore, subtract 3 */ |
| 658 | (1 << (spdinfo.channel[i].chip_capacity + 8 - 3)) * chips_per_rank; |
| 659 | } |
| 660 | } |
| 661 | if (CHANNEL_IS_POPULATED(sysinfo->dimms, 0) && |
| 662 | CHANNEL_IS_POPULATED(sysinfo->dimms, 1)) |
| 663 | sysinfo->selected_timings.channel_mode = CHANNEL_MODE_DUAL_INTERLEAVED; |
| 664 | else |
| 665 | sysinfo->selected_timings.channel_mode = CHANNEL_MODE_SINGLE; |
| 666 | } |
| 667 | |
| 668 | static void reset_on_bad_warmboot(void) |
| 669 | { |
| 670 | /* Check self refresh channel status. */ |
| 671 | const u32 reg = MCHBAR32(PMSTS_MCHBAR); |
| 672 | /* Clear status bits. R/WC */ |
| 673 | MCHBAR32(PMSTS_MCHBAR) = reg; |
| 674 | if ((reg & PMSTS_WARM_RESET) && !(reg & PMSTS_BOTH_SELFREFRESH)) { |
| 675 | printk(BIOS_INFO, "DRAM was not in self refresh " |
| 676 | "during warm boot, reset required.\n"); |
| 677 | gm45_early_reset(); |
| 678 | } |
| 679 | } |
| 680 | |
| 681 | static void set_system_memory_frequency(const timings_t *const timings) |
| 682 | { |
| 683 | MCHBAR16(CLKCFG_MCHBAR + 0x60) &= ~(1 << 15); |
| 684 | MCHBAR16(CLKCFG_MCHBAR + 0x48) &= ~(1 << 15); |
| 685 | |
| 686 | /* Calculate wanted frequency setting. */ |
| 687 | const int want_freq = 6 - timings->mem_clock; |
| 688 | |
| 689 | /* Read current memory frequency. */ |
| 690 | const u32 clkcfg = MCHBAR32(CLKCFG_MCHBAR); |
| 691 | int cur_freq = (clkcfg & CLKCFG_MEMCLK_MASK) >> CLKCFG_MEMCLK_SHIFT; |
| 692 | if (0 == cur_freq) { |
| 693 | /* Try memory frequency from scratchpad. */ |
| 694 | printk(BIOS_DEBUG, "Reading current memory frequency from scratchpad.\n"); |
| 695 | cur_freq = (MCHBAR16(SSKPD_MCHBAR) & SSKPD_CLK_MASK) >> SSKPD_CLK_SHIFT; |
| 696 | } |
| 697 | |
| 698 | if (cur_freq != want_freq) { |
| 699 | printk(BIOS_DEBUG, "Changing memory frequency: old %x, new %x.\n", cur_freq, want_freq); |
| 700 | /* When writing new frequency setting, reset, then set update bit. */ |
| 701 | MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(CLKCFG_UPDATE | CLKCFG_MEMCLK_MASK)) | |
| 702 | (want_freq << CLKCFG_MEMCLK_SHIFT); |
| 703 | MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~CLKCFG_MEMCLK_MASK) | |
| 704 | (want_freq << CLKCFG_MEMCLK_SHIFT) | CLKCFG_UPDATE; |
| 705 | /* Reset update bit. */ |
| 706 | MCHBAR32(CLKCFG_MCHBAR) &= ~CLKCFG_UPDATE; |
| 707 | } |
| 708 | |
| 709 | if ((timings->fsb_clock == FSB_CLOCK_1067MHz) && (timings->mem_clock == MEM_CLOCK_667MT)) { |
| 710 | MCHBAR32(CLKCFG_MCHBAR + 0x16) = 0x000030f0; |
| 711 | MCHBAR32(CLKCFG_MCHBAR + 0x64) = 0x000050c1; |
| 712 | |
| 713 | MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 12)) | (1 << 17); |
| 714 | MCHBAR32(CLKCFG_MCHBAR) |= (1 << 17) | (1 << 12); |
| 715 | MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 12); |
| 716 | |
| 717 | MCHBAR32(CLKCFG_MCHBAR + 0x04) = 0x9bad1f1f; |
| 718 | MCHBAR8(CLKCFG_MCHBAR + 0x08) = 0xf4; |
| 719 | MCHBAR8(CLKCFG_MCHBAR + 0x0a) = 0x43; |
| 720 | MCHBAR8(CLKCFG_MCHBAR + 0x0c) = 0x10; |
| 721 | MCHBAR8(CLKCFG_MCHBAR + 0x0d) = 0x80; |
| 722 | MCHBAR32(CLKCFG_MCHBAR + 0x50) = 0x0b0e151b; |
| 723 | MCHBAR8(CLKCFG_MCHBAR + 0x54) = 0xb4; |
| 724 | MCHBAR8(CLKCFG_MCHBAR + 0x55) = 0x10; |
| 725 | MCHBAR8(CLKCFG_MCHBAR + 0x56) = 0x08; |
| 726 | |
| 727 | MCHBAR32(CLKCFG_MCHBAR) |= (1 << 10); |
| 728 | MCHBAR32(CLKCFG_MCHBAR) |= (1 << 11); |
| 729 | MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 10); |
| 730 | MCHBAR32(CLKCFG_MCHBAR) &= ~(1 << 11); |
| 731 | } |
| 732 | |
| 733 | MCHBAR32(CLKCFG_MCHBAR + 0x48) |= 0x3f << 24; |
| 734 | } |
| 735 | |
| 736 | int raminit_read_vco_index(void) |
| 737 | { |
Nico Huber | d85a71a | 2016-11-27 14:43:12 +0100 | [diff] [blame] | 738 | switch (MCHBAR8(HPLLVCO_MCHBAR) & 0x7) { |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 739 | case VCO_2666: |
| 740 | return 0; |
| 741 | case VCO_3200: |
| 742 | return 1; |
| 743 | case VCO_4000: |
| 744 | return 2; |
| 745 | case VCO_5333: |
| 746 | return 3; |
| 747 | default: |
| 748 | die("Unknown VCO frequency.\n"); |
| 749 | return 0; |
| 750 | } |
| 751 | } |
| 752 | static void set_igd_memory_frequencies(const sysinfo_t *const sysinfo) |
| 753 | { |
| 754 | const int gfx_idx = ((sysinfo->gfx_type == GMCH_GS45) && |
| 755 | !sysinfo->gs45_low_power_mode) |
| 756 | ? (GMCH_GS45 + 1) : sysinfo->gfx_type; |
| 757 | |
| 758 | /* Render and sampler frequency values seem to be some kind of factor. */ |
| 759 | const u16 render_freq_from_vco_and_gfxtype[][10] = { |
| 760 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 761 | /* VCO 2666 */ { 0xd, 0xd, 0xe, 0xd, 0xb, 0xd, 0xb, 0xa, 0xd }, |
| 762 | /* VCO 3200 */ { 0xd, 0xe, 0xf, 0xd, 0xb, 0xd, 0xb, 0x9, 0xd }, |
| 763 | /* VCO 4000 */ { 0xc, 0xd, 0xf, 0xc, 0xa, 0xc, 0xa, 0x9, 0xc }, |
| 764 | /* VCO 5333 */ { 0xb, 0xc, 0xe, 0xb, 0x9, 0xb, 0x9, 0x8, 0xb }, |
| 765 | }; |
| 766 | const u16 sampler_freq_from_vco_and_gfxtype[][10] = { |
| 767 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 768 | /* VCO 2666 */ { 0xc, 0xc, 0xd, 0xc, 0x9, 0xc, 0x9, 0x8, 0xc }, |
| 769 | /* VCO 3200 */ { 0xc, 0xd, 0xe, 0xc, 0x9, 0xc, 0x9, 0x8, 0xc }, |
| 770 | /* VCO 4000 */ { 0xa, 0xc, 0xd, 0xa, 0x8, 0xa, 0x8, 0x8, 0xa }, |
| 771 | /* VCO 5333 */ { 0xa, 0xa, 0xc, 0xa, 0x7, 0xa, 0x7, 0x6, 0xa }, |
| 772 | }; |
| 773 | const u16 display_clock_select_from_gfxtype[] = { |
| 774 | /* GM45 GM47 GM49 GE45 GL40 GL43 GS40 GS45 (perf) */ |
| 775 | 1, 1, 1, 1, 1, 1, 1, 0, 1 |
| 776 | }; |
| 777 | |
| 778 | if (pci_read_config16(GCFGC_PCIDEV, 0) != 0x8086) { |
| 779 | printk(BIOS_DEBUG, "Skipping IGD memory frequency setting.\n"); |
| 780 | return; |
| 781 | } |
| 782 | |
| 783 | MCHBAR16(0x119e) = 0xa800; |
| 784 | MCHBAR16(0x11c0) = (MCHBAR16(0x11c0) & ~0xff00) | (0x01 << 8); |
| 785 | MCHBAR16(0x119e) = 0xb800; |
| 786 | MCHBAR8(0x0f10) |= 1 << 7; |
| 787 | |
| 788 | /* Read VCO. */ |
| 789 | const int vco_idx = raminit_read_vco_index(); |
| 790 | printk(BIOS_DEBUG, "Setting IGD memory frequencies for VCO #%d.\n", vco_idx); |
| 791 | |
| 792 | const u32 freqcfg = |
| 793 | ((render_freq_from_vco_and_gfxtype[vco_idx][gfx_idx] |
| 794 | << GCFGC_CR_SHIFT) & GCFGC_CR_MASK) | |
| 795 | ((sampler_freq_from_vco_and_gfxtype[vco_idx][gfx_idx] |
| 796 | << GCFGC_CS_SHIFT) & GCFGC_CS_MASK); |
| 797 | |
| 798 | /* Set frequencies, clear update bit. */ |
| 799 | u32 gcfgc = pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET); |
| 800 | gcfgc &= ~(GCFGC_CS_MASK | GCFGC_UPDATE | GCFGC_CR_MASK); |
| 801 | gcfgc |= freqcfg; |
| 802 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc); |
| 803 | |
| 804 | /* Set frequencies, set update bit. */ |
| 805 | gcfgc = pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET); |
| 806 | gcfgc &= ~(GCFGC_CS_MASK | GCFGC_CR_MASK); |
| 807 | gcfgc |= freqcfg | GCFGC_UPDATE; |
| 808 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, gcfgc); |
| 809 | |
| 810 | /* Clear update bit. */ |
| 811 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, |
| 812 | pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_UPDATE); |
| 813 | |
| 814 | /* Set display clock select bit. */ |
| 815 | pci_write_config16(GCFGC_PCIDEV, GCFGC_OFFSET, |
| 816 | (pci_read_config16(GCFGC_PCIDEV, GCFGC_OFFSET) & ~GCFGC_CD_MASK) | |
| 817 | (display_clock_select_from_gfxtype[gfx_idx] << GCFGC_CD_SHIFT)); |
| 818 | } |
| 819 | |
| 820 | static void configure_dram_control_mode(const timings_t *const timings, const dimminfo_t *const dimms) |
| 821 | { |
| 822 | int ch, r; |
| 823 | |
| 824 | FOR_EACH_CHANNEL(ch) { |
| 825 | unsigned int mchbar = CxDRC0_MCHBAR(ch); |
| 826 | u32 cxdrc = MCHBAR32(mchbar); |
| 827 | cxdrc &= ~CxDRC0_RANKEN_MASK; |
| 828 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 829 | cxdrc |= CxDRC0_RANKEN(r); |
| 830 | cxdrc = (cxdrc & ~CxDRC0_RMS_MASK) | |
| 831 | /* Always 7.8us for DDR3: */ |
| 832 | CxDRC0_RMS_78US; |
| 833 | MCHBAR32(mchbar) = cxdrc; |
| 834 | |
| 835 | mchbar = CxDRC1_MCHBAR(ch); |
| 836 | cxdrc = MCHBAR32(mchbar); |
| 837 | cxdrc |= CxDRC1_NOTPOP_MASK; |
| 838 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 839 | cxdrc &= ~CxDRC1_NOTPOP(r); |
| 840 | cxdrc |= CxDRC1_MUSTWR; |
| 841 | MCHBAR32(mchbar) = cxdrc; |
| 842 | |
| 843 | mchbar = CxDRC2_MCHBAR(ch); |
| 844 | cxdrc = MCHBAR32(mchbar); |
| 845 | cxdrc |= CxDRC2_NOTPOP_MASK; |
| 846 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) |
| 847 | cxdrc &= ~CxDRC2_NOTPOP(r); |
| 848 | cxdrc |= CxDRC2_MUSTWR; |
| 849 | if (timings->mem_clock == MEM_CLOCK_1067MT) |
| 850 | cxdrc |= CxDRC2_CLK1067MT; |
| 851 | MCHBAR32(mchbar) = cxdrc; |
| 852 | } |
| 853 | } |
| 854 | |
| 855 | static void rcomp_initialization(const stepping_t stepping, const int sff) |
| 856 | { |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 857 | /* Program RCOMP codes. */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 858 | if (sff) |
| 859 | die("SFF platform unsupported in RCOMP initialization.\n"); |
| 860 | /* Values are for DDR3. */ |
| 861 | MCHBAR8(0x6ac) &= ~0x0f; |
| 862 | MCHBAR8(0x6b0) = 0x55; |
| 863 | MCHBAR8(0x6ec) &= ~0x0f; |
| 864 | MCHBAR8(0x6f0) = 0x66; |
| 865 | MCHBAR8(0x72c) &= ~0x0f; |
| 866 | MCHBAR8(0x730) = 0x66; |
| 867 | MCHBAR8(0x76c) &= ~0x0f; |
| 868 | MCHBAR8(0x770) = 0x66; |
| 869 | MCHBAR8(0x7ac) &= ~0x0f; |
| 870 | MCHBAR8(0x7b0) = 0x66; |
| 871 | MCHBAR8(0x7ec) &= ~0x0f; |
| 872 | MCHBAR8(0x7f0) = 0x66; |
| 873 | MCHBAR8(0x86c) &= ~0x0f; |
| 874 | MCHBAR8(0x870) = 0x55; |
| 875 | MCHBAR8(0x8ac) &= ~0x0f; |
| 876 | MCHBAR8(0x8b0) = 0x66; |
| 877 | /* ODT multiplier bits. */ |
| 878 | MCHBAR32(0x04d0) = (MCHBAR32(0x04d0) & ~((7 << 3) | (7 << 0))) | (2 << 3) | (2 << 0); |
| 879 | |
| 880 | /* Perform RCOMP calibration for DDR3. */ |
| 881 | raminit_rcomp_calibration(stepping); |
| 882 | |
| 883 | /* Run initial RCOMP. */ |
| 884 | MCHBAR32(0x418) |= 1 << 17; |
| 885 | MCHBAR32(0x40c) &= ~(1 << 23); |
| 886 | MCHBAR32(0x41c) &= ~((1 << 7) | (1 << 3)); |
| 887 | MCHBAR32(0x400) |= 1; |
| 888 | while (MCHBAR32(0x400) & 1) {} |
| 889 | |
| 890 | /* Run second RCOMP. */ |
| 891 | MCHBAR32(0x40c) |= 1 << 19; |
| 892 | MCHBAR32(0x400) |= 1; |
| 893 | while (MCHBAR32(0x400) & 1) {} |
| 894 | |
| 895 | /* Cleanup and start periodic RCOMP. */ |
| 896 | MCHBAR32(0x40c) &= ~(1 << 19); |
| 897 | MCHBAR32(0x40c) |= 1 << 23; |
| 898 | MCHBAR32(0x418) &= ~(1 << 17); |
| 899 | MCHBAR32(0x41c) |= (1 << 7) | (1 << 3); |
| 900 | MCHBAR32(0x400) |= (1 << 1); |
| 901 | } |
| 902 | |
| 903 | static void dram_powerup(const int resume) |
| 904 | { |
Arthur Heymans | 10141c3 | 2016-10-27 00:31:41 +0200 | [diff] [blame] | 905 | udelay(200); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 906 | MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 3)) | (3 << 21); |
| 907 | if (!resume) { |
| 908 | MCHBAR32(0x1434) |= (1 << 10); |
Arthur Heymans | 10141c3 | 2016-10-27 00:31:41 +0200 | [diff] [blame] | 909 | udelay(1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 910 | } |
| 911 | MCHBAR32(0x1434) |= (1 << 6); |
| 912 | if (!resume) { |
Arthur Heymans | 10141c3 | 2016-10-27 00:31:41 +0200 | [diff] [blame] | 913 | udelay(1); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 914 | MCHBAR32(0x1434) |= (1 << 9); |
| 915 | MCHBAR32(0x1434) &= ~(1 << 10); |
| 916 | udelay(500); |
| 917 | } |
| 918 | } |
| 919 | static void dram_program_timings(const timings_t *const timings) |
| 920 | { |
| 921 | /* Values are for DDR3. */ |
| 922 | const int burst_length = 8; |
| 923 | const int tWTR = 4, tRTP = 1; |
| 924 | int i; |
| 925 | |
| 926 | FOR_EACH_CHANNEL(i) { |
| 927 | u32 reg = MCHBAR32(CxDRT0_MCHBAR(i)); |
| 928 | const int btb_wtp = timings->tWL + burst_length/2 + timings->tWR; |
| 929 | const int btb_wtr = timings->tWL + burst_length/2 + tWTR; |
| 930 | reg = (reg & ~(CxDRT0_BtB_WtP_MASK | CxDRT0_BtB_WtR_MASK)) | |
| 931 | ((btb_wtp << CxDRT0_BtB_WtP_SHIFT) & CxDRT0_BtB_WtP_MASK) | |
| 932 | ((btb_wtr << CxDRT0_BtB_WtR_SHIFT) & CxDRT0_BtB_WtR_MASK); |
| 933 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 934 | reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15); |
| 935 | reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10); |
| 936 | } else { |
| 937 | reg = (reg & ~(0x7 << 15)) | ((10 - timings->CAS) << 15); |
| 938 | reg = (reg & ~(0xf << 10)) | ((timings->CAS - 4) << 10); |
| 939 | } |
| 940 | reg = (reg & ~(0x7 << 5)) | (3 << 5); |
| 941 | reg = (reg & ~(0x7 << 0)) | (1 << 0); |
| 942 | MCHBAR32(CxDRT0_MCHBAR(i)) = reg; |
| 943 | |
| 944 | reg = MCHBAR32(CxDRT1_MCHBAR(i)); |
| 945 | reg = (reg & ~(0x03 << 28)) | ((tRTP & 0x03) << 28); |
| 946 | reg = (reg & ~(0x1f << 21)) | ((timings->tRAS & 0x1f) << 21); |
| 947 | reg = (reg & ~(0x07 << 10)) | (((timings->tRRD - 2) & 0x07) << 10); |
| 948 | reg = (reg & ~(0x07 << 5)) | (((timings->tRCD - 2) & 0x07) << 5); |
| 949 | reg = (reg & ~(0x07 << 0)) | (((timings->tRP - 2) & 0x07) << 0); |
| 950 | MCHBAR32(CxDRT1_MCHBAR(i)) = reg; |
| 951 | |
| 952 | reg = MCHBAR32(CxDRT2_MCHBAR(i)); |
| 953 | reg = (reg & ~(0x1f << 17)) | ((timings->tFAW & 0x1f) << 17); |
| 954 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 955 | reg = (reg & ~(0x7 << 12)) | (0x2 << 12); |
| 956 | reg = (reg & ~(0xf << 6)) | (0x9 << 6); |
| 957 | } else { |
| 958 | reg = (reg & ~(0x7 << 12)) | (0x3 << 12); |
| 959 | reg = (reg & ~(0xf << 6)) | (0xc << 6); |
| 960 | } |
| 961 | reg = (reg & ~(0x1f << 0)) | (0x13 << 0); |
| 962 | MCHBAR32(CxDRT2_MCHBAR(i)) = reg; |
| 963 | |
| 964 | reg = MCHBAR32(CxDRT3_MCHBAR(i)); |
| 965 | reg |= 0x3 << 28; |
| 966 | reg = (reg & ~(0x03 << 26)); |
| 967 | reg = (reg & ~(0x07 << 23)) | (((timings->CAS - 3) & 0x07) << 23); |
| 968 | reg = (reg & ~(0xff << 13)) | ((timings->tRFC & 0xff) << 13); |
| 969 | reg = (reg & ~(0x07 << 0)) | (((timings->tWL - 2) & 0x07) << 0); |
| 970 | MCHBAR32(CxDRT3_MCHBAR(i)) = reg; |
| 971 | |
| 972 | reg = MCHBAR32(CxDRT4_MCHBAR(i)); |
| 973 | static const u8 timings_by_clock[4][3] = { |
| 974 | /* 333MHz 400MHz 533MHz |
| 975 | 667MT 800MT 1067MT */ |
| 976 | { 0x07, 0x0a, 0x0d }, |
| 977 | { 0x3a, 0x46, 0x5d }, |
| 978 | { 0x0c, 0x0e, 0x18 }, |
| 979 | { 0x21, 0x28, 0x35 }, |
| 980 | }; |
| 981 | const int clk_idx = 2 - timings->mem_clock; |
| 982 | reg = (reg & ~(0x01f << 27)) | (timings_by_clock[0][clk_idx] << 27); |
| 983 | reg = (reg & ~(0x3ff << 17)) | (timings_by_clock[1][clk_idx] << 17); |
| 984 | reg = (reg & ~(0x03f << 10)) | (timings_by_clock[2][clk_idx] << 10); |
| 985 | reg = (reg & ~(0x1ff << 0)) | (timings_by_clock[3][clk_idx] << 0); |
| 986 | MCHBAR32(CxDRT4_MCHBAR(i)) = reg; |
| 987 | |
| 988 | reg = MCHBAR32(CxDRT5_MCHBAR(i)); |
| 989 | if (timings->mem_clock == MEM_CLOCK_1067MT) |
| 990 | reg = (reg & ~(0xf << 28)) | (0x8 << 28); |
| 991 | reg = (reg & ~(0x00f << 22)) | ((burst_length/2 + timings->CAS + 2) << 22); |
| 992 | reg = (reg & ~(0x3ff << 12)) | (0x190 << 12); |
| 993 | reg = (reg & ~(0x00f << 4)) | ((timings->CAS - 2) << 4); |
| 994 | reg = (reg & ~(0x003 << 2)) | (0x001 << 2); |
| 995 | reg = (reg & ~(0x003 << 0)); |
| 996 | MCHBAR32(CxDRT5_MCHBAR(i)) = reg; |
| 997 | |
| 998 | reg = MCHBAR32(CxDRT6_MCHBAR(i)); |
| 999 | reg = (reg & ~(0xffff << 16)) | (0x066a << 16); /* always 7.8us refresh rate for DDR3 */ |
| 1000 | reg |= (1 << 2); |
| 1001 | MCHBAR32(CxDRT6_MCHBAR(i)) = reg; |
| 1002 | } |
| 1003 | } |
| 1004 | |
| 1005 | static void dram_program_banks(const dimminfo_t *const dimms) |
| 1006 | { |
| 1007 | int ch, r; |
| 1008 | |
| 1009 | FOR_EACH_CHANNEL(ch) { |
| 1010 | const int tRPALL = dimms[ch].banks == 8; |
| 1011 | |
| 1012 | u32 reg = MCHBAR32(CxDRT1_MCHBAR(ch)) & ~(0x01 << 15); |
| 1013 | IF_CHANNEL_POPULATED(dimms, ch) |
| 1014 | reg |= tRPALL << 15; |
| 1015 | MCHBAR32(CxDRT1_MCHBAR(ch)) = reg; |
| 1016 | |
| 1017 | reg = MCHBAR32(CxDRA_MCHBAR(ch)) & ~CxDRA_BANKS_MASK; |
| 1018 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) { |
| 1019 | reg |= CxDRA_BANKS(r, dimms[ch].banks); |
| 1020 | } |
| 1021 | MCHBAR32(CxDRA_MCHBAR(ch)) = reg; |
| 1022 | } |
| 1023 | } |
| 1024 | |
| 1025 | static void odt_setup(const timings_t *const timings, const int sff) |
| 1026 | { |
| 1027 | /* Values are for DDR3. */ |
| 1028 | int ch; |
| 1029 | |
| 1030 | FOR_EACH_CHANNEL(ch) { |
| 1031 | u32 reg = MCHBAR32(CxODT_HIGH(ch)); |
| 1032 | if (sff && (timings->mem_clock != MEM_CLOCK_1067MT)) |
| 1033 | reg &= ~(0x3 << (61 - 32)); |
| 1034 | else |
| 1035 | reg |= 0x3 << (61 - 32); |
| 1036 | reg = (reg & ~(0x3 << (52 - 32))) | (0x2 << (52 - 32)); |
| 1037 | reg = (reg & ~(0x7 << (48 - 32))) | ((timings->CAS - 3) << (48 - 32)); |
| 1038 | reg = (reg & ~(0xf << (44 - 32))) | (0x7 << (44 - 32)); |
| 1039 | if (timings->mem_clock != MEM_CLOCK_1067MT) { |
| 1040 | reg = (reg & ~(0xf << (40 - 32))) | ((12 - timings->CAS) << (40 - 32)); |
| 1041 | reg = (reg & ~(0xf << (36 - 32))) | (( 2 + timings->CAS) << (36 - 32)); |
| 1042 | } else { |
| 1043 | reg = (reg & ~(0xf << (40 - 32))) | ((13 - timings->CAS) << (40 - 32)); |
| 1044 | reg = (reg & ~(0xf << (36 - 32))) | (( 1 + timings->CAS) << (36 - 32)); |
| 1045 | } |
| 1046 | reg = (reg & ~(0xf << (32 - 32))) | (0x7 << (32 - 32)); |
| 1047 | MCHBAR32(CxODT_HIGH(ch)) = reg; |
| 1048 | |
| 1049 | reg = MCHBAR32(CxODT_LOW(ch)); |
| 1050 | reg = (reg & ~(0x7 << 28)) | (0x2 << 28); |
| 1051 | reg = (reg & ~(0x3 << 22)) | (0x2 << 22); |
| 1052 | reg = (reg & ~(0x7 << 12)) | (0x2 << 12); |
| 1053 | reg = (reg & ~(0x7 << 4)) | (0x2 << 4); |
| 1054 | switch (timings->mem_clock) { |
| 1055 | case MEM_CLOCK_667MT: |
| 1056 | reg = (reg & ~0x7); |
| 1057 | break; |
| 1058 | case MEM_CLOCK_800MT: |
| 1059 | reg = (reg & ~0x7) | 0x2; |
| 1060 | break; |
| 1061 | case MEM_CLOCK_1067MT: |
| 1062 | reg = (reg & ~0x7) | 0x5; |
| 1063 | break; |
| 1064 | } |
| 1065 | MCHBAR32(CxODT_LOW(ch)) = reg; |
| 1066 | } |
| 1067 | } |
| 1068 | |
| 1069 | static void misc_settings(const timings_t *const timings, |
| 1070 | const stepping_t stepping) |
| 1071 | { |
| 1072 | MCHBAR32(0x1260) = (MCHBAR32(0x1260) & ~((1 << 24) | 0x1f)) | timings->tRD; |
| 1073 | MCHBAR32(0x1360) = (MCHBAR32(0x1360) & ~((1 << 24) | 0x1f)) | timings->tRD; |
| 1074 | |
| 1075 | MCHBAR8(0x1268) = (MCHBAR8(0x1268) & ~(0xf)) | timings->tWL; |
| 1076 | MCHBAR8(0x1368) = (MCHBAR8(0x1368) & ~(0xf)) | timings->tWL; |
| 1077 | MCHBAR8(0x12a0) = (MCHBAR8(0x12a0) & ~(0xf)) | 0xa; |
| 1078 | MCHBAR8(0x13a0) = (MCHBAR8(0x13a0) & ~(0xf)) | 0xa; |
| 1079 | |
| 1080 | MCHBAR32(0x218) = (MCHBAR32(0x218) & ~((7 << 29) | (7 << 25) | (3 << 22) | (3 << 10))) | |
| 1081 | (4 << 29) | (3 << 25) | (0 << 22) | (1 << 10); |
| 1082 | MCHBAR32(0x220) = (MCHBAR32(0x220) & ~(7 << 16)) | (1 << 21) | (1 << 16); |
| 1083 | MCHBAR32(0x224) = (MCHBAR32(0x224) & ~(7 << 8)) | (3 << 8); |
| 1084 | if (stepping >= STEPPING_B1) |
| 1085 | MCHBAR8(0x234) |= (1 << 3); |
| 1086 | } |
| 1087 | |
| 1088 | static void clock_crossing_setup(const fsb_clock_t fsb, |
| 1089 | const mem_clock_t ddr3clock, |
| 1090 | const dimminfo_t *const dimms) |
| 1091 | { |
| 1092 | int ch; |
| 1093 | |
| 1094 | static const u32 values_from_fsb_and_mem[][3][4] = { |
| 1095 | /* FSB 1067MHz */{ |
| 1096 | /* DDR3-1067 */ { 0x00000000, 0x00000000, 0x00180006, 0x00810060 }, |
| 1097 | /* DDR3-800 */ { 0x00000000, 0x00000000, 0x0000001c, 0x000300e0 }, |
| 1098 | /* DDR3-667 */ { 0x00000000, 0x00001c00, 0x03c00038, 0x0007e000 }, |
| 1099 | }, |
| 1100 | /* FSB 800MHz */{ |
| 1101 | /* DDR3-1067 */ { 0, 0, 0, 0 }, |
| 1102 | /* DDR3-800 */ { 0x00000000, 0x00000000, 0x0030000c, 0x000300c0 }, |
| 1103 | /* DDR3-667 */ { 0x00000000, 0x00000380, 0x0060001c, 0x00030c00 }, |
| 1104 | }, |
| 1105 | /* FSB 667MHz */{ |
| 1106 | /* DDR3-1067 */ { 0, 0, 0, 0 }, |
| 1107 | /* DDR3-800 */ { 0, 0, 0, 0 }, |
| 1108 | /* DDR3-667 */ { 0x00000000, 0x00000000, 0x0030000c, 0x000300c0 }, |
| 1109 | }, |
| 1110 | }; |
| 1111 | |
| 1112 | const u32 *data = values_from_fsb_and_mem[fsb][ddr3clock]; |
| 1113 | MCHBAR32(0x0208) = data[3]; |
| 1114 | MCHBAR32(0x020c) = data[2]; |
| 1115 | if (((fsb == FSB_CLOCK_1067MHz) || (fsb == FSB_CLOCK_800MHz)) && (ddr3clock == MEM_CLOCK_667MT)) |
| 1116 | MCHBAR32(0x0210) = data[1]; |
| 1117 | |
| 1118 | static const u32 from_fsb_and_mem[][3] = { |
| 1119 | /* DDR3-1067 DDR3-800 DDR3-667 */ |
| 1120 | /* FSB 1067MHz */{ 0x40100401, 0x10040220, 0x08040110, }, |
| 1121 | /* FSB 800MHz */{ 0x00000000, 0x40100401, 0x00080201, }, |
| 1122 | /* FSB 667MHz */{ 0x00000000, 0x00000000, 0x40100401, }, |
| 1123 | }; |
| 1124 | FOR_EACH_CHANNEL(ch) { |
| 1125 | const unsigned int mchbar = 0x1258 + (ch * 0x0100); |
| 1126 | if ((fsb == FSB_CLOCK_1067MHz) && (ddr3clock == MEM_CLOCK_800MT) && CHANNEL_IS_CARDF(dimms, ch)) |
| 1127 | MCHBAR32(mchbar) = 0x08040120; |
| 1128 | else |
| 1129 | MCHBAR32(mchbar) = from_fsb_and_mem[fsb][ddr3clock]; |
| 1130 | MCHBAR32(mchbar + 4) = 0x00000000; |
| 1131 | } |
| 1132 | } |
| 1133 | |
| 1134 | /* Program egress VC1 timings. */ |
| 1135 | static void vc1_program_timings(const fsb_clock_t fsb) |
| 1136 | { |
| 1137 | const u32 timings_by_fsb[][2] = { |
| 1138 | /* FSB 1067MHz */ { 0x1a, 0x01380138 }, |
| 1139 | /* FSB 800MHz */ { 0x14, 0x00f000f0 }, |
| 1140 | /* FSB 667MHz */ { 0x10, 0x00c000c0 }, |
| 1141 | }; |
| 1142 | EPBAR8(0x2c) = timings_by_fsb[fsb][0]; |
| 1143 | EPBAR32(0x38) = timings_by_fsb[fsb][1]; |
| 1144 | EPBAR32(0x3c) = timings_by_fsb[fsb][1]; |
| 1145 | } |
| 1146 | |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1147 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 1148 | #define HOST_BRIDGE PCI_DEVFN(0, 0) |
| 1149 | |
| 1150 | static unsigned int get_mmio_size(void) |
| 1151 | { |
| 1152 | const struct device *dev; |
| 1153 | const struct northbridge_intel_gm45_config *cfg = NULL; |
| 1154 | |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 1155 | dev = pcidev_path_on_root(HOST_BRIDGE); |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1156 | if (dev) |
| 1157 | cfg = dev->chip_info; |
| 1158 | |
| 1159 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 1160 | if (!cfg || cfg->pci_mmio_size == 0) |
| 1161 | return DEFAULT_PCI_MMIO_SIZE; |
| 1162 | else |
| 1163 | return cfg->pci_mmio_size; |
| 1164 | } |
| 1165 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1166 | /* @prejedec if not zero, set rank size to 128MB and page size to 4KB. */ |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1167 | static void program_memory_map(const dimminfo_t *const dimms, const channel_mode_t mode, const int prejedec, u16 ggc) |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1168 | { |
| 1169 | int ch, r; |
| 1170 | |
| 1171 | /* Program rank boundaries (CxDRBy). */ |
| 1172 | unsigned int base = 0; /* start of next rank in MB */ |
| 1173 | unsigned int total_mb[2] = { 0, 0 }; /* total memory per channel in MB */ |
| 1174 | FOR_EACH_CHANNEL(ch) { |
| 1175 | if (mode == CHANNEL_MODE_DUAL_INTERLEAVED) |
| 1176 | /* In interleaved mode, start every channel from 0. */ |
| 1177 | base = 0; |
| 1178 | for (r = 0; r < RANKS_PER_CHANNEL; r += 2) { |
| 1179 | /* Fixed capacity for pre-jedec config. */ |
| 1180 | const unsigned int rank_capacity_mb = |
| 1181 | prejedec ? 128 : dimms[ch].rank_capacity_mb; |
| 1182 | u32 reg = 0; |
| 1183 | |
| 1184 | /* Program bounds in CxDRBy. */ |
| 1185 | IF_RANK_POPULATED(dimms, ch, r) { |
| 1186 | base += rank_capacity_mb; |
| 1187 | total_mb[ch] += rank_capacity_mb; |
| 1188 | } |
| 1189 | reg |= CxDRBy_BOUND_MB(r, base); |
| 1190 | IF_RANK_POPULATED(dimms, ch, r+1) { |
| 1191 | base += rank_capacity_mb; |
| 1192 | total_mb[ch] += rank_capacity_mb; |
| 1193 | } |
| 1194 | reg |= CxDRBy_BOUND_MB(r+1, base); |
| 1195 | |
| 1196 | MCHBAR32(CxDRBy_MCHBAR(ch, r)) = reg; |
| 1197 | } |
| 1198 | } |
| 1199 | |
| 1200 | /* Program page size (CxDRA). */ |
| 1201 | FOR_EACH_CHANNEL(ch) { |
| 1202 | u32 reg = MCHBAR32(CxDRA_MCHBAR(ch)) & ~CxDRA_PAGESIZE_MASK; |
| 1203 | FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) { |
| 1204 | /* Fixed page size for pre-jedec config. */ |
| 1205 | const unsigned int page_size = /* dimm page size in bytes */ |
| 1206 | prejedec ? 4096 : dimms[ch].page_size; |
| 1207 | reg |= CxDRA_PAGESIZE(r, log2(page_size)); |
| 1208 | /* deferred to f5_27: reg |= CxDRA_BANKS(r, dimms[ch].banks); */ |
| 1209 | } |
| 1210 | MCHBAR32(CxDRA_MCHBAR(ch)) = reg; |
| 1211 | } |
| 1212 | |
| 1213 | /* Calculate memory mapping, all values in MB. */ |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1214 | |
| 1215 | u32 uma_sizem = 0; |
| 1216 | if (!prejedec) { |
| 1217 | if (!(ggc & 2)) { |
| 1218 | printk(BIOS_DEBUG, "IGD decoded, subtracting "); |
| 1219 | |
| 1220 | /* Graphics memory */ |
| 1221 | const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); |
| 1222 | printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); |
| 1223 | |
| 1224 | /* GTT Graphics Stolen Memory Size (GGMS) */ |
| 1225 | const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); |
| 1226 | printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); |
| 1227 | |
| 1228 | uma_sizem = (gms_sizek + gsm_sizek) >> 10; |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1229 | } |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1230 | /* TSEG 2M, This amount can easily be covered by SMRR MTRR's, |
| 1231 | which requires to have TSEG_BASE aligned to TSEG_SIZE. */ |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 1232 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC); |
| 1233 | reg8 &= ~0x7; |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1234 | reg8 |= (1 << 1) | (1 << 0); /* 2M and TSEG_Enable */ |
Arthur Heymans | 8b76605 | 2018-01-24 23:25:13 +0100 | [diff] [blame] | 1235 | pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8); |
Arthur Heymans | d522db0 | 2018-08-06 15:50:54 +0200 | [diff] [blame] | 1236 | uma_sizem += 2; |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1237 | } |
| 1238 | |
Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 1239 | const unsigned int mmio_size = get_mmio_size(); |
| 1240 | const unsigned int MMIOstart = 4096 - mmio_size + uma_sizem; |
Vladimir Serbinenko | 9907be4 | 2014-08-12 21:51:28 +0200 | [diff] [blame] | 1241 | const int me_active = pci_read_config8(PCI_DEV(0, 3, 0), PCI_CLASS_REVISION) != 0xff; |
| 1242 | const unsigned int ME_SIZE = prejedec || !me_active ? 0 : 32; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1243 | const unsigned int usedMEsize = (total_mb[0] != total_mb[1]) ? ME_SIZE : 2 * ME_SIZE; |
| 1244 | const unsigned int claimCapable = |
| 1245 | !(pci_read_config32(PCI_DEV(0, 0, 0), D0F0_CAPID0 + 4) & (1 << (47 - 32))); |
| 1246 | |
| 1247 | const unsigned int TOM = total_mb[0] + total_mb[1]; |
| 1248 | unsigned int TOMminusME = TOM - usedMEsize; |
| 1249 | unsigned int TOLUD = (TOMminusME < MMIOstart) ? TOMminusME : MMIOstart; |
| 1250 | unsigned int TOUUD = TOMminusME; |
| 1251 | unsigned int REMAPbase = 0xffff, REMAPlimit = 0; |
| 1252 | |
| 1253 | if (claimCapable && (TOMminusME >= (MMIOstart + 64))) { |
| 1254 | /* 64MB alignment: We'll lose some MBs here, if ME is on. */ |
| 1255 | TOMminusME &= ~(64 - 1); |
| 1256 | /* 64MB alignment: Loss will be reclaimed. */ |
| 1257 | TOLUD &= ~(64 - 1); |
| 1258 | if (TOMminusME > 4096) { |
| 1259 | REMAPbase = TOMminusME; |
| 1260 | REMAPlimit = REMAPbase + (4096 - TOLUD); |
| 1261 | } else { |
| 1262 | REMAPbase = 4096; |
| 1263 | REMAPlimit = REMAPbase + (TOMminusME - TOLUD); |
| 1264 | } |
| 1265 | TOUUD = REMAPlimit; |
| 1266 | /* REMAPlimit is an inclusive bound, all others exclusive. */ |
| 1267 | REMAPlimit -= 64; |
| 1268 | } |
| 1269 | |
| 1270 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, (TOM >> 7) & 0x1ff); |
| 1271 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, TOLUD << 4); |
| 1272 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, TOUUD); |
| 1273 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPBASE, (REMAPbase >> 6) & 0x03ff); |
| 1274 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_REMAPLIMIT, (REMAPlimit >> 6) & 0x03ff); |
| 1275 | |
| 1276 | /* Program channel mode. */ |
| 1277 | switch (mode) { |
| 1278 | case CHANNEL_MODE_SINGLE: |
| 1279 | printk(BIOS_DEBUG, "Memory configured in single-channel mode.\n"); |
| 1280 | MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; |
| 1281 | break; |
| 1282 | case CHANNEL_MODE_DUAL_ASYNC: |
Elyes HAOUAS | c9a717d | 2020-02-16 09:52:09 +0100 | [diff] [blame] | 1283 | printk(BIOS_DEBUG, "Memory configured in dual-channel asymmetric mode.\n"); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1284 | MCHBAR32(DCC_MCHBAR) &= ~DCC_INTERLEAVED; |
| 1285 | break; |
| 1286 | case CHANNEL_MODE_DUAL_INTERLEAVED: |
| 1287 | printk(BIOS_DEBUG, "Memory configured in dual-channel interleaved mode.\n"); |
| 1288 | MCHBAR32(DCC_MCHBAR) &= ~(DCC_NO_CHANXOR | (1 << 9)); |
| 1289 | MCHBAR32(DCC_MCHBAR) |= DCC_INTERLEAVED; |
| 1290 | break; |
| 1291 | } |
| 1292 | |
| 1293 | printk(BIOS_SPEW, "Memory map:\n" |
| 1294 | "TOM = %5uMB\n" |
| 1295 | "TOLUD = %5uMB\n" |
| 1296 | "TOUUD = %5uMB\n" |
| 1297 | "REMAP:\t base = %5uMB\n" |
Vladimir Serbinenko | 9907be4 | 2014-08-12 21:51:28 +0200 | [diff] [blame] | 1298 | "\t limit = %5uMB\n" |
| 1299 | "usedMEsize: %dMB\n", |
| 1300 | TOM, TOLUD, TOUUD, REMAPbase, REMAPlimit, usedMEsize); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1301 | } |
| 1302 | static void prejedec_memory_map(const dimminfo_t *const dimms, channel_mode_t mode) |
| 1303 | { |
| 1304 | /* Never use dual-interleaved mode in pre-jedec config. */ |
| 1305 | if (CHANNEL_MODE_DUAL_INTERLEAVED == mode) |
| 1306 | mode = CHANNEL_MODE_DUAL_ASYNC; |
| 1307 | |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1308 | program_memory_map(dimms, mode, 1, 0); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1309 | MCHBAR32(DCC_MCHBAR) |= DCC_NO_CHANXOR; |
| 1310 | } |
| 1311 | |
| 1312 | static void ddr3_select_clock_mux(const mem_clock_t ddr3clock, |
| 1313 | const dimminfo_t *const dimms, |
| 1314 | const stepping_t stepping) |
| 1315 | { |
| 1316 | const int clk1067 = (ddr3clock == MEM_CLOCK_1067MT); |
| 1317 | const int cardF[] = { CHANNEL_IS_CARDF(dimms, 0), CHANNEL_IS_CARDF(dimms, 1) }; |
| 1318 | |
| 1319 | int ch; |
| 1320 | |
| 1321 | if (stepping < STEPPING_B1) |
| 1322 | die("Stepping <B1 unsupported in clock-multiplexer selection.\n"); |
| 1323 | |
| 1324 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1325 | int mixed = 0; |
| 1326 | if ((1 == ch) && (!CHANNEL_IS_POPULATED(dimms, 0) || (cardF[0] != cardF[1]))) |
| 1327 | mixed = 4 << 11; |
| 1328 | const unsigned int b = 0x14b0 + (ch * 0x0100); |
| 1329 | MCHBAR32(b+0x1c) = (MCHBAR32(b+0x1c) & ~(7 << 11)) | |
| 1330 | ((( cardF[ch])?1:0) << 11) | mixed; |
| 1331 | MCHBAR32(b+0x18) = (MCHBAR32(b+0x18) & ~(7 << 11)) | mixed; |
| 1332 | MCHBAR32(b+0x14) = (MCHBAR32(b+0x14) & ~(7 << 11)) | |
| 1333 | (((!clk1067 && !cardF[ch])?0:1) << 11) | mixed; |
| 1334 | MCHBAR32(b+0x10) = (MCHBAR32(b+0x10) & ~(7 << 11)) | |
| 1335 | ((( clk1067 && !cardF[ch])?1:0) << 11) | mixed; |
| 1336 | MCHBAR32(b+0x0c) = (MCHBAR32(b+0x0c) & ~(7 << 11)) | |
| 1337 | ((( cardF[ch])?3:2) << 11) | mixed; |
| 1338 | MCHBAR32(b+0x08) = (MCHBAR32(b+0x08) & ~(7 << 11)) | |
| 1339 | (2 << 11) | mixed; |
| 1340 | MCHBAR32(b+0x04) = (MCHBAR32(b+0x04) & ~(7 << 11)) | |
| 1341 | (((!clk1067 && !cardF[ch])?2:3) << 11) | mixed; |
| 1342 | MCHBAR32(b+0x00) = (MCHBAR32(b+0x00) & ~(7 << 11)) | |
| 1343 | ((( clk1067 && !cardF[ch])?3:2) << 11) | mixed; |
| 1344 | } |
| 1345 | } |
| 1346 | static void ddr3_write_io_init(const mem_clock_t ddr3clock, |
| 1347 | const dimminfo_t *const dimms, |
| 1348 | const stepping_t stepping, |
| 1349 | const int sff) |
| 1350 | { |
| 1351 | const int a1step = stepping >= STEPPING_CONVERSION_A1; |
| 1352 | const int cardF[] = { CHANNEL_IS_CARDF(dimms, 0), CHANNEL_IS_CARDF(dimms, 1) }; |
| 1353 | |
| 1354 | int ch; |
| 1355 | |
| 1356 | if (stepping < STEPPING_B1) |
| 1357 | die("Stepping <B1 unsupported in write i/o initialization.\n"); |
| 1358 | if (sff) |
| 1359 | die("SFF platform unsupported in write i/o initialization.\n"); |
| 1360 | |
| 1361 | static const u32 ddr3_667_800_by_stepping_ddr3_and_card[][2][2][4] = { |
| 1362 | { /* Stepping B3 and below */ |
| 1363 | { /* 667 MHz */ |
| 1364 | { 0xa3255008, 0x26888209, 0x26288208, 0x6188040f }, |
| 1365 | { 0x7524240b, 0xa5255608, 0x232b8508, 0x5528040f }, |
| 1366 | }, |
| 1367 | { /* 800 MHz */ |
| 1368 | { 0xa6255308, 0x26888209, 0x212b7508, 0x6188040f }, |
| 1369 | { 0x7524240b, 0xa6255708, 0x132b7508, 0x5528040f }, |
| 1370 | }, |
| 1371 | }, |
| 1372 | { /* Conversion stepping A1 and above */ |
| 1373 | { /* 667 MHz */ |
| 1374 | { 0xc5257208, 0x26888209, 0x26288208, 0x6188040f }, |
| 1375 | { 0x7524240b, 0xc5257608, 0x232b8508, 0x5528040f }, |
| 1376 | }, |
| 1377 | { /* 800 MHz */ |
| 1378 | { 0xb6256308, 0x26888209, 0x212b7508, 0x6188040f }, |
| 1379 | { 0x7524240b, 0xb6256708, 0x132b7508, 0x5528040f }, |
| 1380 | } |
| 1381 | }}; |
| 1382 | |
| 1383 | static const u32 ddr3_1067_by_channel_and_card[][2][4] = { |
| 1384 | { /* Channel A */ |
| 1385 | { 0xb2254708, 0x002b7408, 0x132b8008, 0x7228060f }, |
| 1386 | { 0xb0255008, 0xa4254108, 0x4528b409, 0x9428230f }, |
| 1387 | }, |
| 1388 | { /* Channel B */ |
| 1389 | { 0xa4254208, 0x022b6108, 0x132b8208, 0x9228210f }, |
| 1390 | { 0x6024140b, 0x92244408, 0x252ba409, 0x9328360c }, |
| 1391 | }, |
| 1392 | }; |
| 1393 | |
| 1394 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1395 | if ((1 == ch) && CHANNEL_IS_POPULATED(dimms, 0) && (cardF[0] == cardF[1])) |
| 1396 | /* Only write if second channel population differs. */ |
| 1397 | continue; |
| 1398 | const u32 *const data = (ddr3clock != MEM_CLOCK_1067MT) |
| 1399 | ? ddr3_667_800_by_stepping_ddr3_and_card[a1step][2 - ddr3clock][cardF[ch]] |
| 1400 | : ddr3_1067_by_channel_and_card[ch][cardF[ch]]; |
| 1401 | MCHBAR32(CxWRTy_MCHBAR(ch, 0)) = data[0]; |
| 1402 | MCHBAR32(CxWRTy_MCHBAR(ch, 1)) = data[1]; |
| 1403 | MCHBAR32(CxWRTy_MCHBAR(ch, 2)) = data[2]; |
| 1404 | MCHBAR32(CxWRTy_MCHBAR(ch, 3)) = data[3]; |
| 1405 | } |
| 1406 | |
| 1407 | MCHBAR32(0x1490) = 0x00e70067; |
| 1408 | MCHBAR32(0x1494) = 0x000d8000; |
| 1409 | MCHBAR32(0x1590) = 0x00e70067; |
| 1410 | MCHBAR32(0x1594) = 0x000d8000; |
| 1411 | } |
| 1412 | static void ddr3_read_io_init(const mem_clock_t ddr3clock, |
| 1413 | const dimminfo_t *const dimms, |
| 1414 | const int sff) |
| 1415 | { |
| 1416 | int ch; |
| 1417 | |
| 1418 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1419 | u32 addr, tmp; |
| 1420 | const unsigned int base = 0x14b0 + (ch * 0x0100); |
| 1421 | for (addr = base + 0x1c; addr >= base; addr -= 4) { |
| 1422 | tmp = MCHBAR32(addr); |
| 1423 | tmp &= ~((3 << 25) | (1 << 8) | (7 << 16) | (0xf << 20) | (1 << 27)); |
| 1424 | tmp |= (1 << 27); |
| 1425 | switch (ddr3clock) { |
| 1426 | case MEM_CLOCK_667MT: |
| 1427 | tmp |= (1 << 16) | (4 << 20); |
| 1428 | break; |
| 1429 | case MEM_CLOCK_800MT: |
| 1430 | tmp |= (2 << 16) | (3 << 20); |
| 1431 | break; |
| 1432 | case MEM_CLOCK_1067MT: |
| 1433 | if (!sff) |
| 1434 | tmp |= (2 << 16) | (1 << 20); |
| 1435 | else |
| 1436 | tmp |= (2 << 16) | (2 << 20); |
| 1437 | break; |
| 1438 | default: |
| 1439 | die("Wrong clock"); |
| 1440 | } |
| 1441 | MCHBAR32(addr) = tmp; |
| 1442 | } |
| 1443 | } |
| 1444 | } |
| 1445 | |
| 1446 | static void memory_io_init(const mem_clock_t ddr3clock, |
| 1447 | const dimminfo_t *const dimms, |
| 1448 | const stepping_t stepping, |
| 1449 | const int sff) |
| 1450 | { |
| 1451 | u32 tmp; |
| 1452 | |
| 1453 | if (stepping < STEPPING_B1) |
| 1454 | die("Stepping <B1 unsupported in " |
| 1455 | "system-memory i/o initialization.\n"); |
| 1456 | |
| 1457 | tmp = MCHBAR32(0x1400); |
| 1458 | tmp &= ~(3<<13); |
| 1459 | tmp |= (1<<9) | (1<<13); |
| 1460 | MCHBAR32(0x1400) = tmp; |
| 1461 | |
| 1462 | tmp = MCHBAR32(0x140c); |
| 1463 | tmp &= ~(0xff | (1<<11) | (1<<12) | |
| 1464 | (1<<16) | (1<<18) | (1<<27) | (0xf<<28)); |
| 1465 | tmp |= (1<<7) | (1<<11) | (1<<16); |
| 1466 | switch (ddr3clock) { |
| 1467 | case MEM_CLOCK_667MT: |
| 1468 | tmp |= 9 << 28; |
| 1469 | break; |
| 1470 | case MEM_CLOCK_800MT: |
| 1471 | tmp |= 7 << 28; |
| 1472 | break; |
| 1473 | case MEM_CLOCK_1067MT: |
| 1474 | tmp |= 8 << 28; |
| 1475 | break; |
| 1476 | } |
| 1477 | MCHBAR32(0x140c) = tmp; |
| 1478 | |
| 1479 | MCHBAR32(0x1440) &= ~1; |
| 1480 | |
| 1481 | tmp = MCHBAR32(0x1414); |
| 1482 | tmp &= ~((1<<20) | (7<<11) | (0xf << 24) | (0xf << 16)); |
| 1483 | tmp |= (3<<11); |
| 1484 | switch (ddr3clock) { |
| 1485 | case MEM_CLOCK_667MT: |
| 1486 | tmp |= (2 << 24) | (10 << 16); |
| 1487 | break; |
| 1488 | case MEM_CLOCK_800MT: |
| 1489 | tmp |= (3 << 24) | (7 << 16); |
| 1490 | break; |
| 1491 | case MEM_CLOCK_1067MT: |
| 1492 | tmp |= (4 << 24) | (4 << 16); |
| 1493 | break; |
| 1494 | } |
| 1495 | MCHBAR32(0x1414) = tmp; |
| 1496 | |
| 1497 | MCHBAR32(0x1418) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27)); |
| 1498 | |
| 1499 | MCHBAR32(0x141c) &= ~((1<<3) | (1<<11) | (1<<19) | (1<<27)); |
| 1500 | |
| 1501 | MCHBAR32(0x1428) |= 1<<14; |
| 1502 | |
| 1503 | tmp = MCHBAR32(0x142c); |
| 1504 | tmp &= ~((0xf << 8) | (0x7 << 20) | 0xf | (0xf << 24)); |
| 1505 | tmp |= (0x3 << 20) | (5 << 24); |
| 1506 | switch (ddr3clock) { |
| 1507 | case MEM_CLOCK_667MT: |
| 1508 | tmp |= (2 << 8) | 0xc; |
| 1509 | break; |
| 1510 | case MEM_CLOCK_800MT: |
| 1511 | tmp |= (3 << 8) | 0xa; |
| 1512 | break; |
| 1513 | case MEM_CLOCK_1067MT: |
| 1514 | tmp |= (4 << 8) | 0x7; |
| 1515 | break; |
| 1516 | } |
| 1517 | MCHBAR32(0x142c) = tmp; |
| 1518 | |
| 1519 | tmp = MCHBAR32(0x400); |
| 1520 | tmp &= ~((3 << 4) | (3 << 16) | (3 << 30)); |
| 1521 | tmp |= (2 << 4) | (2 << 16); |
| 1522 | MCHBAR32(0x400) = tmp; |
| 1523 | |
| 1524 | MCHBAR32(0x404) &= ~(0xf << 20); |
| 1525 | |
| 1526 | MCHBAR32(0x40c) &= ~(1 << 6); |
| 1527 | |
| 1528 | tmp = MCHBAR32(0x410); |
| 1529 | tmp &= ~(7 << 28); |
| 1530 | tmp |= 2 << 28; |
| 1531 | MCHBAR32(0x410) = tmp; |
| 1532 | |
| 1533 | tmp = MCHBAR32(0x41c); |
| 1534 | tmp &= ~0x77; |
| 1535 | tmp |= 0x11; |
| 1536 | MCHBAR32(0x41c) = tmp; |
| 1537 | |
| 1538 | ddr3_select_clock_mux(ddr3clock, dimms, stepping); |
| 1539 | |
| 1540 | ddr3_write_io_init(ddr3clock, dimms, stepping, sff); |
| 1541 | |
| 1542 | ddr3_read_io_init(ddr3clock, dimms, sff); |
| 1543 | } |
| 1544 | |
| 1545 | static void jedec_init(const timings_t *const timings, |
| 1546 | const dimminfo_t *const dimms) |
| 1547 | { |
| 1548 | if ((timings->tWR < 5) || (timings->tWR > 12)) |
| 1549 | die("tWR value unsupported in Jedec initialization.\n"); |
| 1550 | |
| 1551 | /* Pre-jedec settings */ |
| 1552 | MCHBAR32(0x40) |= (1 << 1); |
| 1553 | MCHBAR32(0x230) |= (3 << 1); |
| 1554 | MCHBAR32(0x238) |= (3 << 24); |
| 1555 | MCHBAR32(0x23c) |= (3 << 24); |
| 1556 | |
| 1557 | /* Normal write pointer operation */ |
| 1558 | MCHBAR32(0x14f0) |= (1 << 9); |
| 1559 | MCHBAR32(0x15f0) |= (1 << 9); |
| 1560 | |
| 1561 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_CMD_NOP; |
| 1562 | |
| 1563 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1564 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); |
| 1565 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1566 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); |
| 1567 | udelay(2); |
| 1568 | |
| 1569 | /* 5 6 7 8 9 10 11 12 */ |
| 1570 | static const u8 wr_lut[] = { 1, 2, 3, 4, 5, 5, 6, 6 }; |
| 1571 | |
| 1572 | const int WL = ((timings->tWL - 5) & 7) << 6; |
| 1573 | const int ODT_120OHMS = (1 << 9); |
| 1574 | const int ODS_34OHMS = (1 << 4); |
| 1575 | const int WR = (wr_lut[timings->tWR - 5] & 7) << 12; |
| 1576 | const int DLL1 = 1 << 11; |
| 1577 | const int CAS = ((timings->CAS - 4) & 7) << 7; |
| 1578 | const int INTERLEAVED = 1 << 6;/* This is READ Burst Type == interleaved. */ |
| 1579 | |
| 1580 | int ch, r; |
| 1581 | FOR_EACH_POPULATED_RANK(dimms, ch, r) { |
| 1582 | /* We won't do this in dual-interleaved mode, |
Felix Held | 7f9f3d0 | 2019-06-07 14:47:28 +0200 | [diff] [blame] | 1583 | so don't care about the offset. |
| 1584 | Mirrored ranks aren't taken into account here. */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1585 | const u32 rankaddr = raminit_get_rank_addr(ch, r); |
Nico Huber | 0624f92 | 2017-04-15 15:57:28 +0200 | [diff] [blame] | 1586 | printk(BIOS_DEBUG, "JEDEC init @0x%08x\n", rankaddr); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1587 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1588 | read32((u32 *)(rankaddr | WL)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1589 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1590 | read32((u32 *)rankaddr); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1591 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(1); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1592 | read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1593 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1594 | read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1595 | MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1596 | read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED)); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1597 | } |
| 1598 | } |
| 1599 | |
| 1600 | static void ddr3_calibrate_zq(void) { |
| 1601 | udelay(2); |
| 1602 | |
| 1603 | u32 tmp = MCHBAR32(DCC_MCHBAR); |
| 1604 | tmp &= ~(7 << 16); |
| 1605 | tmp |= (5 << 16); /* ZQ calibration mode */ |
| 1606 | MCHBAR32(DCC_MCHBAR) = tmp; |
| 1607 | |
| 1608 | MCHBAR32(CxDRT6_MCHBAR(0)) |= (1 << 3); |
| 1609 | MCHBAR32(CxDRT6_MCHBAR(1)) |= (1 << 3); |
| 1610 | |
| 1611 | udelay(1); |
| 1612 | |
| 1613 | MCHBAR32(CxDRT6_MCHBAR(0)) &= ~(1 << 3); |
| 1614 | MCHBAR32(CxDRT6_MCHBAR(1)) &= ~(1 << 3); |
| 1615 | |
| 1616 | MCHBAR32(DCC_MCHBAR) |= (7 << 16); /* Normal operation */ |
| 1617 | } |
| 1618 | |
| 1619 | static void post_jedec_sequence(const int cores) { |
| 1620 | const int quadcore = cores == 4; |
| 1621 | |
| 1622 | MCHBAR32(0x0040) &= ~(1 << 1); |
| 1623 | MCHBAR32(0x0230) &= ~(3 << 1); |
| 1624 | MCHBAR32(0x0230) |= 1 << 15; |
| 1625 | MCHBAR32(0x0230) &= ~(1 << 19); |
| 1626 | MCHBAR32(0x1250) = 0x6c4; |
| 1627 | MCHBAR32(0x1350) = 0x6c4; |
| 1628 | MCHBAR32(0x1254) = 0x871a066d; |
| 1629 | MCHBAR32(0x1354) = 0x871a066d; |
| 1630 | MCHBAR32(0x0238) |= 1 << 26; |
| 1631 | MCHBAR32(0x0238) &= ~(3 << 24); |
| 1632 | MCHBAR32(0x0238) |= 1 << 23; |
| 1633 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 20)) | (3 << 20); |
| 1634 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 17)) | (6 << 17); |
| 1635 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 14)) | (6 << 14); |
| 1636 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 11)) | (6 << 11); |
| 1637 | MCHBAR32(0x0238) = (MCHBAR32(0x238) & ~(7 << 8)) | (6 << 8); |
| 1638 | MCHBAR32(0x023c) &= ~(3 << 24); |
| 1639 | MCHBAR32(0x023c) &= ~(1 << 23); |
| 1640 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 20)) | (3 << 20); |
| 1641 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 17)) | (6 << 17); |
| 1642 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 14)) | (6 << 14); |
| 1643 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 11)) | (6 << 11); |
| 1644 | MCHBAR32(0x023c) = (MCHBAR32(0x23c) & ~(7 << 8)) | (6 << 8); |
| 1645 | |
| 1646 | if (quadcore) { |
| 1647 | MCHBAR32(0xb14) |= (0xbfbf << 16); |
| 1648 | } |
| 1649 | } |
| 1650 | |
| 1651 | static void dram_optimizations(const timings_t *const timings, |
| 1652 | const dimminfo_t *const dimms) |
| 1653 | { |
| 1654 | int ch; |
| 1655 | |
| 1656 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) { |
| 1657 | const unsigned int mchbar = CxDRC1_MCHBAR(ch); |
| 1658 | u32 cxdrc1 = MCHBAR32(mchbar); |
| 1659 | cxdrc1 &= ~CxDRC1_SSDS_MASK; |
| 1660 | if (dimms[ch].ranks == 1) |
| 1661 | cxdrc1 |= CxDRC1_SS; |
| 1662 | else |
| 1663 | cxdrc1 |= CxDRC1_DS; |
| 1664 | MCHBAR32(mchbar) = cxdrc1; |
| 1665 | } |
| 1666 | } |
| 1667 | |
| 1668 | u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank) |
| 1669 | { |
| 1670 | if (!channel && !rank) |
| 1671 | return 0; /* Address of first rank */ |
| 1672 | |
| 1673 | /* Read the bound of the previous rank. */ |
| 1674 | if (rank > 0) { |
| 1675 | rank--; |
| 1676 | } else { |
| 1677 | rank = 3; /* Highest rank per channel */ |
| 1678 | channel--; |
| 1679 | } |
| 1680 | const u32 reg = MCHBAR32(CxDRBy_MCHBAR(channel, rank)); |
| 1681 | /* Bound is in 32MB. */ |
| 1682 | return ((reg & CxDRBy_BOUND_MASK(rank)) >> CxDRBy_BOUND_SHIFT(rank)) << 25; |
| 1683 | } |
| 1684 | |
| 1685 | void raminit_reset_readwrite_pointers(void) { |
| 1686 | MCHBAR32(0x1234) |= (1 << 6); |
| 1687 | MCHBAR32(0x1234) &= ~(1 << 6); |
| 1688 | MCHBAR32(0x1334) |= (1 << 6); |
| 1689 | MCHBAR32(0x1334) &= ~(1 << 6); |
| 1690 | MCHBAR32(0x14f0) &= ~(1 << 9); |
| 1691 | MCHBAR32(0x14f0) |= (1 << 9); |
| 1692 | MCHBAR32(0x14f0) |= (1 << 10); |
| 1693 | MCHBAR32(0x15f0) &= ~(1 << 9); |
| 1694 | MCHBAR32(0x15f0) |= (1 << 9); |
| 1695 | MCHBAR32(0x15f0) |= (1 << 10); |
| 1696 | } |
| 1697 | |
| 1698 | void raminit(sysinfo_t *const sysinfo, const int s3resume) |
| 1699 | { |
| 1700 | const dimminfo_t *const dimms = sysinfo->dimms; |
| 1701 | const timings_t *const timings = &sysinfo->selected_timings; |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1702 | |
| 1703 | int ch; |
| 1704 | u8 reg8; |
| 1705 | |
Arthur Heymans | 049347f | 2017-05-12 11:54:08 +0200 | [diff] [blame] | 1706 | timestamp_add_now(TS_BEFORE_INITRAM); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1707 | |
| 1708 | /* Wait for some bit, maybe TXT clear. */ |
| 1709 | if (sysinfo->txt_enabled) { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 1710 | while (!(read8((u8 *)0xfed40000) & (1 << 7))) {} |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1711 | } |
| 1712 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1713 | /* Collect information about DIMMs and find common settings. */ |
| 1714 | collect_dimm_config(sysinfo); |
| 1715 | |
| 1716 | /* Check for bad warm boot. */ |
| 1717 | reset_on_bad_warmboot(); |
| 1718 | |
| 1719 | |
| 1720 | /***** From now on, program according to collected infos: *****/ |
| 1721 | |
| 1722 | /* Program DRAM type. */ |
| 1723 | switch (sysinfo->spd_type) { |
| 1724 | case DDR2: |
| 1725 | MCHBAR8(0x1434) |= (1 << 7); |
| 1726 | break; |
| 1727 | case DDR3: |
| 1728 | MCHBAR8(0x1434) |= (3 << 0); |
| 1729 | break; |
| 1730 | } |
| 1731 | |
| 1732 | /* Program system memory frequency. */ |
| 1733 | set_system_memory_frequency(timings); |
| 1734 | /* Program IGD memory frequency. */ |
| 1735 | set_igd_memory_frequencies(sysinfo); |
| 1736 | |
| 1737 | /* Configure DRAM control mode for populated channels. */ |
| 1738 | configure_dram_control_mode(timings, dimms); |
| 1739 | |
| 1740 | /* Initialize RCOMP. */ |
Nico Huber | 5aaeb27 | 2015-12-30 00:17:27 +0100 | [diff] [blame] | 1741 | rcomp_initialization(sysinfo->stepping, sysinfo->sff); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1742 | |
| 1743 | /* Power-up DRAM. */ |
| 1744 | dram_powerup(s3resume); |
| 1745 | /* Program DRAM timings. */ |
| 1746 | dram_program_timings(timings); |
| 1747 | /* Program number of banks. */ |
| 1748 | dram_program_banks(dimms); |
| 1749 | /* Enable DRAM clock pairs for populated DIMMs. */ |
| 1750 | FOR_EACH_POPULATED_CHANNEL(dimms, ch) |
| 1751 | MCHBAR32(CxDCLKDIS_MCHBAR(ch)) |= CxDCLKDIS_ENABLE; |
| 1752 | |
| 1753 | /* Enable On-Die Termination. */ |
Nico Huber | 5aaeb27 | 2015-12-30 00:17:27 +0100 | [diff] [blame] | 1754 | odt_setup(timings, sysinfo->sff); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1755 | /* Miscellaneous settings. */ |
| 1756 | misc_settings(timings, sysinfo->stepping); |
| 1757 | /* Program clock crossing registers. */ |
| 1758 | clock_crossing_setup(timings->fsb_clock, timings->mem_clock, dimms); |
| 1759 | /* Program egress VC1 timings. */ |
| 1760 | vc1_program_timings(timings->fsb_clock); |
| 1761 | /* Perform system-memory i/o initialization. */ |
Nico Huber | 5aaeb27 | 2015-12-30 00:17:27 +0100 | [diff] [blame] | 1762 | memory_io_init(timings->mem_clock, dimms, |
| 1763 | sysinfo->stepping, sysinfo->sff); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1764 | |
| 1765 | /* Initialize memory map with dummy values of 128MB per rank with a |
| 1766 | page size of 4KB. This makes the JEDEC initialization code easier. */ |
| 1767 | prejedec_memory_map(dimms, timings->channel_mode); |
| 1768 | if (!s3resume) |
| 1769 | /* Perform JEDEC initialization of DIMMS. */ |
| 1770 | jedec_init(timings, dimms); |
| 1771 | /* Some programming steps after JEDEC initialization. */ |
| 1772 | post_jedec_sequence(sysinfo->cores); |
| 1773 | |
| 1774 | /* Announce normal operation, initialization completed. */ |
| 1775 | MCHBAR32(DCC_MCHBAR) |= (0x7 << 16) | (0x1 << 19); |
| 1776 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1777 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); |
| 1778 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1779 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); |
| 1780 | |
| 1781 | |
| 1782 | /* Take a breath (the reader). */ |
| 1783 | |
| 1784 | |
| 1785 | /* Perform ZQ calibration for DDR3. */ |
Nico Huber | 4a86b3b | 2019-08-11 16:28:05 +0200 | [diff] [blame] | 1786 | if (sysinfo->spd_type == DDR3) |
| 1787 | ddr3_calibrate_zq(); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1788 | |
| 1789 | /* Perform receive-enable calibration. */ |
| 1790 | raminit_receive_enable_calibration(timings, dimms); |
| 1791 | /* Lend clock values from receive-enable calibration. */ |
Jonathan Neuschäfer | 2f828eb | 2018-02-12 12:00:44 +0100 | [diff] [blame] | 1792 | MCHBAR32(CxDRT5_MCHBAR(0)) = |
| 1793 | (MCHBAR32(CxDRT5_MCHBAR(0)) & ~(0xf0)) | |
| 1794 | ((((MCHBAR32(CxDRT3_MCHBAR(0)) >> 7) - 1) & 0xf) << 4); |
| 1795 | MCHBAR32(CxDRT5_MCHBAR(1)) = |
| 1796 | (MCHBAR32(CxDRT5_MCHBAR(1)) & ~(0xf0)) | |
| 1797 | ((((MCHBAR32(CxDRT3_MCHBAR(1)) >> 7) - 1) & 0xf) << 4); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1798 | |
| 1799 | /* Perform read/write training for high clock rate. */ |
| 1800 | if (timings->mem_clock == MEM_CLOCK_1067MT) { |
| 1801 | raminit_read_training(dimms, s3resume); |
| 1802 | raminit_write_training(timings->mem_clock, dimms, s3resume); |
| 1803 | } |
| 1804 | |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1805 | igd_compute_ggc(sysinfo); |
| 1806 | |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1807 | /* Program final memory map (with real values). */ |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1808 | program_memory_map(dimms, timings->channel_mode, 0, sysinfo->ggc); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1809 | |
| 1810 | /* Some last optimizations. */ |
| 1811 | dram_optimizations(timings, dimms); |
| 1812 | |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 1813 | /* Mark raminit being finished. :-) */ |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1814 | u8 tmp8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2) & ~(1 << 7); |
| 1815 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, tmp8); |
Vladimir Serbinenko | 56ae8a0 | 2014-08-16 10:59:02 +0200 | [diff] [blame] | 1816 | |
| 1817 | raminit_thermal(sysinfo); |
| 1818 | init_igd(sysinfo); |
Arthur Heymans | 049347f | 2017-05-12 11:54:08 +0200 | [diff] [blame] | 1819 | |
| 1820 | timestamp_add_now(TS_AFTER_INITRAM); |
Patrick Georgi | 2efc880 | 2012-11-06 11:03:53 +0100 | [diff] [blame] | 1821 | } |