Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 2 | |
| 3 | #include <arch/ioapic.h> |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
Marc Jones | 8b522db | 2020-10-12 11:58:46 -0600 | [diff] [blame] | 5 | #include <console/debug.h> |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 6 | #include <cpu/x86/lapic.h> |
| 7 | #include <device/pci.h> |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 8 | #include <intelblocks/gpio.h> |
Subrata Banik | 1366e44 | 2020-09-29 13:55:50 +0530 | [diff] [blame] | 9 | #include <intelblocks/lpc_lib.h> |
Andrey Petrov | 4e48ac0 | 2020-04-30 14:08:19 -0700 | [diff] [blame] | 10 | #include <intelblocks/p2sb.h> |
Jonathan Zhang | 3172f98 | 2020-05-28 17:53:48 -0700 | [diff] [blame] | 11 | #include <soc/acpi.h> |
Marc Jones | 1f50084 | 2020-10-15 14:32:51 -0600 | [diff] [blame] | 12 | #include <soc/chip_common.h> |
Andrey Petrov | 8670e82 | 2020-03-30 12:25:06 -0700 | [diff] [blame] | 13 | #include <soc/cpu.h> |
Arthur Heymans | 3d80253 | 2020-11-12 21:17:56 +0100 | [diff] [blame] | 14 | #include <soc/pch.h> |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 15 | #include <soc/ramstage.h> |
Arthur Heymans | 0f91e9c | 2020-10-16 13:15:50 +0200 | [diff] [blame] | 16 | #include <soc/p2sb.h> |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 17 | #include <soc/soc_util.h> |
Marc Jones | 5851f9d | 2020-11-02 15:30:10 -0700 | [diff] [blame] | 18 | #include <soc/util.h> |
Arthur Heymans | 0f91e9c | 2020-10-16 13:15:50 +0200 | [diff] [blame] | 19 | #include <soc/pci_devs.h> |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 20 | |
Marc Jones | b9365ef | 2020-10-11 15:00:36 -0600 | [diff] [blame] | 21 | /* UPD parameters to be initialized before SiliconInit */ |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 22 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
| 23 | { |
Marc Jones | b9365ef | 2020-10-11 15:00:36 -0600 | [diff] [blame] | 24 | mainboard_silicon_init_params(silupd); |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 25 | } |
| 26 | |
Jonathan Zhang | 1ba42a9 | 2020-09-21 17:14:44 -0700 | [diff] [blame] | 27 | #if CONFIG(HAVE_ACPI_TABLES) |
| 28 | static const char *soc_acpi_name(const struct device *dev) |
| 29 | { |
| 30 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 31 | return "PC00"; |
| 32 | return NULL; |
| 33 | } |
| 34 | #endif |
| 35 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 36 | static struct device_operations pci_domain_ops = { |
| 37 | .read_resources = &pci_domain_read_resources, |
Marc Jones | 1f50084 | 2020-10-15 14:32:51 -0600 | [diff] [blame] | 38 | .set_resources = &xeonsp_pci_domain_set_resources, |
| 39 | .scan_bus = &xeonsp_pci_domain_scan_bus, |
Jonathan Zhang | 1ba42a9 | 2020-09-21 17:14:44 -0700 | [diff] [blame] | 40 | #if CONFIG(HAVE_ACPI_TABLES) |
Jonathan Zhang | 3172f98 | 2020-05-28 17:53:48 -0700 | [diff] [blame] | 41 | .write_acpi_tables = &northbridge_write_acpi_tables, |
Jonathan Zhang | 1ba42a9 | 2020-09-21 17:14:44 -0700 | [diff] [blame] | 42 | .acpi_name = soc_acpi_name |
| 43 | #endif |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 44 | }; |
| 45 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 46 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 47 | .read_resources = noop_read_resources, |
| 48 | .set_resources = noop_set_resources, |
Andrey Petrov | 8670e82 | 2020-03-30 12:25:06 -0700 | [diff] [blame] | 49 | .init = cpx_init_cpus, |
Jonathan Zhang | c110595 | 2020-06-03 15:55:28 -0700 | [diff] [blame] | 50 | .acpi_fill_ssdt = generate_cpu_entries, |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 51 | }; |
| 52 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 53 | struct pci_operations soc_pci_ops = { |
| 54 | .set_subsystem = pci_dev_set_subsystem, |
| 55 | }; |
| 56 | |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 57 | static void chip_enable_dev(struct device *dev) |
| 58 | { |
| 59 | /* Set the operations if it is a special bus type */ |
| 60 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 61 | dev->ops = &pci_domain_ops; |
| 62 | attach_iio_stacks(dev); |
| 63 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 64 | dev->ops = &cpu_bus_ops; |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 65 | } else if (dev->path.type == DEVICE_PATH_GPIO) { |
| 66 | block_gpio_enable(dev); |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 67 | } |
| 68 | } |
| 69 | |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 70 | static void chip_final(void *data) |
| 71 | { |
Arthur Heymans | 0f91e9c | 2020-10-16 13:15:50 +0200 | [diff] [blame] | 72 | /* Lock SBI */ |
| 73 | pci_or_config32(PCH_DEV_P2SB, P2SBC, SBILOCK); |
Arthur Heymans | 1918553 | 2020-10-27 17:40:22 +0100 | [diff] [blame] | 74 | |
| 75 | /* LOCK PAM */ |
| 76 | pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0); |
| 77 | |
| 78 | /* |
| 79 | * LOCK SMRAM |
| 80 | * According to the CedarIsland FSP Integration Guide this needs to |
| 81 | * be done with legacy 0xCF8/0xCFC IO ops. |
| 82 | */ |
| 83 | uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); |
| 84 | pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); |
| 85 | |
Andrey Petrov | 4e48ac0 | 2020-04-30 14:08:19 -0700 | [diff] [blame] | 86 | p2sb_hide(); |
Jonathan Zhang | bea1980 | 2020-04-13 19:34:53 -0700 | [diff] [blame] | 87 | |
| 88 | set_bios_init_completion(); |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 89 | } |
| 90 | |
| 91 | static void chip_init(void *data) |
| 92 | { |
| 93 | printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 94 | fsp_silicon_init(); |
Arthur Heymans | 3d80253 | 2020-11-12 21:17:56 +0100 | [diff] [blame] | 95 | override_hpet_ioapic_bdf(); |
Subrata Banik | 1366e44 | 2020-09-29 13:55:50 +0530 | [diff] [blame] | 96 | pch_enable_ioapic(); |
Arthur Heymans | 8346307 | 2020-12-16 11:30:40 +0100 | [diff] [blame] | 97 | pch_lock_dmictl(); |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 98 | setup_lapic(); |
Andrey Petrov | 4e48ac0 | 2020-04-30 14:08:19 -0700 | [diff] [blame] | 99 | p2sb_unhide(); |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | struct chip_operations soc_intel_xeon_sp_cpx_ops = { |
| 103 | CHIP_NAME("Intel Cooperlake-SP") |
| 104 | .enable_dev = chip_enable_dev, |
| 105 | .init = chip_init, |
Jonathan Zhang | 7919d61 | 2020-04-02 17:27:54 -0700 | [diff] [blame] | 106 | .final = chip_final, |
Andrey Petrov | 2e41075 | 2020-03-20 12:08:32 -0700 | [diff] [blame] | 107 | }; |