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Myles Watson707fad02009-10-23 18:22:27 +00001/*
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +00002 * This file is part of the coreboot project.
Myles Watson707fad02009-10-23 18:22:27 +00003 *
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +00004 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2005 Eswar Nallusamy, LANL
6 * Copyright (C) 2005 Tyan
7 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
8 * Copyright (C) 2007 coresystems GmbH
9 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
10 * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
11 * Copyright (C) 2008 VIA Technologies, Inc.
12 * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
Myles Watson707fad02009-10-23 18:22:27 +000013 *
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000014 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; version 2 of the License.
Myles Watson707fad02009-10-23 18:22:27 +000017 *
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000018 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
Myles Watson707fad02009-10-23 18:22:27 +000022 *
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000023 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 */
27
Stefan Reinauere08c29e2010-04-25 21:43:29 +000028#include <cpu/x86/stack.h>
Myles Watson707fad02009-10-23 18:22:27 +000029#include <cpu/x86/mtrr.h>
Alexandru Gagniuc5005bb062011-04-11 20:17:22 +000030#include <console/post_codes.h>
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000031
Uwe Hermann42926842010-09-30 23:15:36 +000032#define CacheSize CONFIG_DCACHE_RAM_SIZE
33#define CacheBase CONFIG_DCACHE_RAM_BASE
34
Stefan Reinauer7b0500c2011-01-19 06:54:42 +000035 /* Save the BIST result. */
36 movl %eax, %ebp
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000037
38CacheAsRam:
39
Stefan Reinauer7b0500c2011-01-19 06:54:42 +000040 /* Disable cache. */
41 movl %cr0, %eax
42 orl $(1 << 30), %eax
43 movl %eax, %cr0
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000044 invd
45
Uwe Hermann42926842010-09-30 23:15:36 +000046 /* Set the default memory type and enable fixed and variable MTRRs. */
Myles Watson707fad02009-10-23 18:22:27 +000047 movl $MTRRdefType_MSR, %ecx
48 xorl %edx, %edx
Uwe Hermann66d16872010-10-01 07:27:51 +000049 movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000050 wrmsr
51
Uwe Hermann42926842010-09-30 23:15:36 +000052 /* Clear all MTRRs. */
Myles Watson707fad02009-10-23 18:22:27 +000053 xorl %edx, %edx
Warren Turkal4ffde942010-10-12 06:13:40 +000054 movl $all_mtrr_msrs, %esi
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000055
Myles Watson707fad02009-10-23 18:22:27 +000056clear_fixed_var_mtrr:
57 lodsl (%esi), %eax
58 testl %eax, %eax
59 jz clear_fixed_var_mtrr_out
60
61 movl %eax, %ecx
62 xorl %eax, %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +000063 wrmsr
64
Myles Watson707fad02009-10-23 18:22:27 +000065 jmp clear_fixed_var_mtrr
Stefan Reinauer314e5512010-04-09 20:36:29 +000066
Warren Turkal4ffde942010-10-12 06:13:40 +000067all_mtrr_msrs:
68 /* fixed MTRR MSRs */
69 .long MTRRfix64K_00000_MSR
70 .long MTRRfix16K_80000_MSR
71 .long MTRRfix16K_A0000_MSR
72 .long MTRRfix4K_C0000_MSR
73 .long MTRRfix4K_C8000_MSR
74 .long MTRRfix4K_D0000_MSR
75 .long MTRRfix4K_D8000_MSR
76 .long MTRRfix4K_E0000_MSR
77 .long MTRRfix4K_E8000_MSR
78 .long MTRRfix4K_F0000_MSR
79 .long MTRRfix4K_F8000_MSR
Stefan Reinauer314e5512010-04-09 20:36:29 +000080
Warren Turkal4ffde942010-10-12 06:13:40 +000081 /* var MTRR MSRs */
82 .long MTRRphysBase_MSR(0)
83 .long MTRRphysMask_MSR(0)
84 .long MTRRphysBase_MSR(1)
85 .long MTRRphysMask_MSR(1)
86 .long MTRRphysBase_MSR(2)
87 .long MTRRphysMask_MSR(2)
88 .long MTRRphysBase_MSR(3)
89 .long MTRRphysMask_MSR(3)
90 .long MTRRphysBase_MSR(4)
91 .long MTRRphysMask_MSR(4)
92 .long MTRRphysBase_MSR(5)
93 .long MTRRphysMask_MSR(5)
94 .long MTRRphysBase_MSR(6)
95 .long MTRRphysMask_MSR(6)
96 .long MTRRphysBase_MSR(7)
97 .long MTRRphysMask_MSR(7)
98
Stefan Reinauer314e5512010-04-09 20:36:29 +000099 .long 0x000 /* NULL, end of table */
100
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000101clear_fixed_var_mtrr_out:
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000102 movl $MTRRphysBase_MSR(0), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000103 xorl %edx, %edx
Uwe Hermann42926842010-09-30 23:15:36 +0000104 movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000105 wrmsr
106
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000107 movl $MTRRphysMask_MSR(0), %ecx
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000108 /* This assumes we never access addresses above 2^36 in CAR. */
Uwe Hermann42926842010-09-30 23:15:36 +0000109 movl $0x0000000f, %edx
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000110 movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000111 wrmsr
112
Uwe Hermann42926842010-09-30 23:15:36 +0000113 /*
114 * Enable write base caching so we can do execute in place (XIP)
115 * on the flash ROM.
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000116 */
117 movl $MTRRphysBase_MSR(1), %ecx
118 xorl %edx, %edx
Uwe Hermann36455aa2010-10-02 20:51:29 +0000119 /*
Patrick Georgi1da10462011-10-28 20:28:03 +0200120 * IMPORTANT: The following calculation _must_ be done at runtime. See
Uwe Hermann36455aa2010-10-02 20:51:29 +0000121 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
122 */
Patrick Georgi1da10462011-10-28 20:28:03 +0200123 movl copy_and_run, %eax
124 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
Stefan Reinauerf11b81d2010-10-01 12:24:57 +0000125 orl $MTRR_TYPE_WRBACK, %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000126 wrmsr
127
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000128 movl $MTRRphysMask_MSR(1), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000129 movl $0x0000000f, %edx
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000130 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000131 wrmsr
132
Uwe Hermann66d16872010-10-01 07:27:51 +0000133 /* Set the default memory type and enable fixed and variable MTRRs. */
134 /* TODO: Or also enable fixed MTRRs? Bug in the code? */
Myles Watson707fad02009-10-23 18:22:27 +0000135 movl $MTRRdefType_MSR, %ecx
136 xorl %edx, %edx
Uwe Hermann66d16872010-10-01 07:27:51 +0000137 movl $(MTRRdefTypeEn), %eax
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000138 wrmsr
139
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000140 /* Enable cache. */
141 movl %cr0, %eax
142 andl $(~((1 << 30) | (1 << 29))), %eax
143 movl %eax, %cr0
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000144
Uwe Hermann42926842010-09-30 23:15:36 +0000145 /* Read the range with lodsl. */
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000146 cld
Myles Watson707fad02009-10-23 18:22:27 +0000147 movl $CacheBase, %esi
148 movl %esi, %edi
Uwe Hermann42926842010-09-30 23:15:36 +0000149 movl $(CacheSize >> 2), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000150 rep lodsl
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000151
Myles Watson707fad02009-10-23 18:22:27 +0000152 movl $CacheBase, %esi
153 movl %esi, %edi
154 movl $(CacheSize >> 2), %ecx
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000155
Uwe Hermann42926842010-09-30 23:15:36 +0000156 /*
157 * 0x5c5c5c5c is a memory test pattern.
158 * TODO: Check if everything works with the zero pattern as well.
159 */
160 /* xorl %eax, %eax */
161 xorl $0x5c5c5c5c, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000162 rep stosl
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000163
Kevin O'Connor24f83a72010-09-08 10:53:44 +0000164#ifdef CARTEST
Patrick Georgi1da10462011-10-28 20:28:03 +0200165 /*
166 * IMPORTANT: The following calculation _must_ be done at runtime. See
167 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
168 */
169 movl copy_and_run, %esi
170 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
Myles Watson707fad02009-10-23 18:22:27 +0000171 movl %esi, %edi
Uwe Hermann42926842010-09-30 23:15:36 +0000172 movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000173 rep lodsl
Kevin O'Connor24f83a72010-09-08 10:53:44 +0000174#endif
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000175
Uwe Hermann42926842010-09-30 23:15:36 +0000176 /*
177 * The key point of this CAR code is C7 cache does not turn into
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000178 * "no fill" mode, which is not compatible with general CAR code.
179 */
180
Myles Watson707fad02009-10-23 18:22:27 +0000181 movl $(CacheBase + CacheSize - 4), %eax
182 movl %eax, %esp
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000183
Myles Watson0bc61542009-10-17 13:25:07 +0000184#ifdef CARTEST
Stefan Reinaueraed99202010-06-07 08:29:36 +0000185testok:
186 post_code(0x40)
Myles Watson707fad02009-10-23 18:22:27 +0000187 xorl %edx, %edx
188 xorl %eax, %eax
Uwe Hermann42926842010-09-30 23:15:36 +0000189 movl $0x5c5c, %edx
190 pushl %edx
191 pushl %edx
192 pushl %edx
193 pushl %edx
194 pushl %edx
Myles Watson707fad02009-10-23 18:22:27 +0000195 popl %esi
196 popl %esi
197 popl %eax
198 popl %eax
199 popl %eax
Uwe Hermann42926842010-09-30 23:15:36 +0000200 cmpl %edx, %eax
201 jne stackerr
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000202#endif
203
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000204 /* Restore the BIST result. */
205 movl %ebp, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000206
Uwe Hermann42926842010-09-30 23:15:36 +0000207 /* We need to set EBP? No need. */
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000208 movl %esp, %ebp
Uwe Hermann42926842010-09-30 23:15:36 +0000209 pushl %eax /* BIST */
Stefan Reinauer314e5512010-04-09 20:36:29 +0000210 call main
Carl-Daniel Hailfinger92f3eda2008-10-03 15:17:47 +0000211
Stefan Reinauer14e22772010-04-27 06:56:47 +0000212 /*
Stefan Reinauer314e5512010-04-09 20:36:29 +0000213 * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
214 * get STACK up, we restore that. It is only needed if we
215 * want to go back.
216 */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000217
Uwe Hermann66d16872010-10-01 07:27:51 +0000218 /* We don't need CAR from now on. */
Stefan Reinauer314e5512010-04-09 20:36:29 +0000219
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000220 /* Disable cache. */
221 movl %cr0, %eax
222 orl $(1 << 30), %eax
223 movl %eax, %cr0
Stefan Reinauer314e5512010-04-09 20:36:29 +0000224
Uwe Hermann66d16872010-10-01 07:27:51 +0000225 /* Set the default memory type and enable variable MTRRs. */
226 /* TODO: Or also enable fixed MTRRs? Bug in the code? */
Uwe Hermann42926842010-09-30 23:15:36 +0000227 movl $MTRRdefType_MSR, %ecx
228 xorl %edx, %edx
Uwe Hermann66d16872010-10-01 07:27:51 +0000229 movl $(MTRRdefTypeEn), %eax
Stefan Reinauer314e5512010-04-09 20:36:29 +0000230 wrmsr
231
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000232 /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000233 movl $MTRRphysBase_MSR(0), %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000234 xorl %edx, %edx
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000235 movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax
Stefan Reinauer314e5512010-04-09 20:36:29 +0000236 wrmsr
Stefan Reinauer14e22772010-04-27 06:56:47 +0000237
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000238 movl $MTRRphysMask_MSR(0), %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000239 movl $0x0000000f, %edx /* AMD 40 bit 0xff */
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000240 movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
Stefan Reinauer14e22772010-04-27 06:56:47 +0000241 wrmsr
242
Uwe Hermann42926842010-09-30 23:15:36 +0000243 /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000244 movl $MTRRphysBase_MSR(1), %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000245 xorl %edx, %edx
Patrick Georgi1da10462011-10-28 20:28:03 +0200246 /*
247 * IMPORTANT: The following calculation _must_ be done at runtime. See
248 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
249 */
250 movl copy_and_run, %eax
251 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
Stefan Reinauerf11b81d2010-10-01 12:24:57 +0000252 orl $MTRR_TYPE_WRBACK, %eax
Stefan Reinauer314e5512010-04-09 20:36:29 +0000253 wrmsr
254
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000255 movl $MTRRphysMask_MSR(1), %ecx
Uwe Hermann42926842010-09-30 23:15:36 +0000256 xorl %edx, %edx
Kevin O'Connor5bb9fd62011-01-19 06:32:35 +0000257 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
Stefan Reinauer314e5512010-04-09 20:36:29 +0000258 wrmsr
259
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000260 /* Enable cache. */
261 movl %cr0, %eax
262 andl $(~((1 << 30) | (1 << 29))), %eax
263 movl %eax, %cr0
Stefan Reinauer314e5512010-04-09 20:36:29 +0000264 invd
265
Uwe Hermann42926842010-09-30 23:15:36 +0000266 /* Clear boot_complete flag. */
Stefan Reinauer314e5512010-04-09 20:36:29 +0000267 xorl %ebp, %ebp
268__main:
Alexandru Gagniuc5005bb062011-04-11 20:17:22 +0000269 post_code(POST_PREPARE_RAMSTAGE)
Uwe Hermann42926842010-09-30 23:15:36 +0000270 cld /* Clear direction flag. */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000271
Stefan Reinauer314e5512010-04-09 20:36:29 +0000272 movl %ebp, %esi
273
Uwe Hermann42926842010-09-30 23:15:36 +0000274 movl $ROMSTAGE_STACK, %esp
Stefan Reinauer314e5512010-04-09 20:36:29 +0000275 movl %esp, %ebp
Uwe Hermann42926842010-09-30 23:15:36 +0000276 pushl %esi
277 call copy_and_run
Stefan Reinauer314e5512010-04-09 20:36:29 +0000278
Stefan Reinauer14e22772010-04-27 06:56:47 +0000279.Lhlt:
Alexandru Gagniuc5005bb062011-04-11 20:17:22 +0000280 post_code(POST_DEAD_CODE)
Stefan Reinauer314e5512010-04-09 20:36:29 +0000281 hlt
282 jmp .Lhlt
283