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Myles Watson707fad02009-10-23 18:22:27 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Myles Watson707fad02009-10-23 18:22:27 +00003 *
Stefan Reinauer30584912010-08-14 20:38:17 +00004 * Copyright (C) 2000, 2007 Ronald G. Minnich <rminnich@gmail.com>
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +00005 * Copyright (C) 2005 Eswar Nallusamy, LANL
Stefan Reinauer30584912010-08-14 20:38:17 +00006 * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
7 * Copyright (C) 2007-2010 coresystems GmbH
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +00008 * Copyright (C) 2007 Carl-Daniel Hailfinger
Myles Watson707fad02009-10-23 18:22:27 +00009 *
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Myles Watson707fad02009-10-23 18:22:27 +000013 *
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
Myles Watson707fad02009-10-23 18:22:27 +000018 *
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +000019 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
Stefan Reinauere08c29e2010-04-25 21:43:29 +000024#include <cpu/x86/stack.h>
arch import user (historical)6ca76362005-07-06 17:17:25 +000025#include <cpu/x86/mtrr.h>
Stefan Reinauer30584912010-08-14 20:38:17 +000026#include <cpu/x86/lapic_def.h>
Alexandru Gagniuc5005bb062011-04-11 20:17:22 +000027#include <cpu/x86/post_code.h>
arch import user (historical)6ca76362005-07-06 17:17:25 +000028
Uwe Hermann42926842010-09-30 23:15:36 +000029#define CacheSize CONFIG_DCACHE_RAM_SIZE
30#define CacheBase (0xd0000 - CacheSize)
31
Stefan Reinauer7b0500c2011-01-19 06:54:42 +000032 /* Save the BIST result. */
33 movl %eax, %ebp
arch import user (historical)6ca76362005-07-06 17:17:25 +000034
35CacheAsRam:
Uwe Hermann42926842010-09-30 23:15:36 +000036 /* Check whether the processor has HT capability. */
Myles Watson707fad02009-10-23 18:22:27 +000037 movl $01, %eax
38 cpuid
39 btl $28, %edx
40 jnc NotHtProcessor
41 bswapl %ebx
42 cmpb $01, %bh
43 jbe NotHtProcessor
arch import user (historical)fb07bf42005-07-06 18:17:43 +000044
Uwe Hermann42926842010-09-30 23:15:36 +000045 /*
46 * It is a HT processor. Send SIPI to the other logical processor
47 * within this processor so that the CAR related common system
48 * registers are programmed accordingly.
49 */
arch import user (historical)fb07bf42005-07-06 18:17:43 +000050
Uwe Hermann42926842010-09-30 23:15:36 +000051 /*
52 * Use some register that is common to both logical processors
53 * as semaphore. Refer Appendix B, Vol.3.
54 */
Myles Watson707fad02009-10-23 18:22:27 +000055 xorl %eax, %eax
56 xorl %edx, %edx
Stefan Reinauer30584912010-08-14 20:38:17 +000057 movl $MTRRfix64K_00000_MSR, %ecx
Myles Watson707fad02009-10-23 18:22:27 +000058 wrmsr
arch import user (historical)fb07bf42005-07-06 18:17:43 +000059
Uwe Hermann42926842010-09-30 23:15:36 +000060 /*
61 * Figure out the logical AP's APIC ID; the following logic will
62 * work only for processors with 2 threads.
63 * Refer to Vol 3. Table 7-1 for details about this logic.
64 */
Myles Watson707fad02009-10-23 18:22:27 +000065 movl $0xFEE00020, %esi
66 movl (%esi), %ebx
67 andl $0xFF000000, %ebx
68 bswapl %ebx
69 btl $0, %ebx
70 jnc LogicalAP0
71 andb $0xFE, %bl
72 jmp Send_SIPI
arch import user (historical)fb07bf42005-07-06 18:17:43 +000073LogicalAP0:
Myles Watson707fad02009-10-23 18:22:27 +000074 orb $0x01, %bl
arch import user (historical)fb07bf42005-07-06 18:17:43 +000075Send_SIPI:
Uwe Hermann42926842010-09-30 23:15:36 +000076 bswapl %ebx /* EBX - logical AP's APIC ID. */
arch import user (historical)fb07bf42005-07-06 18:17:43 +000077
Uwe Hermann42926842010-09-30 23:15:36 +000078 /*
79 * Fill up the IPI command registers in the Local APIC mapped to
80 * default address and issue SIPI to the other logical processor
81 * within this processor die.
82 */
arch import user (historical)fb07bf42005-07-06 18:17:43 +000083Retry_SIPI:
Myles Watson707fad02009-10-23 18:22:27 +000084 movl %ebx, %eax
85 movl $0xFEE00310, %esi
86 movl %eax, (%esi)
arch import user (historical)fb07bf42005-07-06 18:17:43 +000087
Uwe Hermann42926842010-09-30 23:15:36 +000088 /* SIPI vector - F900:0000 */
Myles Watson707fad02009-10-23 18:22:27 +000089 movl $0x000006F9, %eax
90 movl $0xFEE00300, %esi
91 movl %eax, (%esi)
arch import user (historical)fb07bf42005-07-06 18:17:43 +000092
Myles Watson707fad02009-10-23 18:22:27 +000093 movl $0x30, %ecx
arch import user (historical)fb07bf42005-07-06 18:17:43 +000094SIPI_Delay:
Myles Watson707fad02009-10-23 18:22:27 +000095 pause
96 decl %ecx
97 jnz SIPI_Delay
arch import user (historical)fb07bf42005-07-06 18:17:43 +000098
Myles Watson707fad02009-10-23 18:22:27 +000099 movl (%esi), %eax
100 andl $0x00001000, %eax
101 jnz Retry_SIPI
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000102
Uwe Hermann42926842010-09-30 23:15:36 +0000103 /* Wait for the Logical AP to complete initialization. */
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000104LogicalAP_SIPINotdone:
Stefan Reinauer30584912010-08-14 20:38:17 +0000105 movl $MTRRfix64K_00000_MSR, %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000106 rdmsr
107 orl %eax, %eax
108 jz LogicalAP_SIPINotdone
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000109
110NotHtProcessor:
Uwe Hermann42926842010-09-30 23:15:36 +0000111 /* Set the default memory type and enable fixed and variable MTRRs. */
Myles Watson707fad02009-10-23 18:22:27 +0000112 movl $MTRRdefType_MSR, %ecx
113 xorl %edx, %edx
Uwe Hermann66d16872010-10-01 07:27:51 +0000114 movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
Myles Watson707fad02009-10-23 18:22:27 +0000115 wrmsr
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000116
Uwe Hermann42926842010-09-30 23:15:36 +0000117 /* Clear all MTRRs. */
Myles Watson707fad02009-10-23 18:22:27 +0000118 xorl %edx, %edx
Warren Turkal4ffde942010-10-12 06:13:40 +0000119 movl $all_mtrr_msrs, %esi
arch import user (historical)6ca76362005-07-06 17:17:25 +0000120
arch import user (historical)6ca76362005-07-06 17:17:25 +0000121clear_fixed_var_mtrr:
Myles Watson707fad02009-10-23 18:22:27 +0000122 lodsl (%esi), %eax
123 testl %eax, %eax
124 jz clear_fixed_var_mtrr_out
arch import user (historical)6ca76362005-07-06 17:17:25 +0000125
Myles Watson707fad02009-10-23 18:22:27 +0000126 movl %eax, %ecx
127 xorl %eax, %eax
128 wrmsr
arch import user (historical)6ca76362005-07-06 17:17:25 +0000129
Myles Watson707fad02009-10-23 18:22:27 +0000130 jmp clear_fixed_var_mtrr
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000131
Warren Turkal4ffde942010-10-12 06:13:40 +0000132all_mtrr_msrs:
133 /* fixed MTRR MSRs */
134 .long MTRRfix64K_00000_MSR
135 .long MTRRfix16K_80000_MSR
136 .long MTRRfix16K_A0000_MSR
137 .long MTRRfix4K_C0000_MSR
138 .long MTRRfix4K_C8000_MSR
139 .long MTRRfix4K_D0000_MSR
140 .long MTRRfix4K_D8000_MSR
141 .long MTRRfix4K_E0000_MSR
142 .long MTRRfix4K_E8000_MSR
143 .long MTRRfix4K_F0000_MSR
144 .long MTRRfix4K_F8000_MSR
Uwe Hermann42926842010-09-30 23:15:36 +0000145
Warren Turkal4ffde942010-10-12 06:13:40 +0000146 /* var MTRR MSRs */
147 .long MTRRphysBase_MSR(0)
148 .long MTRRphysMask_MSR(0)
149 .long MTRRphysBase_MSR(1)
150 .long MTRRphysMask_MSR(1)
151 .long MTRRphysBase_MSR(2)
152 .long MTRRphysMask_MSR(2)
153 .long MTRRphysBase_MSR(3)
154 .long MTRRphysMask_MSR(3)
155 .long MTRRphysBase_MSR(4)
156 .long MTRRphysMask_MSR(4)
157 .long MTRRphysBase_MSR(5)
158 .long MTRRphysMask_MSR(5)
159 .long MTRRphysBase_MSR(6)
160 .long MTRRphysMask_MSR(6)
161 .long MTRRphysBase_MSR(7)
162 .long MTRRphysMask_MSR(7)
163
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000164 .long 0x000 /* NULL, end of table */
165
arch import user (historical)6ca76362005-07-06 17:17:25 +0000166clear_fixed_var_mtrr_out:
167
Uwe Hermann42926842010-09-30 23:15:36 +0000168/*
169 * 0x06 is the WB IO type for a given 4k segment.
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000170 * segs is the number of 4k segments in the area of the particular
Stefan Reinauer30584912010-08-14 20:38:17 +0000171 * register we want to use for CAR.
172 * reg is the register where the IO type should be stored.
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000173 */
174.macro extractmask segs, reg
175.if \segs <= 0
Uwe Hermann42926842010-09-30 23:15:36 +0000176 /*
177 * The xorl here is superfluous because at the point of first execution
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000178 * of this macro, %eax and %edx are cleared. Later invocations of this
179 * macro will have a monotonically increasing segs parameter.
180 */
181 xorl \reg, \reg
182.elseif \segs == 1
Stefan Reinauer30584912010-08-14 20:38:17 +0000183 movl $0x06000000, \reg /* WB IO type */
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000184.elseif \segs == 2
Stefan Reinauer30584912010-08-14 20:38:17 +0000185 movl $0x06060000, \reg /* WB IO type */
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000186.elseif \segs == 3
Stefan Reinauer30584912010-08-14 20:38:17 +0000187 movl $0x06060600, \reg /* WB IO type */
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000188.elseif \segs >= 4
Stefan Reinauer30584912010-08-14 20:38:17 +0000189 movl $0x06060606, \reg /* WB IO type */
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000190.endif
191.endm
192
Uwe Hermann42926842010-09-30 23:15:36 +0000193/*
Uwe Hermann66d16872010-10-01 07:27:51 +0000194 * carsize is the cache size in bytes we want to use for CAR.
Uwe Hermann42926842010-09-30 23:15:36 +0000195 * windowoffset is the 32k-aligned window into CAR size.
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000196 */
197.macro simplemask carsize, windowoffset
Carl-Daniel Hailfinger4afb7fb2008-04-04 15:02:45 +0000198 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
199 extractmask gas_bug_workaround, %eax
200 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
201 extractmask gas_bug_workaround, %edx
Uwe Hermann42926842010-09-30 23:15:36 +0000202 /*
203 * Without the gas bug workaround, the entire macro would consist
204 * only of the two lines below:
205 * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
206 * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
207 */
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000208.endm
209
210#if CacheSize > 0x10000
211#error Invalid CAR size, must be at most 64k.
212#endif
213#if CacheSize < 0x1000
214#error Invalid CAR size, must be at least 4k. This is a processor limitation.
215#endif
216#if (CacheSize & (0x1000 - 1))
217#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
218#endif
219
Myles Watson707fad02009-10-23 18:22:27 +0000220#if CacheSize > 0x8000
Uwe Hermann42926842010-09-30 23:15:36 +0000221 /* Enable caching for 32K-64K using fixed MTRR. */
Stefan Reinauer30584912010-08-14 20:38:17 +0000222 movl $MTRRfix4K_C0000_MSR, %ecx
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000223 simplemask CacheSize, 0x8000
Myles Watson707fad02009-10-23 18:22:27 +0000224 wrmsr
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000225#endif
226
Uwe Hermann42926842010-09-30 23:15:36 +0000227 /* Enable caching for 0-32K using fixed MTRR. */
Stefan Reinauer30584912010-08-14 20:38:17 +0000228 movl $MTRRfix4K_C8000_MSR, %ecx
Carl-Daniel Hailfinger4d1aa0a2008-01-08 17:06:38 +0000229 simplemask CacheSize, 0
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000230 wrmsr
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000231
Stefan Reinauer08670622009-06-30 15:17:49 +0000232#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
Uwe Hermann1d36d6d2010-09-30 21:22:40 +0000233
Uwe Hermann42926842010-09-30 23:15:36 +0000234 /*
235 * Enable write base caching so we can do execute in place (XIP)
236 * on the flash ROM.
Myles Watson707fad02009-10-23 18:22:27 +0000237 */
Stefan Reinauer30584912010-08-14 20:38:17 +0000238 movl $MTRRphysBase_MSR(1), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000239 xorl %edx, %edx
Uwe Hermann36455aa2010-10-02 20:51:29 +0000240 /*
Patrick Georgi1da10462011-10-28 20:28:03 +0200241 * IMPORTANT: The following calculation _must_ be done at runtime. See
Uwe Hermann36455aa2010-10-02 20:51:29 +0000242 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
243 */
Patrick Georgi1da10462011-10-28 20:28:03 +0200244 movl copy_and_run, %eax
245 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
Myles Watsonc7e982b2010-10-01 15:16:20 +0000246 orl $MTRR_TYPE_WRBACK, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000247 wrmsr
arch import user (historical)6ca76362005-07-06 17:17:25 +0000248
Stefan Reinauer30584912010-08-14 20:38:17 +0000249 movl $MTRRphysMask_MSR(1), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000250 movl $0x0000000f, %edx
Stefan Reinauer139e6f92011-04-14 20:06:30 +0000251 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
Myles Watson707fad02009-10-23 18:22:27 +0000252 wrmsr
Stefan Reinauer08670622009-06-30 15:17:49 +0000253#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
arch import user (historical)6ca76362005-07-06 17:17:25 +0000254
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000255 /* Enable cache. */
256 movl %cr0, %eax
257 andl $(~((1 << 30) | (1 << 29))), %eax
258 movl %eax, %cr0
arch import user (historical)6ca76362005-07-06 17:17:25 +0000259
Uwe Hermann42926842010-09-30 23:15:36 +0000260 /* Read the range with lodsl. */
Myles Watson707fad02009-10-23 18:22:27 +0000261 movl $CacheBase, %esi
arch import user (historical)6ca76362005-07-06 17:17:25 +0000262 cld
Myles Watson707fad02009-10-23 18:22:27 +0000263 movl $(CacheSize >> 2), %ecx
264 rep lodsl
arch import user (historical)6ca76362005-07-06 17:17:25 +0000265
Uwe Hermann42926842010-09-30 23:15:36 +0000266 /* Clear the range. */
Myles Watson707fad02009-10-23 18:22:27 +0000267 movl $CacheBase, %edi
268 movl $(CacheSize >> 2), %ecx
269 xorl %eax, %eax
270 rep stosl
arch import user (historical)6ca76362005-07-06 17:17:25 +0000271
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000272#if 0
Uwe Hermann42926842010-09-30 23:15:36 +0000273 /* Check the cache as ram. */
Myles Watson707fad02009-10-23 18:22:27 +0000274 movl $CacheBase, %esi
Uwe Hermann42926842010-09-30 23:15:36 +0000275 movl $(CacheSize >> 2), %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000276.xin1:
277 movl %esi, %eax
278 movl %eax, (%esi)
279 decl %ecx
280 je .xout1
281 add $4, %esi
282 jmp .xin1
283.xout1:
arch import user (historical)6ca76362005-07-06 17:17:25 +0000284
Myles Watson707fad02009-10-23 18:22:27 +0000285 movl $CacheBase, %esi
Uwe Hermann42926842010-09-30 23:15:36 +0000286 // movl $(CacheSize >> 2), %ecx
287 movl $4, %ecx
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000288.xin1x:
Myles Watson707fad02009-10-23 18:22:27 +0000289 movl %esi, %eax
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000290
Myles Watson707fad02009-10-23 18:22:27 +0000291 movl $0x4000, %edx
292 movb %ah, %al
293.testx1:
Uwe Hermann42926842010-09-30 23:15:36 +0000294 outb %al, $0x80
Myles Watson707fad02009-10-23 18:22:27 +0000295 decl %edx
Uwe Hermann42926842010-09-30 23:15:36 +0000296 jnz .testx1
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000297
Myles Watson707fad02009-10-23 18:22:27 +0000298 movl (%esi), %eax
Uwe Hermann42926842010-09-30 23:15:36 +0000299 cmpb 0xff, %al
300 je .xin2 /* Don't show. */
Myles Watson707fad02009-10-23 18:22:27 +0000301
302 movl $0x4000, %edx
arch import user (historical)6ca76362005-07-06 17:17:25 +0000303.testx2:
Uwe Hermann42926842010-09-30 23:15:36 +0000304 outb %al, $0x80
Myles Watson707fad02009-10-23 18:22:27 +0000305 decl %edx
Uwe Hermann42926842010-09-30 23:15:36 +0000306 jnz .testx2
Myles Watson707fad02009-10-23 18:22:27 +0000307
Uwe Hermann42926842010-09-30 23:15:36 +0000308.xin2:
309 decl %ecx
Myles Watson707fad02009-10-23 18:22:27 +0000310 je .xout1x
311 add $4, %esi
312 jmp .xin1x
arch import user (historical)6ca76362005-07-06 17:17:25 +0000313.xout1x:
arch import user (historical)6ca76362005-07-06 17:17:25 +0000314#endif
arch import user (historical)6ca76362005-07-06 17:17:25 +0000315
Myles Watson707fad02009-10-23 18:22:27 +0000316 movl $(CacheBase + CacheSize - 4), %eax
317 movl %eax, %esp
arch import user (historical)6ca76362005-07-06 17:17:25 +0000318lout:
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000319 /* Restore the BIST result. */
320 movl %ebp, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000321
Uwe Hermann42926842010-09-30 23:15:36 +0000322 /* We need to set EBP? No need. */
arch import user (historical)6ca76362005-07-06 17:17:25 +0000323 movl %esp, %ebp
Uwe Hermann42926842010-09-30 23:15:36 +0000324 pushl %eax /* BIST */
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000325 call main
arch import user (historical)6ca76362005-07-06 17:17:25 +0000326
Uwe Hermann66d16872010-10-01 07:27:51 +0000327 /* We don't need CAR from now on. */
Uwe Hermann42926842010-09-30 23:15:36 +0000328
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000329 /* Disable cache. */
330 movl %cr0, %eax
331 orl $(1 << 30), %eax
332 movl %eax, %cr0
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000333
Uwe Hermann42926842010-09-30 23:15:36 +0000334 /* Clear sth. */
Stefan Reinauer30584912010-08-14 20:38:17 +0000335 movl $MTRRfix4K_C8000_MSR, %ecx
336 xorl %edx, %edx
337 xorl %eax, %eax
Myles Watson707fad02009-10-23 18:22:27 +0000338 wrmsr
arch import user (historical)fb07bf42005-07-06 18:17:43 +0000339
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000340#if CONFIG_DCACHE_RAM_SIZE > 0x8000
Stefan Reinauer30584912010-08-14 20:38:17 +0000341 movl $MTRRfix4K_C0000_MSR, %ecx
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000342 wrmsr
343#endif
344
Uwe Hermann42926842010-09-30 23:15:36 +0000345 /*
346 * Set the default memory type and disable fixed
347 * and enable variable MTRRs.
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000348 */
Stefan Reinauer30584912010-08-14 20:38:17 +0000349 movl $MTRRdefType_MSR, %ecx
350 xorl %edx, %edx
Stefan Reinauer139e6f92011-04-14 20:06:30 +0000351 movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */
Stefan Reinauer30584912010-08-14 20:38:17 +0000352 wrmsr
353
Stefan Reinauer7b0500c2011-01-19 06:54:42 +0000354 /* Enable cache. */
355 movl %cr0, %eax
356 andl $(~((1 << 30) | (1 << 29))), %eax
357 movl %eax, %cr0
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000358
Uwe Hermann42926842010-09-30 23:15:36 +0000359 /* Clear boot_complete flag. */
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000360 xorl %ebp, %ebp
361__main:
Alexandru Gagniuc5005bb062011-04-11 20:17:22 +0000362 post_code(POST_PREPARE_RAMSTAGE)
Uwe Hermann42926842010-09-30 23:15:36 +0000363 cld /* Clear direction flag. */
Stefan Reinauer14e22772010-04-27 06:56:47 +0000364
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000365 movl %ebp, %esi
366
Stefan Reinauer30584912010-08-14 20:38:17 +0000367 movl $ROMSTAGE_STACK, %esp
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000368 movl %esp, %ebp
Stefan Reinauer30584912010-08-14 20:38:17 +0000369 pushl %esi
370 call copy_and_run
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000371
Stefan Reinauer14e22772010-04-27 06:56:47 +0000372.Lhlt:
Alexandru Gagniuc5005bb062011-04-11 20:17:22 +0000373 post_code(POST_DEAD_CODE)
Myles Watson707fad02009-10-23 18:22:27 +0000374 hlt
Stefan Reinauerccdd20a2010-04-14 07:47:07 +0000375 jmp .Lhlt
376